From nobody Mon Jan 26 22:46:13 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAF9133A717 for ; Mon, 26 Jan 2026 16:23:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769444590; cv=none; b=Fiz0EuByWE7oAi6QP4kKQ0Fql2jM5GbzrUco5MGexfU4L9d/1QU69sxblHsRmZN/EvtOxcYKYIa93wPIYrBWX9wwBbprYosi2B0XB3vSGFfy9XWlPolpPUth8N/jRsvuV+c4Hq+jvzC18crt2eepyN3gza4HUJG1A235tRvOBjM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769444590; c=relaxed/simple; bh=WJ7NFZ18n9I/IRO2Qd1eUYKElHlcJcBM+w65YsSWMsk=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=HuUujBSw4GSsYKoVC+nY/iCQCoGIa9uUnpTVEF2106V9MHHWyXn29BwZHMXeXB6LyV14Q/EH2Cvy4rEq/FHMWhfqSpQTHrUeuT/9D5ExojoqZgtXigQ8RPAXoe583R55vXbPjRJEYeeL3obu/OSsLn6tJn7lMGBQwVyfquRJlHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=TyYLHlmv; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="TyYLHlmv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1769444588; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=nsIQrgfp5jLTggR6149XJxSxNh6TrKVXLrfEpKoLZdw=; b=TyYLHlmvEdMM4f1DEg297z0j2kW4q18ZpnVLgVjMGzcav0IN+iidi/EGxQK3Fa8GoSKqbL 4ZbDkuWYdWEf2HehA8IUDVZLUCSB+ZkUTRTHe996K/XnuXsAOnOYz7zhy/3AnytvIXoG0m Hxifrqzt6UG2WOfL1evLql9z9f/QdJ8= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-544-AR7DDxPWOnmR01VolRz0iQ-1; Mon, 26 Jan 2026 11:23:03 -0500 X-MC-Unique: AR7DDxPWOnmR01VolRz0iQ-1 X-Mimecast-MFC-AGG-ID: AR7DDxPWOnmR01VolRz0iQ_1769444581 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 898B919775E6; Mon, 26 Jan 2026 16:23:00 +0000 (UTC) Received: from p16v.redhat.com (unknown [10.45.226.107]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E734F19560B2; Mon, 26 Jan 2026 16:22:54 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Donald Hunter , Jakub Kicinski , "David S. Miller" , Eric Dumazet , Paolo Abeni , Simon Horman , Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Prathosh Satish , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Andrew Lunn , Petr Oros , linux-kernel@vger.kernel.org (open list), linux-rdma@vger.kernel.org (open list:MELLANOX MLX5 core VPI driver) Subject: [PATCH net-next] dpll: expose fractional frequency offset in ppt Date: Mon, 26 Jan 2026 17:22:51 +0100 Message-ID: <20260126162253.27890-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" Currently, the dpll subsystem exports the fractional frequency offset (FFO) in parts per million (ppm). This granularity is insufficient for high-precision synchronization scenarios which often require parts per trillion (ppt) resolution. Add a new netlink attribute DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT to expose the FFO in ppt. Update the dpll netlink core to expect the driver-provided FFO value to be in ppt. To maintain backward compatibility with existing userspace tools, populate the legacy DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET attribute by dividing the new ppt value by 1,000,000. Update the zl3073x and mlx5 drivers to provide the FFO value in ppt: - zl3073x: adjust the fixed-point calculation to produce ppt (10^12) instead of ppm (10^6). - mlx5: scale the existing ppm value by 1,000,000. Signed-off-by: Ivan Vecera --- Documentation/netlink/specs/dpll.yaml | 11 +++++++++++ drivers/dpll/dpll_netlink.c | 10 +++++++++- drivers/dpll/zl3073x/core.c | 7 +++++-- drivers/net/ethernet/mellanox/mlx5/core/dpll.c | 2 +- include/uapi/linux/dpll.h | 1 + 5 files changed, 27 insertions(+), 4 deletions(-) diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/= specs/dpll.yaml index b55afa77eac4b..3dd48a32f7837 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -446,6 +446,16 @@ attribute-sets: doc: | Granularity of phase adjustment, in picoseconds. The value of phase adjustment must be a multiple of this granularity. + - + name: fractional-frequency-offset-ppt + type: sint + doc: | + The FFO (Fractional Frequency Offset) of the pin with respect to + the nominal frequency. + Value =3D (frequency_measured - frequency_nominal) / frequency_n= ominal + Value is in PPT (parts per trillion, 10^-12). + Note: This attribute provides higher resolution than the standard + fractional-frequency-offset (which is in PPM). =20 - name: pin-parent-device @@ -628,6 +638,7 @@ operations: - phase-adjust-max - phase-adjust - fractional-frequency-offset + - fractional-frequency-offset-ppt - esync-frequency - esync-frequency-supported - esync-pulse diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index 499bca460b1e1..904199ddd1781 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -389,7 +389,15 @@ static int dpll_msg_add_ffo(struct sk_buff *msg, struc= t dpll_pin *pin, return 0; return ret; } - return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, ffo); + /* Put the FFO value in PPM to preserve compatibility with older + * programs. + */ + ret =3D nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, + div_s64(ffo, 1000000)); + if (ret) + return -EMSGSIZE; + return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, + ffo); } =20 static int diff --git a/drivers/dpll/zl3073x/core.c b/drivers/dpll/zl3073x/core.c index 383e2397dd033..63bd97181b9ee 100644 --- a/drivers/dpll/zl3073x/core.c +++ b/drivers/dpll/zl3073x/core.c @@ -710,8 +710,11 @@ zl3073x_ref_ffo_update(struct zl3073x_dev *zldev) if (rc) return rc; =20 - /* Convert to ppm -> ffo =3D (10^6 * value) / 2^32 */ - zldev->ref[i].ffo =3D mul_s64_u64_shr(value, 1000000, 32); + /* Convert to ppt + * ffo =3D (10^12 * value) / 2^32 + * ffo =3D ( 5^12 * value) / 2^20 + */ + zldev->ref[i].ffo =3D mul_s64_u64_shr(value, 244140625, 20); } =20 return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/e= thernet/mellanox/mlx5/core/dpll.c index 1e5522a194839..3ea8a1766ae28 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c @@ -136,7 +136,7 @@ mlx5_dpll_pin_ffo_get(struct mlx5_dpll_synce_status *sy= nce_status, { if (!synce_status->oper_freq_measure) return -ENODATA; - *ffo =3D synce_status->frequency_diff; + *ffo =3D 1000000LL * synce_status->frequency_diff; return 0; } =20 diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h index b7ff9c44f9aa0..de0005f28e5c5 100644 --- a/include/uapi/linux/dpll.h +++ b/include/uapi/linux/dpll.h @@ -253,6 +253,7 @@ enum dpll_a_pin { DPLL_A_PIN_ESYNC_PULSE, DPLL_A_PIN_REFERENCE_SYNC, DPLL_A_PIN_PHASE_ADJUST_GRAN, + DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, =20 __DPLL_A_PIN_MAX, DPLL_A_PIN_MAX =3D (__DPLL_A_PIN_MAX - 1) --=20 2.52.0