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([82.78.167.31]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435b1c246ecsm29715049f8f.10.2026.01.26.02.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 02:32:13 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, p.zabel@pengutronix.de, geert+renesas@glider.be, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH 7/7] dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor Date: Mon, 26 Jan 2026 12:31:55 +0200 Message-ID: <20260126103155.2644586-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260126103155.2644586-1-claudiu.beznea.uj@bp.renesas.com> References: <20260126103155.2644586-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea On an RZ/G2L-based system, it has been observed that when the DMA channels for all enabled IPs are active (TX and RX for one serial IP, TX and RX for one audio IP, and TX and RX for one SPI IP), shortly after all of them are started, the system can become irrecoverably blocked. In one debug session the system did not block, and the DMA HW registers were inspected. It was found that the DER (Descriptor Error) bit in the CHSTAT register for one of the SPI DMA channels was set. According to the RZ/G2L HW Manual, Rev. 1.30, chapter 14.4.7 Channel Status Register n/nS (CHSTAT_n/nS), description of the DER bit, the DER bit is set when the LV (Link Valid) value loaded with a descriptor in link mode is 0. This means that the DMA engine has loaded an invalid descriptor (as defined in Table 14.14, Header Area, of the same manual). The same chapter states that when a descriptor error occurs, the transfer is stopped, but no DMA error interrupt is generated. Set the LE bit on the last descriptor of a transfer. This informs the DMA engine that this is the final descriptor for the transfer. Signed-off-by: Claudiu Beznea --- drivers/dma/sh/rz-dmac.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 8f3e2719e639..3a77a560fcd5 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -206,6 +206,7 @@ struct rz_dmac { =20 /* LINK MODE DESCRIPTOR */ #define HEADER_LV BIT(0) +#define HEADER_LE BIT(1) #define HEADER_WBD BIT(2) =20 #define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16 @@ -383,7 +384,7 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_d= mac_chan *channel) lmdesc->chcfg =3D chcfg; lmdesc->chitvl =3D 0; lmdesc->chext =3D 0; - lmdesc->header =3D HEADER_LV; + lmdesc->header =3D HEADER_LV | HEADER_LE; =20 rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_= no); =20 @@ -425,7 +426,7 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct r= z_dmac_chan *channel) lmdesc->chext =3D 0; if (i =3D=3D (sg_len - 1)) { lmdesc->chcfg =3D (channel->chcfg & ~CHCFG_DEM); - lmdesc->header =3D HEADER_LV; + lmdesc->header =3D HEADER_LV | HEADER_LE; } else { lmdesc->chcfg =3D channel->chcfg; lmdesc->header =3D HEADER_LV; --=20 2.43.0