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([82.78.167.31]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435b1c246ecsm29715049f8f.10.2026.01.26.02.32.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 02:32:08 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, p.zabel@pengutronix.de, geert+renesas@glider.be, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH 4/7] dmaengine: sh: rz-dmac: Add cyclic DMA support Date: Mon, 26 Jan 2026 12:31:52 +0200 Message-ID: <20260126103155.2644586-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260126103155.2644586-1-claudiu.beznea.uj@bp.renesas.com> References: <20260126103155.2644586-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add cyclic DMA support to the RZ DMAC driver. A per-channel status bit is introduced to mark cyclic channels and is set during the DMA prepare callback. The IRQ handler checks this status bit and calls vchan_cyclic_callback() accordingly. Signed-off-by: Claudiu Beznea --- drivers/dma/sh/rz-dmac.c | 137 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 133 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 4bc7ea9566fd..ab5f49a0b9f2 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -35,6 +35,7 @@ enum rz_dmac_prep_type { RZ_DMAC_DESC_MEMCPY, RZ_DMAC_DESC_SLAVE_SG, + RZ_DMAC_DESC_CYCLIC, }; =20 struct rz_lmdesc { @@ -59,6 +60,7 @@ struct rz_dmac_desc { /* For slave sg */ struct scatterlist *sg; unsigned int sgcount; + u32 start_lmdesc; }; =20 #define to_rz_dmac_desc(d) container_of(d, struct rz_dmac_desc, vd) @@ -67,10 +69,12 @@ struct rz_dmac_desc { * enum rz_dmac_chan_status: RZ DMAC channel status * @RZ_DMAC_CHAN_STATUS_ENABLED: Channel is enabled * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callba= cks + * @RZ_DMAC_CHAN_STATUS_CYCLIC: Channel is cyclic */ enum rz_dmac_chan_status { RZ_DMAC_CHAN_STATUS_ENABLED, RZ_DMAC_CHAN_STATUS_PAUSED, + RZ_DMAC_CHAN_STATUS_CYCLIC, }; =20 struct rz_dmac_chan { @@ -194,6 +198,7 @@ struct rz_dmac { =20 /* LINK MODE DESCRIPTOR */ #define HEADER_LV BIT(0) +#define HEADER_WBD BIT(2) =20 #define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16 #define RZ_DMAC_MAX_CHANNELS 16 @@ -426,6 +431,60 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct = rz_dmac_chan *channel) rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); } =20 +static void rz_dmac_prepare_descs_for_cyclic(struct rz_dmac_chan *channel) +{ + struct dma_chan *chan =3D &channel->vc.chan; + struct rz_dmac *dmac =3D to_rz_dmac(chan->device); + struct rz_dmac_desc *d =3D channel->desc; + size_t period_len =3D d->sgcount; + struct rz_lmdesc *lmdesc; + size_t buf_len =3D d->len; + size_t periods =3D buf_len / period_len; + u32 start_lmdesc; + + lockdep_assert_held(&channel->vc.lock); + + channel->chcfg |=3D CHCFG_SEL(channel->index) | CHCFG_DMS; + + if (d->direction =3D=3D DMA_DEV_TO_MEM) { + channel->chcfg |=3D CHCFG_SAD; + channel->chcfg &=3D ~CHCFG_REQD; + } else { + channel->chcfg |=3D CHCFG_DAD | CHCFG_REQD; + } + + lmdesc =3D channel->lmdesc.tail; + start_lmdesc =3D channel->lmdesc.base_dma + + (sizeof(struct rz_lmdesc) * (lmdesc - channel->lmdesc.base)); + d->start_lmdesc =3D start_lmdesc; + + for (size_t i =3D 0; i < periods; i++) { + if (d->direction =3D=3D DMA_DEV_TO_MEM) { + lmdesc->sa =3D d->src; + lmdesc->da =3D d->dest + (i * period_len); + } else { + lmdesc->sa =3D d->src + (i * period_len); + lmdesc->da =3D d->dest; + } + + lmdesc->tb =3D period_len; + lmdesc->chitvl =3D 0; + lmdesc->chext =3D 0; + lmdesc->chcfg =3D channel->chcfg; + lmdesc->header =3D HEADER_LV | HEADER_WBD; + + if (i =3D=3D periods - 1) + lmdesc->nxla =3D start_lmdesc; + + if (++lmdesc >=3D (channel->lmdesc.base + DMAC_NR_LMDESC)) + lmdesc =3D channel->lmdesc.base; + } + + channel->lmdesc.tail =3D lmdesc; + + rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); +} + static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan) { struct rz_dmac_desc *d =3D chan->desc; @@ -446,6 +505,10 @@ static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan) rz_dmac_prepare_descs_for_slave_sg(chan); break; =20 + case RZ_DMAC_DESC_CYCLIC: + rz_dmac_prepare_descs_for_cyclic(chan); + break; + default: return -EINVAL; } @@ -580,6 +643,52 @@ rz_dmac_prep_slave_sg(struct dma_chan *chan, struct sc= atterlist *sgl, return vchan_tx_prep(&channel->vc, &desc->vd, flags); } =20 +static struct dma_async_tx_descriptor * +rz_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction direction, + unsigned long flags) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + size_t periods =3D buf_len / period_len; + struct rz_dmac_desc *desc; + + if (!is_slave_direction(direction)) + return NULL; + + if (periods > DMAC_NR_LMDESC) + return NULL; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + if (list_empty(&channel->ld_free)) + return NULL; + + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC)) + return NULL; + + channel->status |=3D BIT(RZ_DMAC_CHAN_STATUS_CYCLIC); + + desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + + desc->type =3D RZ_DMAC_DESC_CYCLIC; + desc->sgcount =3D period_len; + desc->len =3D buf_len; + desc->direction =3D direction; + + if (direction =3D=3D DMA_DEV_TO_MEM) { + desc->src =3D channel->src_per_address; + desc->dest =3D buf_addr; + } else { + desc->src =3D buf_addr; + desc->dest =3D channel->dst_per_address; + } + + list_move_tail(channel->ld_free.next, &channel->ld_queue); + } + + return vchan_tx_prep(&channel->vc, &desc->vd, flags); +} + static int rz_dmac_terminate_all(struct dma_chan *chan) { struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); @@ -731,9 +840,18 @@ static u32 rz_dmac_calculate_residue_bytes_in_vd(struc= t rz_dmac_chan *channel) } =20 /* Calculate residue from next lmdesc to end of virtual desc */ - while (lmdesc->chcfg & CHCFG_DEM) { - residue +=3D lmdesc->tb; - lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC)) { + struct rz_dmac_desc *desc =3D channel->desc; + + while (lmdesc->nxla !=3D desc->start_lmdesc) { + residue +=3D lmdesc->tb; + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + } + } else { + while (lmdesc->chcfg & CHCFG_DEM) { + residue +=3D lmdesc->tb; + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + } } =20 dev_dbg(dmac->dev, "%s: VD residue is %u\n", __func__, residue); @@ -972,7 +1090,15 @@ static irqreturn_t rz_dmac_irq_handler_thread(int irq= , void *dev_id) } =20 desc =3D list_first_entry(&channel->ld_active, struct rz_dmac_desc, node); - vchan_cookie_complete(&desc->vd); + + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC)) { + desc =3D channel->desc; + vchan_cyclic_callback(&desc->vd); + goto out; + } else { + vchan_cookie_complete(&desc->vd); + } + list_move_tail(channel->ld_active.next, &channel->ld_free); if (!list_empty(&channel->ld_queue)) { desc =3D list_first_entry(&channel->ld_queue, struct rz_dmac_desc, @@ -1239,6 +1365,8 @@ static int rz_dmac_probe(struct platform_device *pdev) engine =3D &dmac->engine; dma_cap_set(DMA_SLAVE, engine->cap_mask); dma_cap_set(DMA_MEMCPY, engine->cap_mask); + dma_cap_set(DMA_CYCLIC, engine->cap_mask); + engine->directions =3D BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); engine->residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL); rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL); @@ -1250,6 +1378,7 @@ static int rz_dmac_probe(struct platform_device *pdev) engine->device_tx_status =3D rz_dmac_tx_status; engine->device_prep_slave_sg =3D rz_dmac_prep_slave_sg; engine->device_prep_dma_memcpy =3D rz_dmac_prep_dma_memcpy; + engine->device_prep_dma_cyclic =3D rz_dmac_prep_dma_cyclic; engine->device_config =3D rz_dmac_config; engine->device_terminate_all =3D rz_dmac_terminate_all; engine->device_issue_pending =3D rz_dmac_issue_pending; --=20 2.43.0