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Mon, 26 Jan 2026 02:15:12 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] ARM: tegra: lg-x3: complete video device graph Date: Mon, 26 Jan 2026 12:10:18 +0200 Message-ID: <20260126101018.24450-5-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126101018.24450-1-clamor95@gmail.com> References: <20260126101018.24450-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add front and rear camera nodes and interlink them with Tegra CSI and VI. Adjust camera PMIC voltages to better fit requirements and fix the focuser node. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 28 ++++ arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 46 ++++++ arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 154 +++++++++++++++++-- 3 files changed, 214 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p880.dts index cc14e6dca770..1b21d7628c8c 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -12,6 +12,18 @@ aliases { mmc2 =3D &sdmmc1; /* WiFi */ }; =20 + host1x@50000000 { + vi@54080000 { + csi@800 { + /delete-node/ channel@1; + }; + + ports { + /delete-node/ port@1; + }; + }; + }; + pinmux@70000868 { pinctrl-names =3D "default"; pinctrl-0 =3D <&state_default>; @@ -116,6 +128,22 @@ rmi4-f11@11 { }; }; =20 + i2c@7000c500 { + camera-pmic@7d { + vt_1v2_front: ldo1 { + regulator-name =3D "vt_1v2_dig"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + vt_2v7_front: ldo2 { + regulator-name =3D "vt_2v7_vana"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2700000>; + }; + }; + }; + spi@7000dc00 { dsi@2 { /* diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p895.dts index 414117fd4382..896639599c12 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -118,6 +118,52 @@ rmi4-f1a@1a { }; }; =20 + i2c@7000c500 { + /* Aptina 1/6" HD SOC (MT9M114) */ + front-camera@48 { + compatible =3D "onnn,mt9m114"; + reg =3D <0x48>; + + clocks =3D <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios =3D <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>; + + vddio-supply =3D <&vio_1v8_front>; + vdd-supply =3D <&vt_1v8_front>; + vaa-supply =3D <&vt_2v8_front>; + + orientation =3D <0>; /* Front camera */ + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates =3D <24000000>; + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + front_camera_output: endpoint { + bus-type =3D ; + link-frequencies =3D /bits/ 64 <384000000>; + remote-endpoint =3D <&csib_input>; + }; + }; + }; + + camera-pmic@7d { + vt_1v8_front: ldo1 { + regulator-name =3D "vt_1v8_dig"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + vt_2v8_front: ldo2 { + regulator-name =3D "vt_2v8_vana"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + }; + }; + spi@7000dc00 { dsi@2 { /* diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dt= s/nvidia/tegra30-lg-x3.dtsi index 768e201456d8..178e4bb153d3 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include =20 @@ -74,6 +75,91 @@ trustzone@bfe00000 { }; =20 host1x@50000000 { + vi@54080000 { + status =3D "okay"; + + csi@800 { + status =3D "okay"; + + avdd-dsi-csi-supply =3D <&avdd_dsi_csi>; + + /* CSI-A */ + channel@0 { + reg =3D <0>; + + nvidia,mipi-calibrate =3D <&csi 0>; /* CSIA pad */ + + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + csia_input: endpoint { + data-lanes =3D <1 2>; + remote-endpoint =3D <&rear_camera_output>; + }; + }; + + port@1 { + reg =3D <1>; + + csia_output: endpoint { + remote-endpoint =3D <&vi_ppa_input>; + }; + }; + }; + + /* CSI-B */ + channel@1 { + reg =3D <1>; + + nvidia,mipi-calibrate =3D <&csi 1>; /* CSIB pad */ + + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + csib_input: endpoint { + data-lanes =3D <3>; + remote-endpoint =3D <&front_camera_output>; + }; + }; + + port@1 { + reg =3D <1>; + + csib_output: endpoint { + remote-endpoint =3D <&vi_ppb_input>; + }; + }; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + vi_ppa_input: endpoint { + remote-endpoint =3D <&csia_output>; + }; + }; + + port@1 { + reg =3D <1>; + + vi_ppb_input: endpoint { + remote-endpoint =3D <&csib_output>; + }; + }; + }; + }; + lcd: dc@54200000 { rgb { status =3D "okay"; @@ -1112,29 +1198,68 @@ dw9714: coil@c { compatible =3D "dongwoon,dw9714"; reg =3D <0x0c>; =20 - enable-gpios =3D <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + powerdown-gpios =3D <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; =20 vcc-supply =3D <&vcc_focuser>; }; =20 + /* SONY IMX111 1/4" BSI */ + rear-camera@10 { + compatible =3D "sony,imx111"; + reg =3D <0x10>; + + clocks =3D <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios =3D <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>; + + iovdd-supply =3D <&vio_1v8_rear>; + dvdd-supply =3D <&vdd_1v2_rear>; + avdd-supply =3D <&vdd_2v7_rear>; + + orientation =3D <1>; /* Rear camera */ + rotation =3D <90>; + + nvmem =3D <&m24c08>; + lens-focus =3D <&dw9714>; + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates =3D <24000000>; + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + rear_camera_output: endpoint { + data-lanes =3D <1 2>; + bus-type =3D ; + link-frequencies =3D /bits/ 64 <542400000>; + remote-endpoint =3D <&csia_input>; + }; + }; + }; + + /* rear camera sensor eeprom */ + m24c08: eeprom@50 { + compatible =3D "st,m24c08", "atmel,24c08"; + reg =3D <0x50>; + + /* if high then WP is on, if low then off */ + wp-gpios =3D <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; + + /* it is not OTP but writing is unwanted */ + read-only; + pagesize =3D <16>; + num-addresses =3D <1>; + + vcc-supply =3D <&vio_1v8_rear>; + }; + camera-pmic@7d { compatible =3D "ti,lp8720"; reg =3D <0x7d>; =20 enable-gpios =3D <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; =20 - vt_1v2_front: ldo1 { - regulator-name =3D "vt_1v2_dig"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - }; - - vt_2v7_front: ldo2 { - regulator-name =3D "vt_2v7_vana"; - regulator-min-microvolt =3D <2700000>; - regulator-max-microvolt =3D <2700000>; - }; - vdd_2v7_rear: ldo3 { regulator-name =3D "8m_2v7_vana"; regulator-min-microvolt =3D <2700000>; @@ -1348,10 +1473,11 @@ vdd_1v2_mhl: ldo7 { maxim,active-fps-source =3D ; }; =20 - ldo8 { + avdd_dsi_csi: ldo8 { regulator-name =3D "avdd_dsi_csi"; regulator-min-microvolt =3D <1200000>; regulator-max-microvolt =3D <1200000>; + regulator-boot-on; =20 maxim,active-fps-source =3D ; }; --=20 2.51.0