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Mon, 26 Jan 2026 02:15:09 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] ARM: tegra: lg-x3: add panel and bridge nodes Date: Mon, 26 Jan 2026 12:10:15 +0200 Message-ID: <20260126101018.24450-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126101018.24450-1-clamor95@gmail.com> References: <20260126101018.24450-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RGB-DSI bridge and panel nodes to LG Optimus 4X and Vu device trees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 23 ++++++ arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 27 +++++++ arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 81 +++++++++++++++++++- 3 files changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p880.dts index c6ef0a20c19f..cc14e6dca770 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -116,6 +116,29 @@ rmi4-f11@11 { }; }; =20 + spi@7000dc00 { + dsi@2 { + /* + * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible =3D "jdi,dx12d100vm0eaa", "renesas,r69328"; + reg =3D <1>; + + reset-gpios =3D <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + vdd-supply =3D <&vcc_3v0_lcd>; + vddio-supply =3D <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&bridge_output>; + }; + }; + }; + }; + }; + memory-controller@7000f000 { emc-timings-0 { /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p895.dts index e32fafc7f5e0..ab8f5cf317bf 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -112,6 +112,33 @@ rmi4-f11@11 { }; }; =20 + spi@7000dc00 { + dsi@2 { + /* + * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible =3D "koe,tx13d100vm0eaa", "renesas,r61307"; + reg =3D <1>; + + reset-gpios =3D <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + renesas,gamma =3D <3>; + renesas,column-inversion; + renesas,contrast; + + vcc-supply =3D <&vcc_3v0_lcd>; + iovcc-supply =3D <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&bridge_output>; + }; + }; + }; + }; + }; + memory-controller@7000f000 { emc-timings-2 { /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dt= s/nvidia/tegra30-lg-x3.dtsi index 909260a5d0fb..6eea8eacd7d5 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -20,6 +20,8 @@ aliases { rtc0 =3D &pmic; rtc1 =3D "/rtc@7000e000"; =20 + display0 =3D &lcd; + serial0 =3D &uartd; /* Console */ serial1 =3D &uartc; /* Bluetooth */ serial2 =3D &uartb; /* GPS */ @@ -71,6 +73,21 @@ trustzone@bfe00000 { }; }; =20 + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status =3D "okay"; + + port { + dpi_output: endpoint { + remote-endpoint =3D <&bridge_input>; + bus-width =3D <24>; + }; + }; + }; + }; + }; + vde@6001a000 { assigned-clocks =3D <&tegra_car TEGRA30_CLK_VDE>; assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>; @@ -1357,7 +1374,58 @@ spi@7000dc00 { status =3D "okay"; spi-max-frequency =3D <25000000>; =20 - /* DSI bridge */ + dsi@2 { + compatible =3D "solomon,ssd2825"; + reg =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + spi-max-frequency =3D <1000000>; + + spi-cpha; + spi-cpol; + + reset-gpios =3D <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>; + + dvdd-supply =3D <&vdd_1v2_rgb>; + avdd-supply =3D <&vdd_1v2_rgb>; + vddio-supply =3D <&vdd_1v8_vio>; + + solomon,hs-zero-delay-ns =3D <300>; + solomon,hs-prep-delay-ns =3D <65>; + + clocks =3D <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_EXTERN3>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + assigned-clock-rates =3D <24000000>; + + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_EXTERN3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + bridge_input: endpoint { + remote-endpoint =3D <&dpi_output>; + bus-width =3D <24>; + }; + }; + + port@1 { + reg =3D <1>; + + bridge_output: endpoint { + remote-endpoint =3D <&panel_input>; + }; + }; + }; + }; }; =20 pmc@7000e400 { @@ -1617,6 +1685,17 @@ vdd_1v8_sen: regulator-sen1v8 { vin-supply =3D <&vdd_3v3_vbat>; }; =20 + vdd_1v2_rgb: regulator-rgb1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_1v2_rgb"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + gpio =3D <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_3v3_vbat>; + }; + vcc_3v0_lcd: regulator-lcd3v { compatible =3D "regulator-fixed"; regulator-name =3D "vcc_3v0_lcd"; --=20 2.51.0