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Mon, 26 Jan 2026 02:15:09 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] ARM: tegra: lg-x3: add panel and bridge nodes Date: Mon, 26 Jan 2026 12:10:15 +0200 Message-ID: <20260126101018.24450-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126101018.24450-1-clamor95@gmail.com> References: <20260126101018.24450-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RGB-DSI bridge and panel nodes to LG Optimus 4X and Vu device trees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 23 ++++++ arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 27 +++++++ arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 81 +++++++++++++++++++- 3 files changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p880.dts index c6ef0a20c19f..cc14e6dca770 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -116,6 +116,29 @@ rmi4-f11@11 { }; }; =20 + spi@7000dc00 { + dsi@2 { + /* + * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible =3D "jdi,dx12d100vm0eaa", "renesas,r69328"; + reg =3D <1>; + + reset-gpios =3D <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + vdd-supply =3D <&vcc_3v0_lcd>; + vddio-supply =3D <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&bridge_output>; + }; + }; + }; + }; + }; + memory-controller@7000f000 { emc-timings-0 { /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p895.dts index e32fafc7f5e0..ab8f5cf317bf 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -112,6 +112,33 @@ rmi4-f11@11 { }; }; =20 + spi@7000dc00 { + dsi@2 { + /* + * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible =3D "koe,tx13d100vm0eaa", "renesas,r61307"; + reg =3D <1>; + + reset-gpios =3D <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + renesas,gamma =3D <3>; + renesas,column-inversion; + renesas,contrast; + + vcc-supply =3D <&vcc_3v0_lcd>; + iovcc-supply =3D <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&bridge_output>; + }; + }; + }; + }; + }; + memory-controller@7000f000 { emc-timings-2 { /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dt= s/nvidia/tegra30-lg-x3.dtsi index 909260a5d0fb..6eea8eacd7d5 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -20,6 +20,8 @@ aliases { rtc0 =3D &pmic; rtc1 =3D "/rtc@7000e000"; =20 + display0 =3D &lcd; + serial0 =3D &uartd; /* Console */ serial1 =3D &uartc; /* Bluetooth */ serial2 =3D &uartb; /* GPS */ @@ -71,6 +73,21 @@ trustzone@bfe00000 { }; }; =20 + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status =3D "okay"; + + port { + dpi_output: endpoint { + remote-endpoint =3D <&bridge_input>; + bus-width =3D <24>; + }; + }; + }; + }; + }; + vde@6001a000 { assigned-clocks =3D <&tegra_car TEGRA30_CLK_VDE>; assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>; @@ -1357,7 +1374,58 @@ spi@7000dc00 { status =3D "okay"; spi-max-frequency =3D <25000000>; =20 - /* DSI bridge */ + dsi@2 { + compatible =3D "solomon,ssd2825"; + reg =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + spi-max-frequency =3D <1000000>; + + spi-cpha; + spi-cpol; + + reset-gpios =3D <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>; + + dvdd-supply =3D <&vdd_1v2_rgb>; + avdd-supply =3D <&vdd_1v2_rgb>; + vddio-supply =3D <&vdd_1v8_vio>; + + solomon,hs-zero-delay-ns =3D <300>; + solomon,hs-prep-delay-ns =3D <65>; + + clocks =3D <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_EXTERN3>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + assigned-clock-rates =3D <24000000>; + + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_EXTERN3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + bridge_input: endpoint { + remote-endpoint =3D <&dpi_output>; + bus-width =3D <24>; + }; + }; + + port@1 { + reg =3D <1>; + + bridge_output: endpoint { + remote-endpoint =3D <&panel_input>; + }; + }; + }; + }; }; =20 pmc@7000e400 { @@ -1617,6 +1685,17 @@ vdd_1v8_sen: regulator-sen1v8 { vin-supply =3D <&vdd_3v3_vbat>; }; =20 + vdd_1v2_rgb: regulator-rgb1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_1v2_rgb"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + gpio =3D <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_3v3_vbat>; + }; + vcc_3v0_lcd: regulator-lcd3v { compatible =3D "regulator-fixed"; regulator-name =3D "vcc_3v0_lcd"; --=20 2.51.0 From nobody Sun Feb 8 09:37:26 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7929732D451 for ; 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Mon, 26 Jan 2026 02:15:10 -0800 (PST) Received: from xeon ([188.163.112.49]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4804d8a5c32sm319771795e9.11.2026.01.26.02.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 02:15:10 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] ARM: tegra: lg-x3: add USB and power related nodes Date: Mon, 26 Jan 2026 12:10:16 +0200 Message-ID: <20260126101018.24450-3-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126101018.24450-1-clamor95@gmail.com> References: <20260126101018.24450-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add missing charger, MUIC and ADC sensor nodes. Reconfigure USB, set one of the ADC channels as the fuel gauge temperature sensor and add a battery thermal zone. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 93 ++++++++++++++++++++- 1 file changed, 91 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dt= s/nvidia/tegra30-lg-x3.dtsi index 6eea8eacd7d5..768e201456d8 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -1070,6 +1070,38 @@ rmi4-f11@11 { syna,clip-y-low =3D <0>; }; }; + + max14526: muic@44 { + compatible =3D "maxim,max14526"; + reg =3D <0x44>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + muic_con: connector { + compatible =3D "usb-b-connector"; + label =3D "micro-USB"; + type =3D "micro"; + }; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + muic_to_charger: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&charger_input>; + }; + }; + }; + + tsc2007: adc@48 { + compatible =3D "ti,tsc2007"; + reg =3D <0x48>; + + ti,x-plate-ohms =3D <1>; + #io-channel-cells =3D <1>; + }; }; =20 cam_i2c: i2c@7000c500 { @@ -1326,6 +1358,22 @@ ldo8 { }; }; =20 + max8971: charger@35 { + compatible =3D "maxim,max8971"; + reg =3D <0x35>; + + interrupt-parent =3D <&gpio>; + interrupts =3D ; + + monitored-battery =3D <&battery>; + + port { + charger_input: endpoint { + remote-endpoint =3D <&muic_to_charger>; + }; + }; + }; + fuel-gauge@36 { compatible =3D "maxim,max17043"; reg =3D <0x36>; @@ -1334,6 +1382,10 @@ fuel-gauge@36 { interrupts =3D ; =20 monitored-battery =3D <&battery>; + power-supplies =3D <&max8971>; + + io-channels =3D <&tbattery 0>; + io-channel-names =3D "temp"; =20 maxim,alert-low-soc-level =3D <10>; wakeup-source; @@ -1514,12 +1566,13 @@ sdmmc4: mmc@78000600 { usb@7d000000 { compatible =3D "nvidia,tegra30-udc"; status =3D "okay"; - dr_mode =3D "peripheral"; + dr_mode =3D "otg"; + extcon =3D <&max14526>, <&max14526>; }; =20 usb-phy@7d000000 { status =3D "okay"; - dr_mode =3D "peripheral"; + dr_mode =3D "otg"; nvidia,hssync-start-delay =3D <0>; nvidia,xcvr-lsfslew =3D <2>; nvidia,xcvr-lsrslew =3D <2>; @@ -1803,7 +1856,43 @@ sound { <&tegra_car TEGRA30_CLK_EXTERN1>; }; =20 + tbattery: thermal-sensor-battery { + compatible =3D "generic-adc-thermal"; + #thermal-sensor-cells =3D <0>; + + io-channels =3D <&tsc2007 4>; + io-channel-names =3D "sensor-channel"; + #io-channel-cells =3D <1>; + + temperature-lookup-table =3D < + (-50000) 4100 (-40000) 3980 (-30000) 3815 (-20000) 3610 + (-10000) 3285 0 2880 10000 2445 20000 1955 + 30000 1440 40000 1125 50000 840 60000 665 + 70000 465 80000 350 90000 230 100000 185 >; + }; + thermal-zones { + battery-thermal { + polling-delay-passive =3D <0>; /* milliseconds */ + polling-delay =3D <20000>; /* milliseconds */ + + thermal-sensors =3D <&tbattery>; + + trips { + battery-alert { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + battery-crit { + temperature =3D <60000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + /* * NCT72 has two sensors: * --=20 2.51.0 From nobody Sun Feb 8 09:37:26 2026 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B38BD30DECC for ; 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charset="utf-8" Both smartphones have capacitive buttons but only P895 supports RMI4 function 1A (0D touch), while P880 exposes buttons area as a region of the touchscreen. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p895.dts index ab8f5cf317bf..414117fd4382 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -109,6 +109,12 @@ rmi4-f11@11 { syna,clip-x-high =3D <1535>; syna,clip-y-high =3D <2047>; }; + + rmi4-f1a@1a { + reg =3D <0x1a>; + + linux,keycodes =3D ; + }; }; }; =20 --=20 2.51.0 From nobody Sun Feb 8 09:37:26 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D15B330E0C8 for ; Mon, 26 Jan 2026 10:15:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Add front and rear camera nodes and interlink them with Tegra CSI and VI. Adjust camera PMIC voltages to better fit requirements and fix the focuser node. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 28 ++++ arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 46 ++++++ arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 154 +++++++++++++++++-- 3 files changed, 214 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p880.dts index cc14e6dca770..1b21d7628c8c 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -12,6 +12,18 @@ aliases { mmc2 =3D &sdmmc1; /* WiFi */ }; =20 + host1x@50000000 { + vi@54080000 { + csi@800 { + /delete-node/ channel@1; + }; + + ports { + /delete-node/ port@1; + }; + }; + }; + pinmux@70000868 { pinctrl-names =3D "default"; pinctrl-0 =3D <&state_default>; @@ -116,6 +128,22 @@ rmi4-f11@11 { }; }; =20 + i2c@7000c500 { + camera-pmic@7d { + vt_1v2_front: ldo1 { + regulator-name =3D "vt_1v2_dig"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + vt_2v7_front: ldo2 { + regulator-name =3D "vt_2v7_vana"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2700000>; + }; + }; + }; + spi@7000dc00 { dsi@2 { /* diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p895.dts index 414117fd4382..896639599c12 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -118,6 +118,52 @@ rmi4-f1a@1a { }; }; =20 + i2c@7000c500 { + /* Aptina 1/6" HD SOC (MT9M114) */ + front-camera@48 { + compatible =3D "onnn,mt9m114"; + reg =3D <0x48>; + + clocks =3D <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios =3D <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>; + + vddio-supply =3D <&vio_1v8_front>; + vdd-supply =3D <&vt_1v8_front>; + vaa-supply =3D <&vt_2v8_front>; + + orientation =3D <0>; /* Front camera */ + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates =3D <24000000>; + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + front_camera_output: endpoint { + bus-type =3D ; + link-frequencies =3D /bits/ 64 <384000000>; + remote-endpoint =3D <&csib_input>; + }; + }; + }; + + camera-pmic@7d { + vt_1v8_front: ldo1 { + regulator-name =3D "vt_1v8_dig"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + vt_2v8_front: ldo2 { + regulator-name =3D "vt_2v8_vana"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + }; + }; + spi@7000dc00 { dsi@2 { /* diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dt= s/nvidia/tegra30-lg-x3.dtsi index 768e201456d8..178e4bb153d3 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include =20 @@ -74,6 +75,91 @@ trustzone@bfe00000 { }; =20 host1x@50000000 { + vi@54080000 { + status =3D "okay"; + + csi@800 { + status =3D "okay"; + + avdd-dsi-csi-supply =3D <&avdd_dsi_csi>; + + /* CSI-A */ + channel@0 { + reg =3D <0>; + + nvidia,mipi-calibrate =3D <&csi 0>; /* CSIA pad */ + + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + csia_input: endpoint { + data-lanes =3D <1 2>; + remote-endpoint =3D <&rear_camera_output>; + }; + }; + + port@1 { + reg =3D <1>; + + csia_output: endpoint { + remote-endpoint =3D <&vi_ppa_input>; + }; + }; + }; + + /* CSI-B */ + channel@1 { + reg =3D <1>; + + nvidia,mipi-calibrate =3D <&csi 1>; /* CSIB pad */ + + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + csib_input: endpoint { + data-lanes =3D <3>; + remote-endpoint =3D <&front_camera_output>; + }; + }; + + port@1 { + reg =3D <1>; + + csib_output: endpoint { + remote-endpoint =3D <&vi_ppb_input>; + }; + }; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + vi_ppa_input: endpoint { + remote-endpoint =3D <&csia_output>; + }; + }; + + port@1 { + reg =3D <1>; + + vi_ppb_input: endpoint { + remote-endpoint =3D <&csib_output>; + }; + }; + }; + }; + lcd: dc@54200000 { rgb { status =3D "okay"; @@ -1112,29 +1198,68 @@ dw9714: coil@c { compatible =3D "dongwoon,dw9714"; reg =3D <0x0c>; =20 - enable-gpios =3D <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + powerdown-gpios =3D <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; =20 vcc-supply =3D <&vcc_focuser>; }; =20 + /* SONY IMX111 1/4" BSI */ + rear-camera@10 { + compatible =3D "sony,imx111"; + reg =3D <0x10>; + + clocks =3D <&tegra_car TEGRA30_CLK_CSUS>; + + reset-gpios =3D <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>; + + iovdd-supply =3D <&vio_1v8_rear>; + dvdd-supply =3D <&vdd_1v2_rear>; + avdd-supply =3D <&vdd_2v7_rear>; + + orientation =3D <1>; /* Rear camera */ + rotation =3D <90>; + + nvmem =3D <&m24c08>; + lens-focus =3D <&dw9714>; + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_VI_SENSOR>, + <&tegra_car TEGRA30_CLK_CSUS>; + assigned-clock-rates =3D <24000000>; + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_VI_SENSOR>; + + port { + rear_camera_output: endpoint { + data-lanes =3D <1 2>; + bus-type =3D ; + link-frequencies =3D /bits/ 64 <542400000>; + remote-endpoint =3D <&csia_input>; + }; + }; + }; + + /* rear camera sensor eeprom */ + m24c08: eeprom@50 { + compatible =3D "st,m24c08", "atmel,24c08"; + reg =3D <0x50>; + + /* if high then WP is on, if low then off */ + wp-gpios =3D <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; + + /* it is not OTP but writing is unwanted */ + read-only; + pagesize =3D <16>; + num-addresses =3D <1>; + + vcc-supply =3D <&vio_1v8_rear>; + }; + camera-pmic@7d { compatible =3D "ti,lp8720"; reg =3D <0x7d>; =20 enable-gpios =3D <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; =20 - vt_1v2_front: ldo1 { - regulator-name =3D "vt_1v2_dig"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - }; - - vt_2v7_front: ldo2 { - regulator-name =3D "vt_2v7_vana"; - regulator-min-microvolt =3D <2700000>; - regulator-max-microvolt =3D <2700000>; - }; - vdd_2v7_rear: ldo3 { regulator-name =3D "8m_2v7_vana"; regulator-min-microvolt =3D <2700000>; @@ -1348,10 +1473,11 @@ vdd_1v2_mhl: ldo7 { maxim,active-fps-source =3D ; }; =20 - ldo8 { + avdd_dsi_csi: ldo8 { regulator-name =3D "avdd_dsi_csi"; regulator-min-microvolt =3D <1200000>; regulator-max-microvolt =3D <1200000>; + regulator-boot-on; =20 maxim,active-fps-source =3D ; }; --=20 2.51.0