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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF000023D2.mail.protection.outlook.com (10.167.244.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Mon, 26 Jan 2026 07:46:32 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 25 Jan 2026 23:46:19 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 25 Jan 2026 23:46:14 -0800 From: Manikanta Maddireddy To: , , , , , , , , , , , , <18255117159@163.com> CC: , , , , "Manikanta Maddireddy" Subject: [PATCH V4 05/22] PCI: tegra194: Refactor LTSSM state polling on surprise down Date: Mon, 26 Jan 2026 13:15:02 +0530 Message-ID: <20260126074519.3426742-6-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260126074519.3426742-1-mmaddireddy@nvidia.com> References: <20260126074519.3426742-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|MW4PR12MB7214:EE_ X-MS-Office365-Filtering-Correlation-Id: 93965e54-fb7d-4113-9808-08de5caf05e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 07:46:32.0486 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93965e54-fb7d-4113-9808-08de5caf05e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7214 Content-Type: text/plain; charset="utf-8" From: Vidya Sagar On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock -> Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock and Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively. So, the total time taken to transit from L0 to detect state is ~96 msec. Hence, increase the poll time to 120 msec. Disable the LTSSM state after it transits to detect to avoid LTSSM toggling between polling and detect states. tegra_pcie_dw_pme_turnoff() function is called in non-atomic context only, so use the non-atomic poll function. Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- V4: * None V3: * Addressed review comments from Bjorn * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 55 +++++++++++++--------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 04ff211deaea..d3d577d5f67b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -138,7 +138,11 @@ #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 -#define LTSSM_STATE_PRE_DETECT 5 +#define LTSSM_STATE_DETECT_QUIET 0x00 +#define LTSSM_STATE_DETECT_ACT 0x08 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x28 +#define LTSSM_STATE_DETECT_WAIT 0x30 +#define LTSSM_STATE_L2_IDLE 0xa8 =20 #define APPL_RADM_STATUS 0xE4 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) @@ -202,7 +206,8 @@ #define PME_ACK_DELAY 100 /* 100 us */ #define PME_ACK_TIMEOUT 10000 /* 10 ms */ =20 -#define LTSSM_TIMEOUT 50000 /* 50ms */ +#define LTSSM_DELAY 10000 /* 10 ms */ +#define LTSSM_TIMEOUT 120000 /* 120 ms */ =20 #define GEN3_GEN4_EQ_PRESET_INIT 5 =20 @@ -1593,23 +1598,22 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_= pcie_dw *pcie) data &=3D ~APPL_PINMUX_PEX_RST; appl_writel(pcie, data, APPL_PINMUX); =20 + err =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data, + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_QUIET) = || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_ACT) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_PRE_DETECT_QUI= ET) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_WAIT), + LTSSM_DELAY, LTSSM_TIMEOUT); + if (err) + dev_info(pcie->dev, "Link didn't go to detect state\n"); + /* - * Some cards do not go to detect state even after de-asserting - * PERST#. So, de-assert LTSSM to bring link to detect state. + * Deassert LTSSM state to stop the state toggling between + * polling and detect. */ data =3D readl(pcie->appl_base + APPL_CTRL); data &=3D ~APPL_CTRL_LTSSM_EN; writel(data, pcie->appl_base + APPL_CTRL); - - err =3D readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, - data, - ((data & - APPL_DEBUG_LTSSM_STATE_MASK) >> - APPL_DEBUG_LTSSM_STATE_SHIFT) =3D=3D - LTSSM_STATE_PRE_DETECT, - 1, LTSSM_TIMEOUT); - if (err) - dev_info(pcie->dev, "Link didn't go to detect state\n"); } /* * DBI registers may not be accessible after this as PLL-E would be @@ -1677,19 +1681,24 @@ static void pex_ep_event_pex_rst_assert(struct tegr= a_pcie_dw *pcie) if (pcie->ep_state =3D=3D EP_STATE_DISABLED) return; =20 - /* Disable LTSSM */ + ret =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, + ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_QUIET) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_ACT) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_PRE_DETECT_QUIET= ) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_WAIT) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_L2_IDLE), + LTSSM_DELAY, LTSSM_TIMEOUT); + if (ret) + dev_err(pcie->dev, "LTSSM state: 0x%x timeout: %d\n", val, ret); + + /* + * Deassert LTSSM state to stop the state toggling between + * polling and detect. + */ val =3D appl_readl(pcie, APPL_CTRL); val &=3D ~APPL_CTRL_LTSSM_EN; appl_writel(pcie, val, APPL_CTRL); =20 - ret =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, - ((val & APPL_DEBUG_LTSSM_STATE_MASK) >> - APPL_DEBUG_LTSSM_STATE_SHIFT) =3D=3D - LTSSM_STATE_PRE_DETECT, - 1, LTSSM_TIMEOUT); - if (ret) - dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); - reset_control_assert(pcie->core_rst); =20 tegra_pcie_disable_phy(pcie); --=20 2.34.1