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Sun, 25 Jan 2026 23:47:12 -0800 From: Manikanta Maddireddy To: , , , , , , , , , , , , <18255117159@163.com> CC: , , , , "Manikanta Maddireddy" Subject: [PATCH V4 15/22] PCI: tegra194: Don't force the device into the D0 state before L2 Date: Mon, 26 Jan 2026 13:15:12 +0530 Message-ID: <20260126074519.3426742-16-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260126074519.3426742-1-mmaddireddy@nvidia.com> References: <20260126074519.3426742-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000208:EE_|MN6PR12MB8542:EE_ X-MS-Office365-Filtering-Correlation-Id: 4cb66671-f266-446a-1b9e-08de5caf2b1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 07:47:34.4703 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cb66671-f266-446a-1b9e-08de5caf2b1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000208.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8542 Content-Type: text/plain; charset="utf-8" From: Vidya Sagar As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe endpoint device should be in D3 state to assert wake# pin. This takes precedence over PCI Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management which states that the device can be put into D0 state before taking the link to L2 state. So, to enable the wake functionality for endpoints, do not force the devices to D0 state before taking the link to L2 state. There is no functional issue with the endpoints where the link doesn't go into L2 state (the reason why the earlier change was made in the first place) as the root port proceeds with the usual flow post PME timeout. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- V4: * None V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 41 ---------------------- 1 file changed, 41 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 6fcfff93d4bc..1a269397150a 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1283,44 +1283,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegr= a_pcie_dw *pcie, return 0; } =20 -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) -{ - struct dw_pcie_rp *pp =3D &pcie->pci.pp; - struct pci_bus *child, *root_port_bus =3D NULL; - struct pci_dev *pdev; - - /* - * link doesn't go into L2 state with some of the endpoints with Tegra - * if they are not in D0 state. So, need to make sure that immediate - * downstream devices are in D0 state before sending PME_TurnOff to put - * link into L2 state. - * This is as per PCI Express Base r4.0 v1.0 September 27-2017, - * 5.2 Link State Power Management (Page #428). - */ - - list_for_each_entry(child, &pp->bridge->bus->children, node) { - if (child->parent =3D=3D pp->bridge->bus) { - root_port_bus =3D child; - break; - } - } - - if (!root_port_bus) { - dev_err(pcie->dev, "Failed to find downstream bus of Root Port\n"); - return; - } - - /* Bring downstream devices to D0 if they are not already in */ - list_for_each_entry(pdev, &root_port_bus->devices, bus_list) { - if (PCI_SLOT(pdev->devfn) =3D=3D 0) { - if (pci_set_power_state(pdev, PCI_D0)) - dev_err(pcie->dev, - "Failed to transition %s to D0 state\n", - dev_name(&pdev->dev)); - } - } -} - static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) { pcie->slot_ctl_3v3 =3D devm_regulator_get_optional(pcie->dev, "vpcie3v3"); @@ -1650,7 +1612,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pc= ie_dw *pcie) =20 static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { - tegra_pcie_downstream_dev_to_D0(pcie); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2402,7 +2363,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device = *dev) if (!pcie->link_state) return 0; =20 - tegra_pcie_downstream_dev_to_D0(pcie); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); =20 @@ -2479,7 +2439,6 @@ static void tegra_pcie_dw_shutdown(struct platform_de= vice *pdev) return; =20 debugfs_remove_recursive(pcie->debugfs); - tegra_pcie_downstream_dev_to_D0(pcie); =20 disable_irq(pcie->pci.pp.irq); if (IS_ENABLED(CONFIG_PCI_MSI)) --=20 2.34.1