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charset="utf-8" Some DesignWare PCIe endpoint controllers integrate a DesignWare eDMA instance. Remote-eDMA providers (e.g. vNTB) need to expose the eDMA register block to the host through a memory window so the host can ioremap it and run dw_edma_probe() against the remote view. Record the physical base and size of the eDMA register aperture and export dwc_pcie_edma_get_reg_window() so higher-level code can query the register window associated with a given PCI EPC device. Keep the controller-side helper declarations in a dedicated header to avoid pulling eDMA/dmaengine-specific interfaces into the generic DesignWare PCIe header (include/linux/pcie-dwc.h). Signed-off-by: Koichiro Den --- MAINTAINERS | 2 +- drivers/pci/controller/dwc/pcie-designware.c | 29 +++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 2 + include/linux/pcie-dwc-edma.h | 39 ++++++++++++++++++++ 4 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 include/linux/pcie-dwc-edma.h diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..fa0cb454744c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20066,7 +20066,7 @@ S: Maintained F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml F: drivers/pci/controller/dwc/*designware* -F: include/linux/pcie-dwc.h +F: include/linux/pcie-dwc*.h =20 PCI DRIVER FOR TI DRA7XX/J721E M: Vignesh Raghavendra diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 18331d9e85be..bbaeecce199a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -162,8 +163,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci) pci->edma.reg_base =3D devm_ioremap_resource(pci->dev, res); if (IS_ERR(pci->edma.reg_base)) return PTR_ERR(pci->edma.reg_base); + pci->edma_reg_phys =3D res->start; + pci->edma_reg_size =3D resource_size(res); } else if (pci->atu_size >=3D 2 * DEFAULT_DBI_DMA_OFFSET) { pci->edma.reg_base =3D pci->atu_base + DEFAULT_DBI_DMA_OFFSET; + pci->edma_reg_phys =3D pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET; + pci->edma_reg_size =3D pci->atu_size - DEFAULT_DBI_DMA_OFFSET; } } =20 @@ -1340,3 +1345,27 @@ resource_size_t dw_pcie_parent_bus_offset(struct dw_= pcie *pci, =20 return cpu_phys_addr - reg_addr; } + +int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, + resource_size_t *sz) +{ + struct dw_pcie_ep *ep; + struct dw_pcie *pci; + + if (!epc || !phys || !sz) + return -EINVAL; + + ep =3D epc_get_drvdata(epc); + if (!ep) + return -ENODEV; + + pci =3D to_dw_pcie_from_ep(ep); + if (!pci->edma_reg_size) + return -ENODEV; + + *phys =3D pci->edma_reg_phys; + *sz =3D pci->edma_reg_size; + + return 0; +} +EXPORT_SYMBOL_GPL(dwc_pcie_edma_get_reg_window); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index c3301b3aedb7..cd38147443bf 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -534,6 +534,8 @@ struct dw_pcie { int max_link_speed; u8 n_fts[2]; struct dw_edma_chip edma; + phys_addr_t edma_reg_phys; + resource_size_t edma_reg_size; bool l1ss_support; /* L1 PM Substates support */ struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS]; struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS]; diff --git a/include/linux/pcie-dwc-edma.h b/include/linux/pcie-dwc-edma.h new file mode 100644 index 000000000000..a5b0595603f4 --- /dev/null +++ b/include/linux/pcie-dwc-edma.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * DesignWare PCIe controller helpers for integrated DesignWare eDMA. + */ + +#ifndef LINUX_PCIE_DWC_EDMA_H +#define LINUX_PCIE_DWC_EDMA_H + +#include +#include +#include +#include + +#ifdef CONFIG_PCIE_DW +/** + * dwc_pcie_edma_get_reg_window() - get integrated DW eDMA register window + * @epc: EPC device associated with the integrated eDMA instance + * @phys: pointer to receive the CPU-physical base address + * @sz: pointer to receive the size in bytes + * + * Some DesignWare PCIe endpoint controllers integrate a DesignWare eDMA + * instance. Higher-level code (e.g. BAR/window setup for remote use) may + * need the CPU-physical base and size of the eDMA register aperture. + * + * Return: 0 on success, -ENODEV if the EPC has no integrated eDMA register + * window, or -EINVAL if @epc is %NULL. + */ +int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, + resource_size_t *sz); +#else +static inline int +dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, + resource_size_t *sz) +{ + return -ENODEV; +} +#endif /* CONFIG_PCIE_DW */ + +#endif /* LINUX_PCIE_DWC_EDMA_H */ --=20 2.51.0