From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CE3C270552; Sun, 25 Jan 2026 19:07:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368070; cv=none; b=AbDoBOqVK6tnFTWJafxXEYpg7OE78y9hRGkXBweF5oj7cfCC8/xEn9v1Rf9ypGQAGG/F0AeDqZzlpykHifZZLC5zxFsHaMPxtOwWRMLypIsXAf9SGoh/8cjVqoo8Iqp3nNirYKPxj7Bm/kzWfyZOlkBpg7vrA1gtKB7QSfOIpdc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368070; c=relaxed/simple; bh=UGom5F2XoRj2ePCeHluZNCyK/VNDR585euzHO1No7lQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fha1Dfja02odOwHNiBekpfDXuapXZ23+LjsZueCZeUDAbnQvqmpa/tOCQULcjftI09I1jBFLWzyeb54MZiwpAfJp0lC7gfRpLxTxKoB02uThvQMYtu0vfa2OkBv2gD3JA7RGQKISo8FY2BK9RIVrXHypgnJ4gMfUNb686rpiy40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=QjdFFQiA; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="QjdFFQiA" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id DA27427DEF; Sun, 25 Jan 2026 20:07:46 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 4m-0iEfYHiDC; Sun, 25 Jan 2026 20:07:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368066; bh=UGom5F2XoRj2ePCeHluZNCyK/VNDR585euzHO1No7lQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=QjdFFQiArJWA688VUBOFLqpAAEmB1ZW1lbmNv+tHBD+EDceMI6SmoMF1S/xnR4pJH UG6heUnIxrH2+ylOEobor/Dw5FQQFwRBg7zYREIc7SPW61j6TJgZxqfap+qvESDaGY wDpjGV8iomBbkf64LHHTIdjIyJsuDidJG182N14qmmI9ry401WqYPHSOtsoeZj8iqj 2Cq1/ZC/xWhkhOCqQN7kOcQpOv0eJDCwf6SXLKT1ND24V6aDxIwm5hzwk7cKFbYxXN 4OzYG5GdWYEzdlp5CYmU4fIKcGZ9i+eIF86vcNOSHh3Jg1+swNQhIBF/GTheQgnue1 G5HfULHOMu8fQ== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:08 +0530 Subject: [PATCH v2 01/12] dt-bindings: leds: document Samsung S2M series PMIC flash LED device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-1-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty , Conor Dooley Certain Samsung S2M series PMICs have a flash LED controller with two LED channels, and with torch and flash control modes. Document the devicetree schema for the device. Acked-by: Conor Dooley Signed-off-by: Kaustabh Chakraborty --- .../bindings/leds/samsung,s2mu005-flash.yaml | 52 ++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.y= aml b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml new file mode 100644 index 0000000000000..36051ab20509f --- /dev/null +++ b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/samsung,s2mu005-flash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Flash and Torch LED Controller for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC flash LED has two led channels (typically + as back and front camera flashes), with support for both torch and + flash modes. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-flash + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-1]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1] + + required: + - reg + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49FA5223323; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="EQAJtKM3" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id ECA5C2808A; Sun, 25 Jan 2026 20:07:53 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id SBhTL00I8zoi; Sun, 25 Jan 2026 20:07:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368073; bh=txqTjzdPHgzCrlnKm2VnJpot2FYiSJwnJw5EbQDWV2k=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=EQAJtKM3tCW8BLP/4eIkkIjp3mVy8izAwxIQlsl+w84beGoJRPPcKWNeO+6lgqcQN d3d8Yb6ZIoIOzeAL1tXbIBXgPSs/bGLX+mSiFbMuCYi7K/WxOe92xF6blm3HXyanK/ /rzvbSW2TDVKYsBMy0IW2b9iO6Uh8IIlNzuPCU9MuxUK0fsSA/0csEmDuaa+iLt14h xJJx/NmLdaWG3LuQlg7CPq5cAR8W4BlX4gKm7chjxm2vQRrA7bP5RXBrwg7ZCbrX2u C0YAfGE5X6vb4YEyTJP73cBneHK05DiPrV2gjBG+0G017k0v6lXmTQbvF9H7TmMQip anItPTFT5DhfQ== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:09 +0530 Subject: [PATCH v2 02/12] dt-bindings: leds: document Samsung S2M series PMIC RGB LED device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-2-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Certain Samsung S2M series PMICs have a three-channel LED device with independent brightness control for each channel, typically used as status indicators in mobile phones. Document the devicetree schema from this device. Signed-off-by: Kaustabh Chakraborty --- .../bindings/leds/samsung,s2mu005-rgb.yaml | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/leds/samsung,s2mu005-rgb.yam= l b/Documentation/devicetree/bindings/leds/samsung,s2mu005-rgb.yaml new file mode 100644 index 0000000000000..6806b6d869ff7 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/samsung,s2mu005-rgb.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/samsung,s2mu005-rgb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RGB LED Controller for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC RGB LED is a three-channel LED device with + 8-bit brightness control for each channel, typically used as status + indicators in mobile phones. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +allOf: + - $ref: common.yaml# + +properties: + compatible: + enum: + - samsung,s2mu005-rgb + +required: + - compatible + +unevaluatedProperties: false --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C60F32EE5FD; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-3-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Certain Samsung S2M series PMICs have a MUIC device which reports various cable states by measuring the ID-GND resistance with an internal ADC. Document the devicetree schema for this device. Signed-off-by: Kaustabh Chakraborty --- .../bindings/extcon/samsung,s2mu005-muic.yaml | 35 ++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.= yaml b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml new file mode 100644 index 0000000000000..05828b7b5be13 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/samsung,s2mu005-muic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Extcon Device for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC extcon device is a USB port accessory + detector. It reports multiple states depending on the ID-GND + resistance measured by an internal ADC. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-muic + + port: + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - port + +additionalProperties: false --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 758722BF006; Sun, 25 Jan 2026 19:08:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368090; cv=none; b=iwJpfGRmHT1jWMWHRNKIt4QncdEYyGqwBFtF4yyaXtnB4BVoz4jgVHf7aJ8setGNKat3DXDrucvJ2tI3KhInONiRna3nyEzQ5UK0bD+oxedHphvFBxvdOvuVDpgC/DFqM0e8753L4zepTM5FEPShb4yFYgOil+Qp2ETU+lCQDAY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368090; c=relaxed/simple; bh=v18ecyJjpRt8OYAuP8S1Zuke3HLjhsE22p1SX0Vty34=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CIYzvVEIg8uizo883LoHywAvWVy0xy4FtGAZ66GW87kHYdYoZzuoXF6h36sK3CEQI8/MNJ6znNSXKeuwvpWBu+W2aLIZMh+sEgGRNIww1IjOZkstyHuUjni0fLnzK+YRNokx6nUVJSnu9FXTIzYIsLgLpIueRBJ6BwvDtA3SCsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ezCqyN9o; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ezCqyN9o" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id BA42928091; Sun, 25 Jan 2026 20:08:07 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id IRqWjFqTHowk; Sun, 25 Jan 2026 20:08:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368086; bh=v18ecyJjpRt8OYAuP8S1Zuke3HLjhsE22p1SX0Vty34=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ezCqyN9oq1zLOId9gV+uNJ2YCfSC+38qpsNWLOp+XrWS7MBMRmkdHmpjRI5/q8mJ9 1TD73w2cdFXWQTvz/iywrn/xcPh84YUbcHnzGT2MT3JKLxba9qeLd6In/vSWZEmAw1 YA6r3u+jDJ4VQmIfB3SX/f0uF7N6wT2BNqDf4Di4meh1ZLqF48Qv1nIGu5lAFGpRna BT35j+6g9vKGhftv5juaqRWwdhfu9RROC1B0MORbMGecLILpctD8k6KN1R7QzxLTt2 W2uB+5nm/ZA2zsWBQz+RUHXM1TJ2bHDRKVfw1kLuBUUrlHUEjFx7Ct7m5iQTHxWy1N ycvPrU1s6K+9Q== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:11 +0530 Subject: [PATCH v2 04/12] dt-bindings: power: supply: document Samsung S2M series PMIC charger device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-4-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Certain Samsung S2M series PMICs have a battery charger device which, among other things, manages power interfacing of the USB port. It may supply power, as done in USB OTG operation mode, or it may accept power and redirect it to the battery fuelgauge for charging. Document this device. Signed-off-by: Kaustabh Chakraborty --- .../power/supply/samsung,s2mu005-charger.yaml | 35 ++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/power/supply/samsung,s2mu005= -charger.yaml b/Documentation/devicetree/bindings/power/supply/samsung,s2mu= 005-charger.yaml new file mode 100644 index 0000000000000..9159a15e77c61 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/samsung,s2mu005-charge= r.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/samsung,s2mu005-charger.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Battery Charger for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC battery charger manages power interfacing + of the USB port. It may supply power, as done in USB OTG operation + mode, or it may accept power and redirect it to the battery fuelgauge + for charging. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + enum: + - samsung,s2mu005-charger + +required: + - compatible + +unevaluatedProperties: false --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4E102F1FC2; Sun, 25 Jan 2026 19:08:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368098; cv=none; b=X2bPBtRzS4MzKPfxNJ6de0zfvpAKuPXQ5y3+Qh9EKeWZ9+i1+FWcmOl2sITJwAzaqysePaEi+tG/XqjvLzMxch012/rWzamz4J0dNYaXK3EXwPUyCCwdnC+IGu2Neo99FQkSQ91n8j5OLIMqN0kIIhfxRP291x5XR2uF8zVRFcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368098; c=relaxed/simple; bh=Zy+SVUpiJPjBHTmVZxRaYPNFRrYrsIXJ4T0wcFAGRGQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mLaR60DougF6ySA4tHY4cqIQpqKPaybYFdPubOXv2Vl5fhehCplTOD7FVxw9tWITY4gplaLCv5+ASzvFsQ4jb0l+NCt3vhv25Avt1m07RlAOu7arkBZTa7TiyKJVWTffl56F8TAk5wERwpGdW/kf10663t1qTQY8WfVox2SWfS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=I30CBUZa; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="I30CBUZa" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 2DBA728088; Sun, 25 Jan 2026 20:08:15 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id WICNRE4q0Jxc; Sun, 25 Jan 2026 20:08:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368094; bh=Zy+SVUpiJPjBHTmVZxRaYPNFRrYrsIXJ4T0wcFAGRGQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=I30CBUZaEeGWXCJW1mJeeIE91qdxqZIlaPjvFXLMN2WNmADQpmeJXXJcR62NWW5UY LOYNtqNaBJvDG78vLlMdim0K2soILbfv99oC+4QylGkJ/sbCip3ElYPskzy5cbEfTV i1ghRC42jFx5blFwb7noNQmH4BGbLKrjyh6jHZW1XW6Dct7MXmLBVosvembDUN5l1D Rj7/kZ45LG1NQ0gbTBj1TrvrmsEee1SMfUC621F+Df0kgJWjTZg+dl6d34hhzNnc+e IBXJ73MfdD1F+ffZ/J5fhgIdCkmp7tH8hVRvf20Me8YrUr/AkDoXI+zrly01rKVfCz YwMgRqK5Ns7aQ== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:12 +0530 Subject: [PATCH v2 05/12] dt-bindings: mfd: s2mps11: add documentation for S2MU005 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-5-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. Since regulators are not supported by this device, unmark this property as required and instead set this in a per-device basis for ones which need it. Add the compatible and documentation for the S2MU005 PMIC. Also, add an example for nodes for supported sub-devices, i.e. charger, extcon, flash, and rgb. Signed-off-by: Kaustabh Chakraborty --- .../devicetree/bindings/mfd/samsung,s2mps11.yaml | 103 +++++++++++++++++= +++- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml b/D= ocumentation/devicetree/bindings/mfd/samsung,s2mps11.yaml index 31d544a9c05ca..aef634ca2e36f 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml @@ -27,12 +27,28 @@ properties: - samsung,s2mps15-pmic - samsung,s2mpu02-pmic - samsung,s2mpu05-pmic + - samsung,s2mu005-pmic =20 clocks: $ref: /schemas/clock/samsung,s2mps11.yaml description: Child node describing clock provider. =20 + charger: + $ref: /schemas/power/supply/samsung,s2m-charger.yaml + description: + Child node describing battery charger device. + + extcon: + $ref: /schemas/extcon/samsung,s2m-muic.yaml + description: + Child node describing extcon device. + + flash: + $ref: /schemas/leds/samsung,s2m-flash.yaml + description: + Child node describing flash LEDs. + interrupts: maxItems: 1 =20 @@ -44,6 +60,11 @@ properties: description: List of child nodes that specify the regulators. =20 + rgb: + $ref: /schemas/leds/samsung,s2m-rgb.yaml + description: + Child node describing RGB LEDs. + samsung,s2mps11-acokb-ground: description: | Indicates that ACOKB pin of S2MPS11 PMIC is connected to the ground = so @@ -65,7 +86,6 @@ properties: =20 required: - compatible - - regulators =20 additionalProperties: false =20 @@ -105,6 +125,8 @@ allOf: regulators: $ref: /schemas/regulator/samsung,s2mps11.yaml samsung,s2mps11-wrstbi-ground: false + required: + - regulators =20 - if: properties: @@ -116,6 +138,8 @@ allOf: regulators: $ref: /schemas/regulator/samsung,s2mps13.yaml samsung,s2mps11-acokb-ground: false + required: + - regulators =20 - if: properties: @@ -128,6 +152,8 @@ allOf: $ref: /schemas/regulator/samsung,s2mps14.yaml samsung,s2mps11-acokb-ground: false samsung,s2mps11-wrstbi-ground: false + required: + - regulators =20 - if: properties: @@ -140,6 +166,8 @@ allOf: $ref: /schemas/regulator/samsung,s2mps15.yaml samsung,s2mps11-acokb-ground: false samsung,s2mps11-wrstbi-ground: false + required: + - regulators =20 - if: properties: @@ -152,6 +180,8 @@ allOf: $ref: /schemas/regulator/samsung,s2mpu02.yaml samsung,s2mps11-acokb-ground: false samsung,s2mps11-wrstbi-ground: false + required: + - regulators =20 - if: properties: @@ -164,6 +194,18 @@ allOf: $ref: /schemas/regulator/samsung,s2mpu05.yaml samsung,s2mps11-acokb-ground: false samsung,s2mps11-wrstbi-ground: false + required: + - regulators + + - if: + properties: + compatible: + contains: + const: samsung,s2mu005-pmic + then: + properties: + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false =20 examples: - | @@ -305,3 +347,62 @@ examples: }; }; }; + + - | + #include + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmic@3d { + compatible =3D "samsung,s2mu005-pmic"; + reg =3D <0x3d>; + interrupt-parent =3D <&gpa2>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + + charger { + compatible =3D "samsung,s2mu005-charger"; + monitored-battery =3D <&battery>; + }; + + extcon { + compatible =3D "samsung,s2mu005-muic"; + + port { + muic_to_usb: endpoint { + remote-endpoint =3D <&usb_to_muic>; + }; + }; + }; + + flash { + compatible =3D "samsung,s2mu005-flash"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + label =3D "back-cam:white:flash"; + color =3D ; + function =3D LED_FUNCTION_FLASH; + }; + + led@1 { + reg =3D <1>; + label =3D "front-cam:white:flash"; + color =3D ; + function =3D LED_FUNCTION_FLASH; + }; + }; + + rgb { + compatible =3D "samsung,s2mu005-rgb"; + label =3D "notification:rgb:indicator"; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + linux,default-trigger =3D "pattern"; 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t=1769368101; bh=DZSMV0gohpZBSDAPOJEnnJhDmgN21hMhSTPno/RQGic=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=HJbQaU7A7H5fibeuf8n+yH1j+J/Tajbau6z4VY3s6pnVogRvcExW1/4/+Jslb9LRz Ke3+IBBGGqTH17sqyBZO2NSAq91VfgyTVhk7giP8RJAzWbYcxrF/u+I9oE0QzPd0qJ XqfUcvqbQq/VbQRHreYRtyWY656WtXUsg+kfW6KsRvdS+a74cLs+xQLL3w91N/JPZi NXtznndT82ft1hUfouRuLJnLq70MmJ0/eOV9UW1SnhtPIgn5DsozkIWFQYq1Xbdwn5 8uIS/PBRIypg/tQaqaD3A1Q4pRYyUWRkt/9yXpqam+Qd9Js97hFpKdSL3ORJ+ddAQ1 NHyNjpJffGRrg== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:13 +0530 Subject: [PATCH v2 06/12] mfd: sec: add support for S2MU005 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-6-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. S2MU005's interrupt registers can be properly divided into three regmap IRQ chips, one each for the charger, flash LEDs, and the MUIC. Add initial support for S2MU005 in the PMIC driver, along with it's three interrupt chips. Signed-off-by: Kaustabh Chakraborty --- drivers/mfd/sec-common.c | 16 ++ drivers/mfd/sec-i2c.c | 12 ++ drivers/mfd/sec-irq.c | 74 ++++++++ include/linux/mfd/samsung/core.h | 1 + include/linux/mfd/samsung/irq.h | 66 ++++++++ include/linux/mfd/samsung/s2mu005.h | 328 ++++++++++++++++++++++++++++++++= ++++ 6 files changed, 497 insertions(+) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index 0021f9ae8484f..bc2a1f2c6dc7a 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -99,6 +99,18 @@ static const struct mfd_cell s2mpu05_devs[] =3D { MFD_CELL_RES("s2mps15-rtc", s2mpu05_rtc_resources), }; =20 +static const struct resource s2mu005_muic_resources[] =3D { + DEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_ATTACH, "attach"), + DEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_DETACH, "detach"), +}; + +static const struct mfd_cell s2mu005_devs[] =3D { + MFD_CELL_OF("s2mu005-charger", NULL, NULL, 0, 0, "samsung,s2mu005-charger= "), + MFD_CELL_OF("s2mu005-flash", NULL, NULL, 0, 0, "samsung,s2mu005-flash"), + MFD_CELL_OF("s2mu005-muic", s2mu005_muic_resources, NULL, 0, 0, "samsung,= s2mu005-muic"), + MFD_CELL_OF("s2mu005-rgb", NULL, NULL, 0, 0, "samsung,s2mu005-rgb"), +}; + static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) { unsigned int val; @@ -235,6 +247,10 @@ int sec_pmic_probe(struct device *dev, int device_type= , unsigned int irq, sec_devs =3D s2mpu05_devs; num_sec_devs =3D ARRAY_SIZE(s2mpu05_devs); break; + case S2MU005: + sec_devs =3D s2mu005_devs; + num_sec_devs =3D ARRAY_SIZE(s2mu005_devs); + break; default: return dev_err_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", diff --git a/drivers/mfd/sec-i2c.c b/drivers/mfd/sec-i2c.c index 3132b849b4bc4..3f1d70cc3292b 100644 --- a/drivers/mfd/sec-i2c.c +++ b/drivers/mfd/sec-i2c.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -130,6 +131,11 @@ static const struct regmap_config s2mpu05_regmap_confi= g =3D { .val_bits =3D 8, }; =20 +static const struct regmap_config s2mu005_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, +}; + static const struct regmap_config s5m8767_regmap_config =3D { .reg_bits =3D 8, .val_bits =3D 8, @@ -203,6 +209,11 @@ static const struct sec_pmic_i2c_platform_data s2mpu05= _data =3D { .device_type =3D S2MPU05, }; =20 +static const struct sec_pmic_i2c_platform_data s2mu005_data =3D { + .regmap_cfg =3D &s2mu005_regmap_config, + .device_type =3D S2MU005, +}; + static const struct sec_pmic_i2c_platform_data s5m8767_data =3D { .regmap_cfg =3D &s5m8767_regmap_config, .device_type =3D S5M8767X, @@ -217,6 +228,7 @@ static const struct of_device_id sec_pmic_i2c_of_match[= ] =3D { { .compatible =3D "samsung,s2mps15-pmic", .data =3D &s2mps15_data, }, { .compatible =3D "samsung,s2mpu02-pmic", .data =3D &s2mpu02_data, }, { .compatible =3D "samsung,s2mpu05-pmic", .data =3D &s2mpu05_data, }, + { .compatible =3D "samsung,s2mu005-pmic", .data =3D &s2mu005_data, }, { .compatible =3D "samsung,s5m8767-pmic", .data =3D &s5m8767_data, }, { }, }; diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index 4c0faf4c99893..44a1eb074a082 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include "sec-core.h" @@ -164,6 +165,65 @@ static const struct regmap_irq s2mpu05_irqs[] =3D { REGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK), }; =20 +static const struct regmap_irq s2mu005_irqs[] =3D { + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_DETBAT, 0, S2MU005_IRQ_CHGR_DETBAT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_BAT, 0, S2MU005_IRQ_CHGR_BAT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_IVR, 0, S2MU005_IRQ_CHGR_IVR_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_EVENT, 0, S2MU005_IRQ_CHGR_EVENT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_CHG, 0, S2MU005_IRQ_CHGR_CHG_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VMID, 0, S2MU005_IRQ_CHGR_VMID_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_WCIN, 0, S2MU005_IRQ_CHGR_WCIN_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VBUS, 0, S2MU005_IRQ_CHGR_VBUS_MASK), + + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_LBPROT, 1, S2MU005_IRQ_FLED_LBPROT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH2, 1, S2MU005_IRQ_FLED_OPENCH2_MASK= ), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH1, 1, S2MU005_IRQ_FLED_OPENCH1_MASK= ), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH2, 1, S2MU005_IRQ_FLED_SHORTCH2_MA= SK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH1, 1, S2MU005_IRQ_FLED_SHORTCH1_MA= SK), + + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ATTACH, 2, S2MU005_IRQ_MUIC_ATTACH_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_DETACH, 2, S2MU005_IRQ_MUIC_DETACH_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_KP, 2, S2MU005_IRQ_MUIC_KP_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKP, 2, S2MU005_IRQ_MUIC_LKP_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKR, 2, S2MU005_IRQ_MUIC_LKR_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RIDCHG, 2, S2MU005_IRQ_MUIC_RIDCHG_MASK), + + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSON, 3, S2MU005_IRQ_MUIC_VBUSON_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RSVD, 3, S2MU005_IRQ_MUIC_RSVD_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ADC, 3, S2MU005_IRQ_MUIC_ADC_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCK, 3, S2MU005_IRQ_MUIC_STUCK_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCKRCV, 3, S2MU005_IRQ_MUIC_STUCKRCV_MA= SK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_MHDL, 3, S2MU005_IRQ_MUIC_MHDL_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_AVCHG, 3, S2MU005_IRQ_MUIC_AVCHG_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSOFF, 3, S2MU005_IRQ_MUIC_VBUSOFF_MASK= ), +}; + +static unsigned int s2mu005_irq_get_reg(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + const unsigned int irqf_regs[] =3D { + S2MU005_REG_CHGR_INT1, + S2MU005_REG_FLED_INT1, + S2MU005_REG_MUIC_INT1, + S2MU005_REG_MUIC_INT2, + }; + const unsigned int mask_regs[] =3D { + S2MU005_REG_CHGR_INT1M, + S2MU005_REG_FLED_INT1M, + S2MU005_REG_MUIC_INT1M, + S2MU005_REG_MUIC_INT2M, + }; + + switch (base) { + case irqf_regs[0]: + return irqf_regs[index]; + case mask_regs[0]: + return mask_regs[index]; + } + + return base; +} + static const struct regmap_irq s5m8767_irqs[] =3D { REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK), REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK), @@ -259,6 +319,17 @@ static const struct regmap_irq_chip s2mpu05_irq_chip = =3D { .ack_base =3D S2MPU05_REG_INT1, }; =20 +static const struct regmap_irq_chip s2mu005_irq_chip =3D { + .name =3D "s2mu005", + .irqs =3D s2mu005_irqs, + .num_irqs =3D ARRAY_SIZE(s2mu005_irqs), + .num_regs =3D 4, + .status_base =3D S2MU005_REG_CHGR_INT1, + .mask_base =3D S2MU005_REG_CHGR_INT1M, + .ack_base =3D S2MU005_REG_CHGR_INT1, + .get_irq_reg =3D s2mu005_irq_get_reg, +}; + static const struct regmap_irq_chip s5m8767_irq_chip =3D { .name =3D "s5m8767", .irqs =3D s5m8767_irqs, @@ -358,6 +429,9 @@ struct regmap_irq_chip_data *sec_irq_init(struct sec_pm= ic_dev *sec_pmic) case S2MPU05: sec_irq_chip =3D &s2mpu05_irq_chip; break; + case S2MU005: + sec_irq_chip =3D &s2mu005_irq_chip; + break; default: return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device typ= e %d\n", sec_pmic->device_type); diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/c= ore.h index c7c3c8cd8d5f9..43e0c5e55f5d3 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -46,6 +46,7 @@ enum sec_device_type { S2MPS15X, S2MPU02, S2MPU05, + S2MU005, }; =20 /** diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/ir= q.h index 8402a5f8e18ab..936369a733a1c 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -303,6 +303,72 @@ enum s2mpu05_irq { #define S2MPU05_IRQ_INT140C_MASK BIT(1) #define S2MPU05_IRQ_TSD_MASK BIT(2) =20 +enum s2mu005_irq { + S2MU005_IRQ_CHGR_DETBAT, + S2MU005_IRQ_CHGR_BAT, + S2MU005_IRQ_CHGR_IVR, + S2MU005_IRQ_CHGR_EVENT, + S2MU005_IRQ_CHGR_CHG, + S2MU005_IRQ_CHGR_VMID, + S2MU005_IRQ_CHGR_WCIN, + S2MU005_IRQ_CHGR_VBUS, + + S2MU005_IRQ_FLED_LBPROT, + S2MU005_IRQ_FLED_OPENCH2, + S2MU005_IRQ_FLED_OPENCH1, + S2MU005_IRQ_FLED_SHORTCH2, + S2MU005_IRQ_FLED_SHORTCH1, + + S2MU005_IRQ_MUIC_ATTACH, + S2MU005_IRQ_MUIC_DETACH, + S2MU005_IRQ_MUIC_KP, + S2MU005_IRQ_MUIC_LKP, + S2MU005_IRQ_MUIC_LKR, + S2MU005_IRQ_MUIC_RIDCHG, + + S2MU005_IRQ_MUIC_VBUSON, + S2MU005_IRQ_MUIC_RSVD, + S2MU005_IRQ_MUIC_ADC, + S2MU005_IRQ_MUIC_STUCK, + S2MU005_IRQ_MUIC_STUCKRCV, + S2MU005_IRQ_MUIC_MHDL, + S2MU005_IRQ_MUIC_AVCHG, + S2MU005_IRQ_MUIC_VBUSOFF, + + S2MU005_IRQ_NR, +}; + +#define S2MU005_IRQ_CHGR_DETBAT_MASK BIT(0) +#define S2MU005_IRQ_CHGR_BAT_MASK BIT(1) +#define S2MU005_IRQ_CHGR_IVR_MASK BIT(2) +#define S2MU005_IRQ_CHGR_EVENT_MASK BIT(3) +#define S2MU005_IRQ_CHGR_CHG_MASK BIT(4) +#define S2MU005_IRQ_CHGR_VMID_MASK BIT(5) +#define S2MU005_IRQ_CHGR_WCIN_MASK BIT(6) +#define S2MU005_IRQ_CHGR_VBUS_MASK BIT(7) + +#define S2MU005_IRQ_FLED_LBPROT_MASK BIT(2) +#define S2MU005_IRQ_FLED_OPENCH2_MASK BIT(4) +#define S2MU005_IRQ_FLED_OPENCH1_MASK BIT(5) +#define S2MU005_IRQ_FLED_SHORTCH2_MASK BIT(6) +#define S2MU005_IRQ_FLED_SHORTCH1_MASK BIT(7) + +#define S2MU005_IRQ_MUIC_ATTACH_MASK BIT(0) +#define S2MU005_IRQ_MUIC_DETACH_MASK BIT(1) +#define S2MU005_IRQ_MUIC_KP_MASK BIT(2) +#define S2MU005_IRQ_MUIC_LKP_MASK BIT(3) +#define S2MU005_IRQ_MUIC_LKR_MASK BIT(4) +#define S2MU005_IRQ_MUIC_RIDCHG_MASK BIT(5) + +#define S2MU005_IRQ_MUIC_VBUSON_MASK BIT(0) +#define S2MU005_IRQ_MUIC_RSVD_MASK BIT(1) +#define S2MU005_IRQ_MUIC_ADC_MASK BIT(2) +#define S2MU005_IRQ_MUIC_STUCK_MASK BIT(3) +#define S2MU005_IRQ_MUIC_STUCKRCV_MASK BIT(4) +#define S2MU005_IRQ_MUIC_MHDL_MASK BIT(5) +#define S2MU005_IRQ_MUIC_AVCHG_MASK BIT(6) +#define S2MU005_IRQ_MUIC_VBUSOFF_MASK BIT(7) + enum s5m8767_irq { S5M8767_IRQ_PWRR, S5M8767_IRQ_PWRF, diff --git a/include/linux/mfd/samsung/s2mu005.h b/include/linux/mfd/samsun= g/s2mu005.h new file mode 100644 index 0000000000000..32ad35dda661d --- /dev/null +++ b/include/linux/mfd/samsung/s2mu005.h @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2025 Kaustabh Chakraborty + */ + +#ifndef __LINUX_MFD_S2MU005_H +#define __LINUX_MFD_S2MU005_H + +#include +#include + +/* S2MU005 registers */ +enum s2mu005_reg { + S2MU005_REG_CHGR_INT1, + S2MU005_REG_CHGR_INT1M, + + S2MU005_REG_FLED_INT1, + S2MU005_REG_FLED_INT1M, + + S2MU005_REG_MUIC_INT1, + S2MU005_REG_MUIC_INT2, + S2MU005_REG_MUIC_INT1M, + S2MU005_REG_MUIC_INT2M, + + S2MU005_REG_CHGR_STATUS0, + S2MU005_REG_CHGR_STATUS1, + S2MU005_REG_CHGR_STATUS2, + S2MU005_REG_CHGR_STATUS3, + S2MU005_REG_CHGR_STATUS4, + S2MU005_REG_CHGR_STATUS5, + S2MU005_REG_CHGR_CTRL0, + S2MU005_REG_CHGR_CTRL1, + S2MU005_REG_CHGR_CTRL2, + S2MU005_REG_CHGR_CTRL3, + S2MU005_REG_CHGR_CTRL4, + S2MU005_REG_CHGR_CTRL5, + S2MU005_REG_CHGR_CTRL6, + S2MU005_REG_CHGR_CTRL7, + S2MU005_REG_CHGR_CTRL8, + S2MU005_REG_CHGR_CTRL9, + S2MU005_REG_CHGR_CTRL10, + S2MU005_REG_CHGR_CTRL11, + S2MU005_REG_CHGR_CTRL12, + S2MU005_REG_CHGR_CTRL13, + S2MU005_REG_CHGR_CTRL14, + S2MU005_REG_CHGR_CTRL15, + S2MU005_REG_CHGR_CTRL16, + S2MU005_REG_CHGR_CTRL17, + S2MU005_REG_CHGR_CTRL18, + S2MU005_REG_CHGR_CTRL19, + S2MU005_REG_CHGR_TEST0, + S2MU005_REG_CHGR_TEST1, + S2MU005_REG_CHGR_TEST2, + S2MU005_REG_CHGR_TEST3, + S2MU005_REG_CHGR_TEST4, + S2MU005_REG_CHGR_TEST5, + S2MU005_REG_CHGR_TEST6, + S2MU005_REG_CHGR_TEST7, + S2MU005_REG_CHGR_TEST8, + S2MU005_REG_CHGR_TEST9, + S2MU005_REG_CHGR_TEST10, + + S2MU005_REG_FLED_STATUS, + S2MU005_REG_FLED_CH0_CTRL0, + S2MU005_REG_FLED_CH0_CTRL1, + S2MU005_REG_FLED_CH0_CTRL2, + S2MU005_REG_FLED_CH0_CTRL3, + S2MU005_REG_FLED_CH1_CTRL0, + S2MU005_REG_FLED_CH1_CTRL1, + S2MU005_REG_FLED_CH1_CTRL2, + S2MU005_REG_FLED_CH1_CTRL3, + S2MU005_REG_FLED_CTRL0, + S2MU005_REG_FLED_CTRL1, + S2MU005_REG_FLED_CTRL2, + S2MU005_REG_FLED_CTRL3, + S2MU005_REG_FLED_CTRL4, + S2MU005_REG_FLED_CTRL5, + S2MU005_REG_FLED_CTRL6, + + S2MU005_REG_RGB_EN, + S2MU005_REG_RGB_CH0_CTRL, + S2MU005_REG_RGB_CH1_CTRL, + S2MU005_REG_RGB_CH2_CTRL, + S2MU005_REG_RGB_CH0_RAMP, + S2MU005_REG_RGB_CH0_STAY, + S2MU005_REG_RGB_CH1_RAMP, + S2MU005_REG_RGB_CH1_STAY, + S2MU005_REG_RGB_CH2_RAMP, + S2MU005_REG_RGB_CH2_STAY, + S2MU005_REG_RGB_TEST0, + S2MU005_REG_RGB_CTRL0, + + S2MU005_REG_MUIC_ADC, + S2MU005_REG_MUIC_DEV1, + S2MU005_REG_MUIC_DEV2, + S2MU005_REG_MUIC_DEV3, + S2MU005_REG_MUIC_BUTTON1, + S2MU005_REG_MUIC_BUTTON2, + S2MU005_REG_MUIC_RESET, + S2MU005_REG_MUIC_CHGTYPE, + S2MU005_REG_MUIC_DEVAPPLE, + S2MU005_REG_MUIC_BCDRESCAN, + S2MU005_REG_MUIC_TEST1, + S2MU005_REG_MUIC_TEST2, + S2MU005_REG_MUIC_TEST3, + + S2MU005_REG_ID =3D 0x73, + + S2MU005_REG_MUIC_CTRL1 =3D 0xb2, + S2MU005_REG_MUIC_TIMERSET1, + S2MU005_REG_MUIC_TIMERSET2, + S2MU005_REG_MUIC_SWCTRL, + S2MU005_REG_MUIC_TIMERSET3, + S2MU005_REG_MUIC_CTRL2, + S2MU005_REG_MUIC_CTRL3, + + S2MU005_REG_MUIC_LDOADC_L =3D 0xbf, + S2MU005_REG_MUIC_LDOADC_H, +}; + +#define S2MU005_REG_FLED_CH_CTRL0(x) (S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL1(x) (S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL2(x) (S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL3(x) (S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x)) + +#define S2MU005_REG_RGB_CH_CTRL(x) (S2MU005_REG_RGB_CH0_CTRL + 1 * (x)) +#define S2MU005_REG_RGB_CH_RAMP(x) (S2MU005_REG_RGB_CH0_RAMP + 2 * (x)) +#define S2MU005_REG_RGB_CH_STAY(x) (S2MU005_REG_RGB_CH0_STAY + 2 * (x)) + +/* S2MU005_REG_CHGR_STATUS0 */ +#define S2MU005_CHGR_VBUS BIT(7) +#define S2MU005_CHGR_WCIN BIT(6) +#define S2MU005_CHGR_VMID BIT(5) +#define S2MU005_CHGR_CHG BIT(4) +#define S2MU005_CHGR_STAT GENMASK(3, 0) + +#define S2MU005_CHGR_STAT_DONE FIELD_PREP(S2MU005_CHGR_STAT, 8) +#define S2MU005_CHGR_STAT_TOPOFF FIELD_PREP(S2MU005_CHGR_STAT, 7) +#define S2MU005_CHGR_STAT_DONE_FLAG FIELD_PREP(S2MU005_CHGR_STAT, 6) +#define S2MU005_CHGR_STAT_CV FIELD_PREP(S2MU005_CHGR_STAT, 5) +#define S2MU005_CHGR_STAT_CC FIELD_PREP(S2MU005_CHGR_STAT, 4) +#define S2MU005_CHGR_STAT_COOL_CHG FIELD_PREP(S2MU005_CHGR_STAT, 3) +#define S2MU005_CHGR_STAT_PRE_CHG FIELD_PREP(S2MU005_CHGR_STAT, 2) + +/* S2MU005_REG_CHGR_STATUS1 */ +#define S2MU005_CHGR_DETBAT BIT(7) +#define S2MU005_CHGR_VBUSOVP GENMASK(6, 4) + +#define S2MU005_CHGR_VBUS_OVP_OVERVOLT FIELD_PREP(S2MU005_CHGR_OVP, 2) + +/* S2MU005_REG_CHGR_STATUS2 */ +#define S2MU005_CHGR_BAT GENMASK(6, 4) + +#define S2MU005_CHGR_BAT_VOLT_DET FIELD_PREP(S2MU005_CHGR_BAT, 7) +#define S2MU005_CHGR_BAT_FAST_CHG_DET FIELD_PREP(S2MU005_CHGR_BAT, 6) +#define S2MU005_CHGR_BAT_COOL_CHG_DET FIELD_PREP(S2MU005_CHGR_BAT, 5) +#define S2MU005_CHGR_BAT_LOW_CHG FIELD_PREP(S2MU005_CHGR_BAT, 2) +#define S2MU005_CHGR_BAT_SELF_DISCHG FIELD_PREP(S2MU005_CHGR_BAT, 1) +#define S2MU005_CHGR_BAT_OVP_DET FIELD_PREP(S2MU005_CHGR_BAT, 0) + +/* S2MU005_REG_CHGR_STATUS3 */ +#define S2MU005_CHGR_EVT GENMASK(3, 0) + +#define S2MU005_CHGR_EVT_WDT_RST FIELD_PREP(S2MU005_CHGR_EVT, 6) +#define S2MU005_CHGR_EVT_WDT_SUSP FIELD_PREP(S2MU005_CHGR_EVT, 5) +#define S2MU005_CHGR_EVT_VSYS_VUVLO FIELD_PREP(S2MU005_CHGR_EVT, 4) +#define S2MU005_CHGR_EVT_VSYS_VOVP FIELD_PREP(S2MU005_CHGR_EVT, 3) +#define S2MU005_CHGR_EVT_THERM_FOLDBACK FIELD_PREP(S2MU005_CHGR_EVT, 2) +#define S2MU005_CHGR_EVT_THERM_SHUTDOWN FIELD_PREP(S2MU005_CHGR_EVT, 1) + +/* S2MU005_REG_CHGR_CTRL0 */ +#define S2MU005_CHGR_CHG_EN BIT(4) +#define S2MU005_CHGR_OP_MODE GENMASK(2, 0) + +#define S2MU005_CHGR_OP_MODE_OTG FIELD_PREP(S2MU005_CHGR_OP_MODE, BIT(2)) +#define S2MU005_CHGR_OP_MODE_CHG FIELD_PREP(S2MU005_CHGR_OP_MODE, BIT(1)) + +/* S2MU005_REG_CHGR_CTRL1 */ +#define S2MU005_CHGR_VIN_DROP GENMASK(6, 4) + +/* S2MU005_REG_CHGR_CTRL2 */ +#define S2MU005_CHGR_IN_CURR_LIM GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL4 */ +#define S2MU005_CHGR_OTG_OCP_ON BIT(5) +#define S2MU005_CHGR_OTG_OCP_OFF BIT(4) +#define S2MU005_CHGR_OTG_OCP GENMASK(3, 2) + +/* S2MU005_REG_CHGR_CTRL5 */ +#define S2MU005_CHGR_VMID_BOOST GENMASK(4, 0) + +/* S2MU005_REG_CHGR_CTRL6 */ +#define S2MU005_CHGR_COOL_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL7 */ +#define S2MU005_CHGR_FAST_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL8 */ +#define S2MU005_CHGR_VF_VBAT GENMASK(6, 1) + +/* S2MU005_REG_CHGR_CTRL10 */ +#define S2MU005_CHGR_TOPOFF_CURR(x) (GENMASK(3, 0) << 4 * (x)) + +/* S2MU005_REG_CHGR_CTRL11 */ +#define S2MU005_CHGR_OSC_BOOST GENMASK(6, 5) +#define S2MU005_CHGR_OSC_BUCK GENMASK(4, 3) + +/* S2MU005_REG_CHGR_CTRL12 */ +#define S2MU005_CHGR_WDT GENMASK(2, 0) + +#define S2MU005_CHGR_WDT_ON FIELD_PREP(S2MU005_CHGR_WDT, BIT(2)) +#define S2MU005_CHGR_WDT_OFF FIELD_PREP(S2MU005_CHGR_WDT, BIT(1)) + +/* S2MU005_REG_CHGR_CTRL15 */ +#define S2MU005_CHGR_OTG_EN GENMASK(3, 2) + +/* S2MU005_REG_FLED_STATUS */ +#define S2MU005_FLED_FLASH_STATUS(x) (BIT(7) >> 2 * (x)) +#define S2MU005_FLED_TORCH_STATUS(x) (BIT(6) >> 2 * (x)) + +/* S2MU005_REG_FLED_CHx_CTRL0 */ +#define S2MU005_FLED_FLASH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL1 */ +#define S2MU005_FLED_TORCH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL2 */ +#define S2MU005_FLED_TORCH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL3 */ +#define S2MU005_FLED_FLASH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CTRL1 */ +#define S2MU005_FLED_CH_EN BIT(7) + +/* + * S2MU005_REG_FLED_CTRL4 - Rev. EVT0 + * S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later + */ +#define S2MU005_FLED_FLASH_EN(x) (GENMASK(7, 6) >> 4 * (x)) +#define S2MU005_FLED_TORCH_EN(x) (GENMASK(5, 4) >> 4 * (x)) + +/* S2MU005_REG_RGB_EN */ +#define S2MU005_RGB_RESET BIT(6) +#define S2MU005_RGB_SLOPE GENMASK(5, 0) + +#define S2MU005_RGB_SLOPE_CONST (BIT(4) | BIT(2) | BIT(0)) +#define S2MU005_RGB_SLOPE_SMOOTH (BIT(5) | BIT(3) | BIT(1)) + +/* S2MU005_REG_RGB_CHx_RAMP */ +#define S2MU005_RGB_CH_RAMP_UP GENMASK(7, 4) +#define S2MU005_RGB_CH_RAMP_DN GENMASK(3, 0) + +/* S2MU005_REG_RGB_CHx_STAY */ +#define S2MU005_RGB_CH_STAY_HI GENMASK(7, 4) +#define S2MU005_RGB_CH_STAY_LO GENMASK(3, 0) + +/* S2MU005_REG_MUIC_DEV1 */ +#define S2MU005_MUIC_OTG BIT(7) +#define S2MU005_MUIC_DCP BIT(6) +#define S2MU005_MUIC_CDP BIT(5) +#define S2MU005_MUIC_T1_T2_CHG BIT(4) +#define S2MU005_MUIC_UART BIT(3) +#define S2MU005_MUIC_SDP BIT(2) +#define S2MU005_MUIC_LANHUB BIT(1) +#define S2MU005_MUIC_AUDIO BIT(0) + +/* S2MU005_REG_MUIC_DEV2 */ +#define S2MU005_MUIC_SDP_1P8S BIT(7) +#define S2MU005_MUIC_AV BIT(6) +#define S2MU005_MUIC_TTY BIT(5) +#define S2MU005_MUIC_PPD BIT(4) +#define S2MU005_MUIC_JIG_UART_OFF BIT(3) +#define S2MU005_MUIC_JIG_UART_ON BIT(2) +#define S2MU005_MUIC_JIG_USB_OFF BIT(1) +#define S2MU005_MUIC_JIG_USB_ON BIT(0) + +/* S2MU005_REG_MUIC_DEV3 */ +#define S2MU005_MUIC_U200_CHG BIT(7) +#define S2MU005_MUIC_VBUS_AV BIT(4) +#define S2MU005_MUIC_VBUS_R255 BIT(1) +#define S2MU005_MUIC_MHL BIT(0) + +/* S2MU005_REG_MUIC_DEVAPPLE */ +#define S2MU005_MUIC_APPLE_CHG_0P5A BIT(7) +#define S2MU005_MUIC_APPLE_CHG_1P0A BIT(6) +#define S2MU005_MUIC_APPLE_CHG_2P0A BIT(5) +#define S2MU005_MUIC_APPLE_CHG_2P4A BIT(4) +#define S2MU005_MUIC_SDP_DCD_OUT BIT(3) +#define S2MU005_MUIC_RID_WAKEUP BIT(2) +#define S2MU005_MUIC_VBUS_WAKEUP BIT(1) +#define S2MU005_MUIC_BCV1P2_OR_OPEN BIT(0) + +/* S2MU005_REG_ID */ +#define S2MU005_ID_MASK GENMASK(3, 0) +#define S2MU005_ID_SHIFT 0 + +/* S2MU005_REG_MUIC_SWCTRL */ +#define S2MU005_MUIC_DM_DP GENMASK(7, 2) +#define S2MU005_MUIC_JIG BIT(0) + +#define S2MU005_MUIC_DM_DP_UART FIELD_PREP(S2MU005_MUIC_DM_DP, 0x12) +#define S2MU005_MUIC_DM_DP_USB FIELD_PREP(S2MU005_MUIC_DM_DP, 0x09) + +/* S2MU005_REG_MUIC_CTRL1 */ +#define S2MU005_MUIC_OPEN BIT(4) +#define S2MU005_MUIC_RAW_DATA BIT(3) +#define S2MU005_MUIC_MAN_SW BIT(2) +#define S2MU005_MUIC_WAIT BIT(1) +#define S2MU005_MUIC_IRQ BIT(0) + +/* S2MU005_REG_MUIC_CTRL3 */ +#define S2MU005_MUIC_ONESHOT_ADC BIT(2) + +/* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */ +#define S2MU005_MUIC_VSET GENMASK(4, 0) + +#define S2MU005_MUIC_VSET_3P0V FIELD_PREP(S2MU005_MUIC_VSET, 0x1f) +#define S2MU005_MUIC_VSET_2P6V FIELD_PREP(S2MU005_MUIC_VSET, 0x0e) +#define S2MU005_MUIC_VSET_2P4V FIELD_PREP(S2MU005_MUIC_VSET, 0x0c) +#define S2MU005_MUIC_VSET_2P2V FIELD_PREP(S2MU005_MUIC_VSET, 0x0a) +#define S2MU005_MUIC_VSET_2P0V FIELD_PREP(S2MU005_MUIC_VSET, 0x08) +#define S2MU005_MUIC_VSET_1P5V FIELD_PREP(S2MU005_MUIC_VSET, 0x03) +#define S2MU005_MUIC_VSET_1P4V FIELD_PREP(S2MU005_MUIC_VSET, 0x02) +#define S2MU005_MUIC_VSET_1P2V FIELD_PREP(S2MU005_MUIC_VSET, 0x00) + +#endif /* __LINUX_MFD_S2MU005_H */ --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A66E92F28FB; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-7-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty The device revision matters in cases when in some PMICs, the correct register offsets very in different revisions. Instead of just debug printing the value, store it in the driver data struct. Unlike other devices, S2MU005 has its hardware revision ID in register offset 0x73. Allow handling different devices and add support for S2MU005. Signed-off-by: Kaustabh Chakraborty --- drivers/mfd/sec-common.c | 41 ++++++++++++++++++++++++++++++------= ---- include/linux/mfd/samsung/core.h | 1 + 2 files changed, 32 insertions(+), 10 deletions(-) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index bc2a1f2c6dc7a..069a1ba9aa1f1 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -111,17 +112,38 @@ static const struct mfd_cell s2mu005_devs[] =3D { MFD_CELL_OF("s2mu005-rgb", NULL, NULL, 0, 0, "samsung,s2mu005-rgb"), }; =20 -static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) +static int sec_pmic_store_rev(struct sec_pmic_dev *sec_pmic) { - unsigned int val; + unsigned int reg, mask, shift; + int ret; =20 - /* For s2mpg1x, the revision is in a different regmap */ - if (sec_pmic->device_type =3D=3D S2MPG10) - return; + switch (sec_pmic->device_type) { + case S2MPG10: + /* For s2mpg1x, the revision is in a different regmap */ + return 0; + case S2MU005: + reg =3D S2MU005_REG_ID; + mask =3D S2MU005_ID_MASK; + shift =3D S2MU005_ID_SHIFT; + break; + default: + /* For other device types, the REG_ID is always the first register. */ + reg =3D S2MPS11_REG_ID; + mask =3D ~0; + shift =3D 0; + } + + ret =3D regmap_read(sec_pmic->regmap_pmic, reg, &sec_pmic->revision); + if (ret) { + dev_err(sec_pmic->dev, "Failed to read PMIC revision (%d)\n", ret); + return ret; + } + + sec_pmic->revision &=3D mask; + sec_pmic->revision >>=3D shift; =20 - /* For each device type, the REG_ID is always the first register */ - if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) - dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val); + dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", sec_pmic->revision); + return 0; } =20 static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic) @@ -262,9 +284,8 @@ int sec_pmic_probe(struct device *dev, int device_type,= unsigned int irq, return ret; =20 sec_pmic_configure(sec_pmic); - sec_pmic_dump_rev(sec_pmic); =20 - return ret; + return sec_pmic_store_rev(sec_pmic); } EXPORT_SYMBOL_GPL(sec_pmic_probe); =20 diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/c= ore.h index 43e0c5e55f5d3..56aa33d7e3d60 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -70,6 +70,7 @@ struct sec_pmic_dev { =20 int device_type; int irq; + unsigned int revision; }; =20 struct sec_platform_data { --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F3792F1FC2; Sun, 25 Jan 2026 19:08:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368119; cv=none; b=gYDMWSMGJeyZobPcREqX6lIaM7O5uiEgyQxjYP41OduEokT4PvVYhxZQKb2KJkKYkIBpkoZ9dCUPlJjlFhGeVjdeSvdqFeHABVoXBNl8E3Qi2T6Ipzl4MJuTduOfpJ2jTHLwVyIz1BV0UpZIUvXfHR1ghtpbfDj9AYnu4F/RmiI= ARC-Message-Signature: i=1; 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Sun, 25 Jan 2026 20:08:36 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id clKBSZf38ECN; Sun, 25 Jan 2026 20:08:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368114; bh=ZxZv1/mSxcOAffir2fDEH8kGrmmK6VmHkZcHg4bQinI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=M9hEZU1TqtBTA06W1LgLdbzR8bZB92yUCO+frxne86mGmor1WYEo6O4rU4eRiTUPa 3QyT/zThZsBD3ecYZijxFrJic3AokQDXBktMPJlsL2zfZ3cKhQjwFKpE/D5BANOfA+ 3oLbFNh8jjqARwvJg/uWYqUtp/t+3FP38NiaOJPPn/mo3QDcrFzSoq3kIvViPVUxQZ kNUIige+lPdoDuSsYFMrbvccxsriwxkG0idO1XROZt8FKFaAZCCXDyH/2LTuCvOa5i Vjlrk6Z+co8gGXrFrlkyDCujbL5O89UDBB69fYKcNHqBkZy90lrUVjLQnzOou6zWJx e5sT4jwsyHD3A== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:15 +0530 Subject: [PATCH v2 08/12] leds: flash: add support for Samsung S2M series PMIC flash LED device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-8-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add support for flash LEDs found in certain Samsung S2M series PMICs. The device has two channels for LEDs, typically for the back and front cameras in mobile devices. Both channels can be independently controlled, and can be operated in torch or flash modes. The driver includes initial support for the S2MU005 PMIC flash LEDs. Signed-off-by: Kaustabh Chakraborty --- drivers/leds/flash/Kconfig | 12 ++ drivers/leds/flash/Makefile | 1 + drivers/leds/flash/leds-s2m-flash.c | 410 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 423 insertions(+) diff --git a/drivers/leds/flash/Kconfig b/drivers/leds/flash/Kconfig index 5e08102a67841..be62e05277429 100644 --- a/drivers/leds/flash/Kconfig +++ b/drivers/leds/flash/Kconfig @@ -114,6 +114,18 @@ config LEDS_RT8515 To compile this driver as a module, choose M here: the module will be called leds-rt8515. =20 +config LEDS_S2M_FLASH + tristate "Samsung S2M series PMICs flash/torch LED support" + depends on LEDS_CLASS + depends on MFD_SEC_CORE + depends on V4L2_FLASH_LED_CLASS || !V4L2_FLASH_LED_CLASS + select REGMAP_IRQ + help + This option enables support for the flash/torch LEDs found in + certain Samsung S2M series PMICs, such as the S2MU005. It has + a LED channel dedicated for every physical LED. The LEDs can + be controlled in flash and torch modes. + config LEDS_SGM3140 tristate "LED support for the SGM3140" depends on V4L2_FLASH_LED_CLASS || !V4L2_FLASH_LED_CLASS diff --git a/drivers/leds/flash/Makefile b/drivers/leds/flash/Makefile index 712fb737a428e..44e6c1b4beb37 100644 --- a/drivers/leds/flash/Makefile +++ b/drivers/leds/flash/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_LEDS_MAX77693) +=3D leds-max77693.o obj-$(CONFIG_LEDS_QCOM_FLASH) +=3D leds-qcom-flash.o obj-$(CONFIG_LEDS_RT4505) +=3D leds-rt4505.o obj-$(CONFIG_LEDS_RT8515) +=3D leds-rt8515.o +obj-$(CONFIG_LEDS_S2M_FLASH) +=3D leds-s2m-flash.o obj-$(CONFIG_LEDS_SGM3140) +=3D leds-sgm3140.o obj-$(CONFIG_LEDS_SY7802) +=3D leds-sy7802.o obj-$(CONFIG_LEDS_TPS6131X) +=3D leds-tps6131x.o diff --git a/drivers/leds/flash/leds-s2m-flash.c b/drivers/leds/flash/leds-= s2m-flash.c new file mode 100644 index 0000000000000..1be2745c475bf --- /dev/null +++ b/drivers/leds/flash/leds-s2m-flash.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Flash and Torch LED Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2025 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_CHANNELS 2 + +struct s2m_fled { + struct device *dev; + struct regmap *regmap; + struct led_classdev_flash cdev; + struct v4l2_flash *v4l2_flash; + struct mutex lock; + const struct s2m_fled_spec *spec; + unsigned int pmic_revision; + u8 channel; + u8 flash_brightness; + u8 flash_timeout; +}; + +struct s2m_fled_spec { + u8 num_channels; + u32 torch_max_brightness; + u32 flash_min_current_ua; + u32 flash_max_current_ua; + u32 flash_min_timeout_us; + u32 flash_max_timeout_us; + int (*torch_brightness_set_blocking)(struct led_classdev *led_cdev, + enum led_brightness brightness); + const struct led_flash_ops *flash_ops; +}; + +static struct led_classdev_flash *to_cdev_flash(struct led_classdev *cdev) +{ + return container_of(cdev, struct led_classdev_flash, led_cdev); +} + +static struct s2m_fled *to_led_priv(struct led_classdev_flash *cdev) +{ + return container_of(cdev, struct s2m_fled, cdev); +} + +static int s2m_fled_flash_brightness_set(struct led_classdev_flash *cdev, + u32 brightness) +{ + struct s2m_fled *priv =3D to_led_priv(cdev); + struct led_flash_setting *setting =3D &cdev->brightness; + + priv->flash_brightness =3D (brightness - setting->min) / setting->step; + + return 0; +} + +static int s2m_fled_flash_timeout_set(struct led_classdev_flash *cdev, + u32 timeout) +{ + struct s2m_fled *priv =3D to_led_priv(cdev); + struct led_flash_setting *setting =3D &cdev->timeout; + + priv->flash_timeout =3D (timeout - setting->min) / setting->step; + + return 0; +} + +#if IS_ENABLED(CONFIG_V4L2_FLASH_LED_CLASS) +static int s2m_fled_flash_external_strobe_set(struct v4l2_flash *v4l2_flas= h, + bool enable) +{ + struct s2m_fled *priv =3D to_led_priv(v4l2_flash->fled_cdev); + + mutex_lock(&priv->lock); + + priv->cdev.ops->strobe_set(&priv->cdev, enable); + + mutex_unlock(&priv->lock); + + return 0; +} + +static const struct v4l2_flash_ops s2m_fled_v4l2_flash_ops =3D { + .external_strobe_set =3D s2m_fled_flash_external_strobe_set, +}; +#else +static const struct v4l2_flash_ops s2m_fled_v4l2_flash_ops; +#endif + +static int s2mu005_fled_torch_brightness_set(struct led_classdev *cdev, + enum led_brightness value) +{ + struct s2m_fled *priv =3D to_led_priv(to_cdev_flash(cdev)); + struct regmap *regmap =3D priv->regmap; + u8 channel =3D priv->channel; + unsigned int reg_enable; + int ret; + + mutex_lock(&priv->lock); + + /* + * Get the LED enable register address. Revision EVT0 has the + * register at CTRL4, while EVT1 and higher have it at CTRL6. + */ + if (priv->pmic_revision =3D=3D 0) + reg_enable =3D S2MU005_REG_FLED_CTRL4; + else + reg_enable =3D S2MU005_REG_FLED_CTRL6; + + if (value =3D=3D LED_OFF) { + ret =3D regmap_clear_bits(regmap, reg_enable, + S2MU005_FLED_TORCH_EN(channel)); + if (ret < 0) + dev_err(priv->dev, "failed to disable torch LED\n"); + goto unlock; + } + + ret =3D regmap_update_bits(regmap, S2MU005_REG_FLED_CH_CTRL1(channel), + S2MU005_FLED_TORCH_IOUT, + FIELD_PREP(S2MU005_FLED_TORCH_IOUT, value - 1)); + if (ret < 0) { + dev_err(priv->dev, "failed to set torch current\n"); + goto unlock; + } + + ret =3D regmap_set_bits(regmap, reg_enable, S2MU005_FLED_TORCH_EN(channel= )); + if (ret < 0) { + dev_err(priv->dev, "failed to enable torch LED\n"); + goto unlock; + } + +unlock: + mutex_unlock(&priv->lock); + + return ret; +} + +static int s2mu005_fled_flash_strobe_set(struct led_classdev_flash *cdev, + bool state) +{ + struct s2m_fled *priv =3D to_led_priv(cdev); + struct regmap *regmap =3D priv->regmap; + u8 channel =3D priv->channel; + unsigned int reg_enable; + int ret; + + mutex_lock(&priv->lock); + + /* + * Get the LED enable register address. Revision EVT0 has the + * register at CTRL4, while EVT1 and higher have it at CTRL6. + */ + if (priv->pmic_revision =3D=3D 0) + reg_enable =3D S2MU005_REG_FLED_CTRL4; + else + reg_enable =3D S2MU005_REG_FLED_CTRL6; + + ret =3D regmap_clear_bits(regmap, reg_enable, S2MU005_FLED_FLASH_EN(chann= el)); + if (ret < 0) { + dev_err(priv->dev, "failed to disable flash LED\n"); + goto unlock; + } + + if (!state) + goto unlock; + + ret =3D regmap_update_bits(regmap, S2MU005_REG_FLED_CH_CTRL0(channel), + S2MU005_FLED_FLASH_IOUT, + FIELD_PREP(S2MU005_FLED_FLASH_IOUT, + priv->flash_brightness)); + if (ret < 0) { + dev_err(priv->dev, "failed to set flash brightness\n"); + goto unlock; + } + + ret =3D regmap_update_bits(regmap, S2MU005_REG_FLED_CH_CTRL3(channel), + S2MU005_FLED_FLASH_TIMEOUT, + FIELD_PREP(S2MU005_FLED_FLASH_TIMEOUT, + priv->flash_timeout)); + if (ret < 0) { + dev_err(priv->dev, "failed to set flash timeout\n"); + goto unlock; + } + + ret =3D regmap_set_bits(regmap, reg_enable, S2MU005_FLED_FLASH_EN(channel= )); + if (ret < 0) { + dev_err(priv->dev, "failed to enable flash LED\n"); + goto unlock; + } + +unlock: + mutex_unlock(&priv->lock); + + return 0; +} + +static int s2mu005_fled_flash_strobe_get(struct led_classdev_flash *cdev, + bool *state) +{ + struct s2m_fled *priv =3D to_led_priv(cdev); + struct regmap *regmap =3D priv->regmap; + u8 channel =3D priv->channel; + u32 val; + int ret; + + mutex_lock(&priv->lock); + + ret =3D regmap_read(regmap, S2MU005_REG_FLED_STATUS, &val); + if (ret < 0) { + dev_err(priv->dev, "failed to fetch LED status"); + goto unlock; + } + + *state =3D !!(val & S2MU005_FLED_FLASH_STATUS(channel)); + +unlock: + mutex_unlock(&priv->lock); + + return ret; +} + +static const struct led_flash_ops s2mu005_fled_flash_ops =3D { + .flash_brightness_set =3D s2m_fled_flash_brightness_set, + .timeout_set =3D s2m_fled_flash_timeout_set, + .strobe_set =3D s2mu005_fled_flash_strobe_set, + .strobe_get =3D s2mu005_fled_flash_strobe_get, +}; + +static const struct s2m_fled_spec s2mu005_fled_spec =3D { + .num_channels =3D 2, + .torch_max_brightness =3D 16, + .flash_min_current_ua =3D 25000, + .flash_max_current_ua =3D 375000, /* 400000 causes flickering */ + .flash_min_timeout_us =3D 62000, + .flash_max_timeout_us =3D 992000, + .torch_brightness_set_blocking =3D s2mu005_fled_torch_brightness_set, + .flash_ops =3D &s2mu005_fled_flash_ops, +}; + +static int s2m_fled_init_channel(struct device *dev, struct fwnode_handle = *fwnp, + struct s2m_fled *priv) +{ + struct led_classdev *led =3D &priv->cdev.led_cdev; + struct led_init_data init_data =3D {}; + struct v4l2_flash_config v4l2_cfg =3D {}; + int ret; + + led->max_brightness =3D priv->spec->torch_max_brightness; + led->brightness_set_blocking =3D priv->spec->torch_brightness_set_blockin= g; + led->flags |=3D LED_DEV_CAP_FLASH; + + priv->cdev.timeout.min =3D priv->spec->flash_min_timeout_us; + priv->cdev.timeout.step =3D priv->spec->flash_min_timeout_us; + priv->cdev.timeout.max =3D priv->spec->flash_max_timeout_us; + priv->cdev.timeout.val =3D priv->spec->flash_max_timeout_us; + + priv->cdev.brightness.min =3D priv->spec->flash_min_current_ua; + priv->cdev.brightness.step =3D priv->spec->flash_min_current_ua; + priv->cdev.brightness.max =3D priv->spec->flash_max_current_ua; + priv->cdev.brightness.val =3D priv->spec->flash_max_current_ua; + + s2m_fled_flash_timeout_set(&priv->cdev, priv->cdev.timeout.val); + s2m_fled_flash_brightness_set(&priv->cdev, priv->cdev.brightness.val); + + priv->cdev.ops =3D priv->spec->flash_ops; + + init_data.fwnode =3D fwnp; + ret =3D devm_led_classdev_flash_register_ext(dev, &priv->cdev, &init_data= ); + if (ret < 0) { + dev_err(dev, "failed to create LED flash device\n"); + return ret; + } + + v4l2_cfg.intensity.min =3D priv->spec->flash_min_current_ua; + v4l2_cfg.intensity.step =3D priv->spec->flash_min_current_ua; + v4l2_cfg.intensity.max =3D priv->spec->flash_max_current_ua; + v4l2_cfg.intensity.val =3D priv->spec->flash_max_current_ua; + + v4l2_cfg.has_external_strobe =3D true; + + priv->v4l2_flash =3D v4l2_flash_init(dev, fwnp, &priv->cdev, + &s2m_fled_v4l2_flash_ops, &v4l2_cfg); + if (IS_ERR(priv->v4l2_flash)) { + dev_err(dev, "failed to create V4L2 flash device\n"); + v4l2_flash_release(priv->v4l2_flash); + return PTR_ERR(priv->v4l2_flash); + } + + return devm_add_action_or_reset(dev, (void *)v4l2_flash_release, + priv->v4l2_flash); +} + +static int s2m_fled_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *pmic_drvdata =3D dev_get_drvdata(dev->parent); + struct s2m_fled *priv; + struct fwnode_handle *child; + struct regmap *regmap; + const struct s2m_fled_spec *spec; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv) * MAX_CHANNELS, GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, "failed to allocate driver private\n"= ); + + platform_set_drvdata(pdev, priv); + regmap =3D pmic_drvdata->regmap_pmic; + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + spec =3D &s2mu005_fled_spec; + /* Enable the LED channels. */ + ret =3D regmap_set_bits(regmap, S2MU005_REG_FLED_CTRL1, + S2MU005_FLED_CH_EN); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to enable LED channels\n"); + break; + default: + return dev_err_probe(dev, -ENODEV, + "device type %d is not supported by driver\n", + pmic_drvdata->device_type); + } + + device_for_each_child_node(dev, child) { + u32 reg; + + if (fwnode_property_read_u32(child, "reg", ®)) + goto next_child; + + if (reg >=3D spec->num_channels) { + dev_warn(dev, "channel %d is non-existent\n", reg); + goto next_child; + } + + if (priv[reg].dev) { + dev_warn(dev, "duplicate node for channel %d\n", reg); + goto next_child; + } + + priv[reg].dev =3D dev; + priv[reg].regmap =3D regmap; + priv[reg].channel =3D (u8)reg; + priv[reg].spec =3D spec; + priv[reg].pmic_revision =3D pmic_drvdata->revision; + + ret =3D devm_mutex_init(dev, &priv[reg].lock); + if (ret) + return dev_err_probe(dev, ret, "failed to create mutex lock\n"); + + ret =3D s2m_fled_init_channel(dev, child, &priv[reg]); + if (ret < 0) + dev_warn(dev, "channel init failed (%d)\n", ret); + +next_child: + fwnode_handle_put(child); + } + + return 0; +} + +static const struct platform_device_id s2m_fled_id_table[] =3D { + { "s2mu005-flash", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_fled_id_table); + +#ifdef CONFIG_OF +/* + * Device is instantiated through parent MFD device and device matching + * is done through platform_device_id. + * + * However if device's DT node contains proper compatible and driver is + * built as a module, then the *module* matching will be done through DT + * aliases. This requires of_device_id table. In the same time this will + * not change the actual *device* matching so do not add .of_match_table. + */ +static const struct of_device_id s2m_fled_of_match_table[] =3D { + { + .compatible =3D "samsung,s2mu005-flash", + .data =3D (void *)S2MU005, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, s2m_fled_of_match_table); +#endif + +static struct platform_driver s2m_fled_driver =3D { + .driver =3D { + .name =3D "s2m-flash", + }, + .probe =3D s2m_fled_probe, + .id_table =3D s2m_fled_id_table, +}; +module_platform_driver(s2m_fled_driver); + +MODULE_DESCRIPTION("Flash/Torch LED Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2610A8F4A; Sun, 25 Jan 2026 19:08:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368126; cv=none; b=ZRFP2pw09QlZw0l/oba7RVZwzGU+gs6h+OT/w8ZrU7b8yKMwJm5tfvBuMwwumdBkqF7khzOhtRKYAflstJydOj/pJ7mPFwJG/JtsspwG1WMnw0UiTJH7e3n2hgGvuUNzvQDGOCmdQx8JxIiS43Wdeo4AdFHmLooCqgBwy/AWlCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368126; c=relaxed/simple; bh=HIcF/ZD87Z6ZpiLN/KZqlptLT3/nfDt6Nqpj/3KyC6s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sz/6ZgkjdOSlxJCXHvF1o89QhBcWbwe+ebIH6zJqrCbJh1JKHZ1ajbAJeopkvZvEo74AkSn1DHgkjbJ/zUlhZSfYtyaA2mCRP4J/hwz4zsfRbpZ5me0E35zi2PtC3ohDyZR/VbYNuL5CCXCw9EdYGYKwOGA0m0+2d5TWOg65CF4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=IUzJgE4J; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="IUzJgE4J" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id CDCCD27BF6; Sun, 25 Jan 2026 20:08:42 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 5cxRGa40buKL; Sun, 25 Jan 2026 20:08:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368121; bh=HIcF/ZD87Z6ZpiLN/KZqlptLT3/nfDt6Nqpj/3KyC6s=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=IUzJgE4JIdu0KawawPcBbHxgCdjOQHb4x++PK+Y0TUvjFkHIFaSO1KL2vMCBWkjzW xTtyZlTNsOr0vWQ/tjwm7oT9oTcgyg98D9DzOpdyo5YzS0MFOC+/9D9ss2tsTaq+ec PIDDmKYwzYm/2erP/Mfd5TSzUBRQJiTnlQRRjqt5zyrtRB3cYcHxa21OuXAl+mxNQ/ f6BD5pEn3abQCKNIrxjZgP//LGC0zLizehWgZ3zKKBCAPMbCpQC9d/hv+mGawBUIX3 3bbyfhctvfeaMnz6s8yNsukcKRFmDvsmQbM6iASUyhY4mVhLXKi+DbQv8pPwS9TOOk rMSaPbiu5xOUw== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:16 +0530 Subject: [PATCH v2 09/12] leds: rgb: add support for Samsung S2M series PMIC RGB LED device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-9-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add support for the RGB LEDs found in certain Samsung S2M series PMICs. The device has three LED channels, controlled as a single device. These LEDs are typically used as status indicators in mobile phones. The driver includes initial support for the S2MU005 PMIC RGB LEDs. Signed-off-by: Kaustabh Chakraborty --- drivers/leds/rgb/Kconfig | 11 + drivers/leds/rgb/Makefile | 1 + drivers/leds/rgb/leds-s2m-rgb.c | 460 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 472 insertions(+) diff --git a/drivers/leds/rgb/Kconfig b/drivers/leds/rgb/Kconfig index 222d943d826aa..e38ba1bd434e9 100644 --- a/drivers/leds/rgb/Kconfig +++ b/drivers/leds/rgb/Kconfig @@ -62,6 +62,17 @@ config LEDS_QCOM_LPG =20 If compiled as a module, the module will be named leds-qcom-lpg. =20 +config LEDS_S2M_RGB + tristate "Samsung S2M series PMICs RGB LED support" + depends on LEDS_CLASS + depends on MFD_SEC_CORE + select REGMAP_IRQ + help + This option enables support for the S2MU005 RGB LEDs. These + devices have three LED channels, with 8-bit brightness control + for each channel. It's usually found in mobile phones as + status indicators. + config LEDS_MT6370_RGB tristate "LED Support for MediaTek MT6370 PMIC" depends on MFD_MT6370 diff --git a/drivers/leds/rgb/Makefile b/drivers/leds/rgb/Makefile index a501fd27f1793..fc9d38fa60e1d 100644 --- a/drivers/leds/rgb/Makefile +++ b/drivers/leds/rgb/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_LEDS_KTD202X) +=3D leds-ktd202x.o obj-$(CONFIG_LEDS_NCP5623) +=3D leds-ncp5623.o obj-$(CONFIG_LEDS_PWM_MULTICOLOR) +=3D leds-pwm-multicolor.o obj-$(CONFIG_LEDS_QCOM_LPG) +=3D leds-qcom-lpg.o +obj-$(CONFIG_LEDS_S2M_RGB) +=3D leds-s2m-rgb.o obj-$(CONFIG_LEDS_MT6370_RGB) +=3D leds-mt6370-rgb.o diff --git a/drivers/leds/rgb/leds-s2m-rgb.c b/drivers/leds/rgb/leds-s2m-rg= b.c new file mode 100644 index 0000000000000..dd304be6c65c8 --- /dev/null +++ b/drivers/leds/rgb/leds-s2m-rgb.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RGB LED Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2025 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct s2m_rgb { + struct device *dev; + struct regmap *regmap; + struct led_classdev_mc cdev; + struct mutex lock; + const struct s2m_rgb_spec *spec; + u8 ramp_up; + u8 ramp_dn; + u8 stay_hi; + u8 stay_lo; +}; + +struct s2m_rgb_spec { + int (*params_apply)(struct s2m_rgb *priv); + int (*params_reset)(struct s2m_rgb *priv); + const u32 *lut_ramp_up; + const size_t lut_ramp_up_len; + const u32 *lut_ramp_dn; + const size_t lut_ramp_dn_len; + const u32 *lut_stay_hi; + const size_t lut_stay_hi_len; + const u32 *lut_stay_lo; + const size_t lut_stay_lo_len; + const unsigned int max_brightness; +}; + +static struct led_classdev_mc *to_cdev_mc(struct led_classdev *cdev) +{ + return container_of(cdev, struct led_classdev_mc, led_cdev); +} + +static struct s2m_rgb *to_rgb_priv(struct led_classdev_mc *cdev) +{ + return container_of(cdev, struct s2m_rgb, cdev); +} + +static int s2m_rgb_lut_calc_timing(const u32 *lut, const size_t len, + const u32 req_time, u8 *idx) +{ + int lo =3D 0; + int hi =3D len - 2; + + /* Bounds checking */ + if (req_time < lut[0] || req_time > lut[len - 1]) + return -EINVAL; + + /* + * Perform a binary search to pick the best timing from the LUT. + * + * The search algorithm picks two consecutive elements of the + * LUT and tries to search the pair between which the requested + * time lies. + */ + while (lo <=3D hi) { + *idx =3D (lo + hi) / 2; + + if ((lut[*idx] <=3D req_time) && (req_time <=3D lut[*idx + 1])) + break; + + if ((req_time < lut[*idx]) && (req_time < lut[*idx + 1])) + hi =3D *idx - 1; + else + lo =3D *idx + 1; + } + + /* + * The searched timing is always less than the requested time. At + * times, the succeeding timing in the LUT is closer thus more + * accurate. Adjust the resulting value if that's the case. + */ + if (abs(req_time - lut[*idx]) > abs(lut[*idx + 1] - req_time)) + (*idx)++; + + return 0; +} + +static int s2m_rgb_brightness_set(struct led_classdev *cdev, + enum led_brightness value) +{ + struct s2m_rgb *priv =3D to_rgb_priv(to_cdev_mc(cdev)); + int ret; + + mutex_lock(&priv->lock); + + led_mc_calc_color_components(&priv->cdev, value); + + if (value =3D=3D LED_OFF) + ret =3D priv->spec->params_reset(priv); + else + ret =3D priv->spec->params_apply(priv); + + mutex_unlock(&priv->lock); + + return ret; +} + +static int s2m_rgb_pattern_set(struct led_classdev *cdev, + struct led_pattern *pattern, u32 len, int repeat) +{ + struct s2m_rgb *priv =3D to_rgb_priv(to_cdev_mc(cdev)); + int brightness_peak =3D 0; + u32 time_hi =3D 0; + u32 time_lo =3D 0; + bool ramp_up_en; + bool ramp_dn_en; + int ret; + int i; + + /* + * The typical pattern supported by this device can be + * represented with the following graph: + * + * 255 T ''''''-. .-'''''''-. + * | '. .' '. + * | \ / \ + * | '. .' '. + * | '-...........-' '- + * 0 +----------------------------------------------------> time (s) + * + * <---- HIGH ----><-- LOW --><-------- HIGH ---------> + * <-----><-------><---------><-------><-----><-------> + * stay_hi ramp_dn stay_lo ramp_up stay_hi ramp_dn + * + * There are two states, named HIGH and LOW. HIGH has a non-zero + * brightness level, while LOW is of zero brightness. The + * pattern provided should mention only one zero and non-zero + * brightness level. The hardware always starts the pattern from + * the HIGH state, as shown in the graph. + * + * The HIGH state can be divided in three somewhat equal timings: + * ramp_up, stay_hi, and ramp_dn. The LOW state has only one + * timing: stay_lo. + */ + + /* Only indefinitely looping patterns are supported. */ + if (repeat !=3D -1) + return -EINVAL; + + /* Pattern should consist of at least two tuples. */ + if (len < 2) + return -EINVAL; + + for (i =3D 0; i < len; i++) { + int brightness =3D pattern[i].brightness; + u32 delta_t =3D pattern[i].delta_t; + + if (brightness) { + /* + * The pattern shold define only one non-zero + * brightness in the HIGH state. The device + * doesn't have any provisions to handle + * multiple peak brightness levels. + */ + if (brightness_peak && brightness_peak !=3D brightness) + return -EINVAL; + + brightness_peak =3D brightness; + time_hi +=3D delta_t; + ramp_dn_en =3D !!delta_t; + } else { + time_lo +=3D delta_t; + ramp_up_en =3D !!delta_t; + } + } + + mutex_lock(&priv->lock); + + /* + * The timings ramp_up, stay_hi, and ramp_dn of the HIGH state + * are roughly equal. Firstly, calculate and set timings for + * ramp_up and ramp_dn (making sure they're exactly equal). + */ + priv->ramp_up =3D 0; + priv->ramp_dn =3D 0; + + if (ramp_up_en) { + ret =3D s2m_rgb_lut_calc_timing(priv->spec->lut_ramp_up, + priv->spec->lut_ramp_up_len, + time_hi / 3, &priv->ramp_up); + if (ret < 0) + goto param_fail; + } + + if (ramp_dn_en) { + ret =3D s2m_rgb_lut_calc_timing(priv->spec->lut_ramp_dn, + priv->spec->lut_ramp_dn_len, + time_hi / 3, &priv->ramp_dn); + if (ret < 0) + goto param_fail; + } + + /* + * Subtract the allocated ramp timings from time_hi (and also + * making sure it doesn't underflow!). The remaining time is + * allocated to stay_hi. + */ + time_hi -=3D min(time_hi, priv->spec->lut_ramp_up[priv->ramp_up]); + time_hi -=3D min(time_hi, priv->spec->lut_ramp_dn[priv->ramp_dn]); + + ret =3D s2m_rgb_lut_calc_timing(priv->spec->lut_stay_hi, + priv->spec->lut_stay_hi_len, time_hi, + &priv->stay_hi); + if (ret < 0) + goto param_fail; + + ret =3D s2m_rgb_lut_calc_timing(priv->spec->lut_stay_lo, + priv->spec->lut_stay_lo_len, time_lo, + &priv->stay_lo); + if (ret < 0) + goto param_fail; + + led_mc_calc_color_components(&priv->cdev, brightness_peak); + ret =3D priv->spec->params_apply(priv); + if (ret < 0) + goto param_fail; + + mutex_unlock(&priv->lock); + + return 0; + +param_fail: + mutex_unlock(&priv->lock); + priv->ramp_up =3D 0; + priv->ramp_dn =3D 0; + priv->stay_hi =3D 0; + priv->stay_lo =3D 0; + + return ret; +} + +static int s2m_rgb_pattern_clear(struct led_classdev *cdev) +{ + struct s2m_rgb *priv =3D to_rgb_priv(to_cdev_mc(cdev)); + int ret; + + mutex_lock(&priv->lock); + + ret =3D priv->spec->params_reset(priv); + + mutex_unlock(&priv->lock); + + return ret; +} + +static int s2mu005_rgb_apply_params(struct s2m_rgb *priv) +{ + struct regmap *regmap =3D priv->regmap; + unsigned int ramp_val =3D 0; + unsigned int stay_val =3D 0; + int ret; + int i; + + ramp_val |=3D FIELD_PREP(S2MU005_RGB_CH_RAMP_UP, priv->ramp_up); + ramp_val |=3D FIELD_PREP(S2MU005_RGB_CH_RAMP_DN, priv->ramp_dn); + + stay_val |=3D FIELD_PREP(S2MU005_RGB_CH_STAY_HI, priv->stay_hi); + stay_val |=3D FIELD_PREP(S2MU005_RGB_CH_STAY_LO, priv->stay_lo); + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_EN, S2MU005_RGB_RESET); + if (ret < 0) { + dev_err(priv->dev, "failed to reset RGB LEDs\n"); + return ret; + } + + for (i =3D 0; i < priv->cdev.num_colors; i++) { + ret =3D regmap_write(regmap, S2MU005_REG_RGB_CH_CTRL(i), + priv->cdev.subled_info[i].brightness); + if (ret < 0) { + dev_err(priv->dev, "failed to set LED brightness\n"); + return ret; + } + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_CH_RAMP(i), ramp_val); + if (ret < 0) { + dev_err(priv->dev, "failed to set ramp timings\n"); + return ret; + } + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_CH_STAY(i), stay_val); + if (ret < 0) { + dev_err(priv->dev, "failed to set stay timings\n"); + return ret; + } + } + + ret =3D regmap_update_bits(regmap, S2MU005_REG_RGB_EN, S2MU005_RGB_SLOPE, + S2MU005_RGB_SLOPE_SMOOTH); + if (ret < 0) { + dev_err(priv->dev, "failed to set ramp slope\n"); + return ret; + } + + return 0; +} + +static int s2mu005_rgb_reset_params(struct s2m_rgb *priv) +{ + struct regmap *regmap =3D priv->regmap; + int ret; + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_EN, S2MU005_RGB_RESET); + if (ret < 0) { + dev_err(priv->dev, "failed to reset RGB LEDs\n"); + return ret; + } + + priv->ramp_up =3D 0; + priv->ramp_dn =3D 0; + priv->stay_hi =3D 0; + priv->stay_lo =3D 0; + + return 0; +} + +static const u32 s2mu005_rgb_lut_ramp[] =3D { + 0, 100, 200, 300, 400, 500, 600, 700, + 800, 1000, 1200, 1400, 1600, 1800, 2000, 2200, +}; + +static const u32 s2mu005_rgb_lut_stay_hi[] =3D { + 100, 200, 300, 400, 500, 750, 1000, 1250, + 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250, +}; + +static const u32 s2mu005_rgb_lut_stay_lo[] =3D { + 0, 500, 1000, 1500, 2000, 2500, 3000, 3500, + 4000, 4500, 5000, 6000, 7000, 8000, 10000, 12000, +}; + +static const struct s2m_rgb_spec s2mu005_rgb_spec =3D { + .params_apply =3D s2mu005_rgb_apply_params, + .params_reset =3D s2mu005_rgb_reset_params, + .lut_ramp_up =3D s2mu005_rgb_lut_ramp, + .lut_ramp_up_len =3D ARRAY_SIZE(s2mu005_rgb_lut_ramp), + .lut_ramp_dn =3D s2mu005_rgb_lut_ramp, + .lut_ramp_dn_len =3D ARRAY_SIZE(s2mu005_rgb_lut_ramp), + .lut_stay_hi =3D s2mu005_rgb_lut_stay_hi, + .lut_stay_hi_len =3D ARRAY_SIZE(s2mu005_rgb_lut_stay_hi), + .lut_stay_lo =3D s2mu005_rgb_lut_stay_lo, + .lut_stay_lo_len =3D ARRAY_SIZE(s2mu005_rgb_lut_stay_lo), + .max_brightness =3D 255, +}; + +static struct mc_subled s2mu005_rgb_subled_info[] =3D { + { + .channel =3D 0, + .color_index =3D LED_COLOR_ID_BLUE, + }, { + .channel =3D 1, + .color_index =3D LED_COLOR_ID_GREEN, + }, { + .channel =3D 2, + .color_index =3D LED_COLOR_ID_RED, + }, +}; + +static int s2m_rgb_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *pmic_drvdata =3D dev_get_drvdata(dev->parent); + struct s2m_rgb *priv; + struct led_init_data init_data =3D {}; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, "failed to allocate driver private\n"= ); + + platform_set_drvdata(pdev, priv); + priv->dev =3D dev; + priv->regmap =3D pmic_drvdata->regmap_pmic; + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + priv->spec =3D &s2mu005_rgb_spec; + priv->cdev.subled_info =3D s2mu005_rgb_subled_info; + priv->cdev.num_colors =3D ARRAY_SIZE(s2mu005_rgb_subled_info); + break; + default: + return dev_err_probe(dev, -ENODEV, + "device type %d is not supported by driver\n", + pmic_drvdata->device_type); + } + + priv->cdev.led_cdev.max_brightness =3D priv->spec->max_brightness; + priv->cdev.led_cdev.brightness_set_blocking =3D s2m_rgb_brightness_set; + priv->cdev.led_cdev.pattern_set =3D s2m_rgb_pattern_set; + priv->cdev.led_cdev.pattern_clear =3D s2m_rgb_pattern_clear; + + ret =3D devm_mutex_init(dev, &priv->lock); + if (ret) + return dev_err_probe(dev, ret, "failed to create mutex lock\n"); + + init_data.fwnode =3D of_fwnode_handle(dev->of_node); + ret =3D devm_led_classdev_multicolor_register_ext(dev, &priv->cdev, + &init_data); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to create LED device\n"); + + return 0; +} + +static const struct platform_device_id s2m_rgb_id_table[] =3D { + { "s2mu005-rgb", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_rgb_id_table); + +#ifdef CONFIG_OF +/* + * Device is instantiated through parent MFD device and device matching + * is done through platform_device_id. + * + * However if device's DT node contains proper compatible and driver is + * built as a module, then the *module* matching will be done through DT + * aliases. This requires of_device_id table. In the same time this will + * not change the actual *device* matching so do not add .of_match_table. + */ +static const struct of_device_id s2m_rgb_of_match_table[] =3D { + { + .compatible =3D "samsung,s2mu005-rgb", + .data =3D (void *)S2MU005, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, s2m_rgb_of_match_table); +#endif + +static struct platform_driver s2m_rgb_driver =3D { + .driver =3D { + .name =3D "s2m-rgb", + }, + .probe =3D s2m_rgb_probe, + .id_table =3D s2m_rgb_id_table, +}; +module_platform_driver(s2m_rgb_driver); + +MODULE_DESCRIPTION("RGB LED Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69ED92F1FF4; Sun, 25 Jan 2026 19:08:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368130; cv=none; b=SyRQXX5mrI41zlDsq//GVneXyMcqgvEu0rZWG6UDK7p2j4P/CfHn1NCn23QkX7fofk+eACDrKqhq/UHNIgjriDgn3lA+/r4KoG2Jv4+IGIVjKHq2vUswzaNTpizVCF36l2i8CWpm+/qPVFYqnhvpvJ6LrRbS4NrXW+tPmj19BCU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368130; c=relaxed/simple; bh=9yWBI+gYov2ELwPEW/EaRpgooS+fd0CmNyD5hHzzb0w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aSzht5sur0+jAVmgT/QH/b+mqSJ+nXao+e2SV7OJLVrQfXfDCsydgnGiUnFYZwImm70jy11NcYm5qE/IAaFZLZd1roIy7ayZmoWSXZtm0B3tfsqwtq27aGvA5PC4PiZutuXuanrPkAhbdRqPMVOtoTEfJLSpWqPIsoq5Xx2u3wY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=O4EZu5wz; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="O4EZu5wz" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 1302B2808A; Sun, 25 Jan 2026 20:08:48 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id XrrZa3dgvy94; Sun, 25 Jan 2026 20:08:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368127; bh=9yWBI+gYov2ELwPEW/EaRpgooS+fd0CmNyD5hHzzb0w=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=O4EZu5wz2wFjdZB/Z49AB3movTpgseYvABkQ4Te9oOAKs+ea61sqWtBFtGmInMstx H/gMKfi3gtqiZyGEmYtvXGmW0LWcgoV1xKu6HcKM2/ciPF2nzTw6h10SFmkTTWkbiG +9E96QA43KbzPBRx6vT/g5UxtH5XON0KHTGlfJXXQsO/1DAaHZAC8fnaSkgfszJsw6 xt0tUqDZSPfaj116zNl8pay7BzT+x2Tn+K5GiuFL0NGkJKIlhQU4dFNcNtq3fZ3Unv rhBdq/8Q2+OcuaoXajHs1KqKBFFqU2UuRuQkhjbaPgXXAmr1I46Lu4YDpBohZgKjw7 O8Fp2UknCJbdw== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:17 +0530 Subject: [PATCH v2 10/12] Documentation: leds: document pattern behavior of Samsung S2M series PMIC RGB LEDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-10-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add documentation to describe how hardware patterns (as defined by the documentation of led-class-multicolor) are parsed and implemented by the Samsung S2M series PMIC RGB LED driver. Signed-off-by: Kaustabh Chakraborty --- Documentation/leds/index.rst | 1 + Documentation/leds/leds-s2m-rgb.rst | 60 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 61 insertions(+) diff --git a/Documentation/leds/index.rst b/Documentation/leds/index.rst index 76fae171039c6..05d8e8517a807 100644 --- a/Documentation/leds/index.rst +++ b/Documentation/leds/index.rst @@ -27,6 +27,7 @@ LEDs leds-lp55xx leds-mlxcpld leds-mt6370-rgb + leds-s2m-rgb leds-sc27xx leds-st1202 leds-qcom-lpg diff --git a/Documentation/leds/leds-s2m-rgb.rst b/Documentation/leds/leds-= s2m-rgb.rst new file mode 100644 index 0000000000000..4f89a8c89ea86 --- /dev/null +++ b/Documentation/leds/leds-s2m-rgb.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Samsung S2M Series PMIC RGB LED Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Description +----------- + +The RGB LED on the S2M series PMIC hardware features a three-channel LED t= hat +is grouped together as a single device. Furthermore, it supports 8-bit +brightness control for each channel. This LED is typically used as a status +indicator in mobile devices. It also supports various parameters for hardw= are +patterns. + +The hardware pattern can be programmed using the "pattern" trigger, using = the +hw_pattern attribute. + +/sys/class/leds//repeat +---------------------------- + +The hardware supports only indefinitely repeating patterns. The repeat +attribute must be set to -1 for hardware patterns to function. + +/sys/class/leds//hw_pattern +-------------------------------- + +Specify a hardware pattern for the RGB LEDs. + +The pattern is a series of brightness levels and durations in milliseconds. +There should be only one non-zero brightness level. Unlike the results +described in leds-trigger-pattern, the transitions between on and off stat= es +are smoothed out by the hardware. + +Simple pattern:: + + "255 3000 0 1000" + + 255 -+ ''''''-. .-'''''''-. + | '. .' '. + | \ / \ + | '. .' '. + | '-.......-' '- + 0 -+-------+-------+-------+-------+-------+-------+--> time (s) + 0 1 2 3 4 5 6 + +As described in leds-trigger-pattern, it is also possible to use zero-leng= th +entries to disable the ramping mechanism. + +On-Off pattern:: + + "255 1000 255 0 0 1000 0 0" + + 255 -+ ------+ +-------+ +-------+ + | | | | | | + | | | | | | + | | | | | | + | +-------+ +-------+ +------- + 0 -+-------+-------+-------+-------+-------+-------+--> time (s) + 0 1 2 3 4 5 6 --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAFDB8F4A; Sun, 25 Jan 2026 19:08:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368138; cv=none; b=WsJEAsrfI0xGvn7EkJRcYPUfnpjv+M1aZAABH84Fs7fzEtVPWT6B4wnHUJ0vjoNETD7jM+7REKxsFRhtAhJizNXT4CBcYyVkI3COvRfPWB+QlJsH4kR2BIWIEY+hbqptlLuzIFkYVSdZDwu5sTa1FW5J9RwU4vEDFGjurnDLkQg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368138; c=relaxed/simple; bh=d080FNm0u+7ZOHr4ji+ICwSqBO1gkL47TYsLJthwYVM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=il8hBLioUIQkAr4cTqHV8tE/X/M7IxPVEwlIb+tB0rvdWtc+lBSj1xvUmVTNmFFJZ6f/WAtz7NufBAVspvunbZoDgyIaWdgRoRfYXHFLstrRiy4G9yoMhe35RvF5ycBb0L9P5+PhPl4AlOo/Rq6nIWIh5G5MUJbriXAWHvUl9IA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ZC6xOpag; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ZC6xOpag" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 943AC27E78; Sun, 25 Jan 2026 20:08:55 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id LxfTmmAVVvvx; Sun, 25 Jan 2026 20:08:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368134; bh=d080FNm0u+7ZOHr4ji+ICwSqBO1gkL47TYsLJthwYVM=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ZC6xOpagS0HJgdqwiog8f4PyQ/PIe1hjzlgE3+tHbRFv07BW7tSF01U7do0Jk4uoI 4jsElELxnTh7n/YMobvkqTUcAGMp0w2XNjR+YgMPstL/k3bGUjGAD/UCQCY23z4f06 Vi0UAd/L0Si9FlBavIK32M2zsPv7+x66AwneR1xvmKY9Jev2AoJ/UxgVxL/epdlVT2 +A2ntX41u575vIur2LOstPakqW5l1iwJDhxNHTM9jtw0yUxRpJIJJNhQ7oI2Nol90h FPo1cw4skUckKi39o/ELiMug/LIDxEeSZgQkV0MPH1l5Fc/fVT/nXAfl+h6E5tq/Pk vGI1KnIbd3k9g== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:18 +0530 Subject: [PATCH v2 11/12] extcon: add support for Samsung S2M series PMIC extcon devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-11-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add a driver for MUIC devices found in certain Samsung S2M series PMICs These are USB port accessory detectors. These devices report multiple cable states depending on the ID-GND resistance measured by an internal ADC. The driver includes initial support for the S2MU005 PMIC extcon. Signed-off-by: Kaustabh Chakraborty --- drivers/extcon/Kconfig | 10 ++ drivers/extcon/Makefile | 1 + drivers/extcon/extcon-s2m.c | 351 ++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 362 insertions(+) diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index 68d9df7d2dae0..19c712e591955 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -183,6 +183,16 @@ config EXTCON_RT8973A and switch that is optimized to protect low voltage system from abnormal high input voltage (up to 28V). =20 +config EXTCON_S2M + tristate "Samsung S2M series PMIC EXTCON support" + depends on MFD_SEC_CORE + select REGMAP_IRQ + help + This option enables support for MUIC devices found in certain + Samsung S2M series PMICs, such as the S2MU005. These devices + have internal ADCs measuring the ID-GND resistance, thereby + can be used as a USB port accessory detector. + config EXTCON_SM5502 tristate "Silicon Mitus SM5502/SM5504/SM5703 EXTCON support" depends on I2C diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile index 6482f2bfd6611..e3939786f3474 100644 --- a/drivers/extcon/Makefile +++ b/drivers/extcon/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_EXTCON_PALMAS) +=3D extcon-palmas.o obj-$(CONFIG_EXTCON_PTN5150) +=3D extcon-ptn5150.o obj-$(CONFIG_EXTCON_QCOM_SPMI_MISC) +=3D extcon-qcom-spmi-misc.o obj-$(CONFIG_EXTCON_RT8973A) +=3D extcon-rt8973a.o +obj-$(CONFIG_EXTCON_S2M) +=3D extcon-s2m.o obj-$(CONFIG_EXTCON_SM5502) +=3D extcon-sm5502.o obj-$(CONFIG_EXTCON_USB_GPIO) +=3D extcon-usb-gpio.o obj-$(CONFIG_EXTCON_USBC_CROS_EC) +=3D extcon-usbc-cros-ec.o diff --git a/drivers/extcon/extcon-s2m.c b/drivers/extcon/extcon-s2m.c new file mode 100644 index 0000000000000..7a49e8e54f439 --- /dev/null +++ b/drivers/extcon/extcon-s2m.c @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Extcon Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (C) 2025 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct s2m_muic { + struct device *dev; + struct regmap *regmap; + struct extcon_dev *extcon; + struct s2m_muic_irq_data *irq_data; + const unsigned int *extcon_cable; + bool attached; +}; + +struct s2m_muic_irq_data { + const char *name; + int (*const handler)(struct s2m_muic *); + int irq; +}; + +static int s2mu005_muic_detach(struct s2m_muic *priv) +{ + int ret; + int i; + + ret =3D regmap_set_bits(priv->regmap, S2MU005_REG_MUIC_CTRL1, + S2MU005_MUIC_MAN_SW); + if (ret < 0) { + dev_err(priv->dev, "failed to disable manual switching\n"); + return ret; + } + + ret =3D regmap_set_bits(priv->regmap, S2MU005_REG_MUIC_CTRL3, + S2MU005_MUIC_ONESHOT_ADC); + if (ret < 0) { + dev_err(priv->dev, "failed to enable ADC oneshot mode\n"); + return ret; + } + + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_SWCTRL, ~0); + if (ret < 0) { + dev_err(priv->dev, "failed to clear switch control register\n"); + return ret; + } + + /* Find all set states and clear them */ + for (i =3D 0; priv->extcon_cable[i]; i++) { + unsigned int state =3D priv->extcon_cable[i]; + + if (extcon_get_state(priv->extcon, state) =3D=3D true) + extcon_set_state_sync(priv->extcon, state, false); + } + + priv->attached =3D false; + + return 0; +} + +static int s2mu005_muic_attach(struct s2m_muic *priv) +{ + unsigned int type; + int ret; + + /* If any device is already attached, detach it */ + if (priv->attached) { + s2mu005_muic_detach(priv); + msleep(100); + } + + ret =3D regmap_read(priv->regmap, S2MU005_REG_MUIC_DEV1, &type); + if (ret < 0) { + dev_err(priv->dev, "failed to read DEV1 register\n"); + return ret; + } + + /* + * All USB connections which require communication via its D+ + * and D- wires need it. + */ + if (type & (S2MU005_MUIC_OTG | S2MU005_MUIC_DCP | S2MU005_MUIC_SDP)) { + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_MUIC_SWCTRL, + S2MU005_MUIC_DM_DP, + S2MU005_MUIC_DM_DP_USB); + if (ret < 0) { + dev_err(priv->dev, "failed to configure DM/DP pins\n"); + return ret; + } + } + + /* + * For OTG connections, enable manual switching and ADC oneshot + * mode. Since the port will now be supplying power, the + * internal ADC (measuring the ID-GND resistance) is made to + * poll periodically for any changes, so as to prevent any + * damages due to power. + */ + if (type & S2MU005_MUIC_OTG) { + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_CTRL1, + S2MU005_MUIC_MAN_SW); + if (ret < 0) { + dev_err(priv->dev, "failed to enable manual switching\n"); + return ret; + } + + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_CTRL3, + S2MU005_MUIC_ONESHOT_ADC); + if (ret < 0) { + dev_err(priv->dev, "failed to disable ADC oneshot mode\n"); + return ret; + } + } + + switch (type) { + case S2MU005_MUIC_OTG: + dev_dbg(priv->dev, "USB OTG connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB_HOST, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_CDP: + dev_dbg(priv->dev, "USB CDP connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB, true); + extcon_set_state_sync(priv->extcon, EXTCON_CHG_USB_CDP, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_SDP: + dev_dbg(priv->dev, "USB SDP connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB, true); + extcon_set_state_sync(priv->extcon, EXTCON_CHG_USB_SDP, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_DCP: + dev_dbg(priv->dev, "USB DCP connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB, true); + extcon_set_state_sync(priv->extcon, EXTCON_CHG_USB_DCP, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_UART: + dev_dbg(priv->dev, "UART connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_JIG, true); + priv->attached =3D true; + break; + } + + if (!priv->attached) + dev_warn(priv->dev, "failed to recognize the device attached\n"); + + return ret; +} + +static int s2mu005_muic_init(struct s2m_muic *priv) +{ + int ret =3D 0; + + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_MUIC_LDOADC_L, + S2MU005_MUIC_VSET, S2MU005_MUIC_VSET_3P0V); + if (ret < 0) { + dev_err(priv->dev, "failed to set internal ADC voltage regulator\n"); + return ret; + } + + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_MUIC_LDOADC_H, + S2MU005_MUIC_VSET, S2MU005_MUIC_VSET_3P0V); + if (ret < 0) { + dev_err(priv->dev, "failed to set internal ADC voltage regulator\n"); + return ret; + } + + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_CTRL1, + S2MU005_MUIC_IRQ); + if (ret < 0) { + dev_err(priv->dev, "failed to enable MUIC interrupts\n"); + return ret; + } + + return s2mu005_muic_attach(priv); +} + +static const unsigned int s2mu005_muic_extcon_cable[] =3D { + EXTCON_USB, + EXTCON_USB_HOST, + EXTCON_CHG_USB_SDP, + EXTCON_CHG_USB_DCP, + EXTCON_CHG_USB_CDP, + EXTCON_JIG, + EXTCON_NONE, +}; + +static struct s2m_muic_irq_data s2mu005_muic_irq_data[] =3D { + { + .name =3D "attach", + .handler =3D s2mu005_muic_attach + }, { + .name =3D "detach", + .handler =3D s2mu005_muic_detach + }, { + /* sentinel */ + } +}; + +static irqreturn_t s2m_muic_irq_func(int virq, void *data) +{ + struct s2m_muic *priv =3D data; + const struct s2m_muic_irq_data *irq_data =3D priv->irq_data; + int ret; + int i; + + for (i =3D 0; irq_data[i].handler; i++) { + if (virq !=3D irq_data[i].irq) + continue; + + ret =3D irq_data[i].handler(priv); + if (ret < 0) + dev_err(priv->dev, "failed to handle interrupt for %s (%d)\n", + irq_data[i].name, ret); + break; + } + + return IRQ_HANDLED; +} + +static int s2m_muic_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *pmic_drvdata =3D dev_get_drvdata(dev->parent); + struct s2m_muic *priv; + int ret; + int i; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, "failed to allocate driver private\n"= ); + + platform_set_drvdata(pdev, priv); + priv->dev =3D dev; + priv->regmap =3D pmic_drvdata->regmap_pmic; + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + priv->extcon_cable =3D s2mu005_muic_extcon_cable; + priv->irq_data =3D s2mu005_muic_irq_data; + /* Initialize MUIC */ + ret =3D s2mu005_muic_init(priv); + break; + default: + return dev_err_probe(dev, -ENODEV, + "device type %d is not supported by driver\n", + pmic_drvdata->device_type); + } + if (ret < 0) + return dev_err_probe(dev, ret, "failed to initialize MUIC\n"); + + priv->extcon =3D devm_extcon_dev_allocate(&pdev->dev, priv->extcon_cable); + if (IS_ERR(priv->extcon)) + return dev_err_probe(dev, PTR_ERR(priv->extcon), + "failed to allocate memory for extcon\n"); + + ret =3D devm_extcon_dev_register(dev, priv->extcon); + if (ret) + return dev_err_probe(dev, ret, "failed to register extcon device\n"); + + for (i =3D 0; priv->irq_data[i].handler; i++) { + int irq =3D platform_get_irq_byname_optional(pdev, + priv->irq_data[i].name); + if (irq =3D=3D -ENXIO) + continue; + if (irq <=3D 0) + return dev_err_probe(dev, -EINVAL, "failed to get IRQ %s\n", + priv->irq_data[i].name); + + priv->irq_data[i].irq =3D irq; + ret =3D devm_request_threaded_irq(dev, irq, NULL, + s2m_muic_irq_func, IRQF_ONESHOT, + priv->irq_data[i].name, priv); + if (ret) + return dev_err_probe(dev, ret, "failed to request IRQ\n"); + } + + return 0; +} + +static void s2m_muic_remove(struct platform_device *pdev) +{ + struct s2m_muic *priv =3D dev_get_drvdata(&pdev->dev); + + /* + * Disabling the MUIC device is important as it disables manual + * switching mode, thereby enabling auto switching mode. + * + * This is to ensure that when the board is powered off, it + * goes into LPM charging mode when a USB charger is connected. + */ + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + s2mu005_muic_detach(priv); + break; + } +} + +static const struct platform_device_id s2m_muic_id_table[] =3D { + { "s2mu005-muic", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_muic_id_table); + +#ifdef CONFIG_OF +/* + * Device is instantiated through parent MFD device and device matching + * is done through platform_device_id. + * + * However if device's DT node contains proper compatible and driver is + * built as a module, then the *module* matching will be done through DT + * aliases. This requires of_device_id table. In the same time this will + * not change the actual *device* matching so do not add .of_match_table. + */ +static const struct of_device_id s2m_muic_of_match_table[] =3D { + { + .compatible =3D "samsung,s2mu005-muic", + .data =3D (void *)S2MU005, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, s2m_muic_of_match_table); +#endif + +static struct platform_driver s2m_muic_driver =3D { + .driver =3D { + .name =3D "s2m-muic", + }, + .probe =3D s2m_muic_probe, + .remove =3D s2m_muic_remove, + .id_table =3D s2m_muic_id_table, +}; +module_platform_driver(s2m_muic_driver); + +MODULE_DESCRIPTION("Extcon Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Sun Feb 8 13:48:17 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 333282F2604; Sun, 25 Jan 2026 19:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368144; cv=none; b=Otj6TVbvXQsRDiVCgWr9a0uw8UOGq5qpd1g+MOuB4UXU4CL2WC46JDy6zVep2h7Pwg9ZpJAX+yDlV194HfCGdxeZ+ECUG0RBc0pidiKXpr/3HuekZjnSWaJDU01U1axS27xjBu3ob1o6BwKrl7IkxV+GtELApM1lycGIm6FNIgg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769368144; c=relaxed/simple; bh=zC/3rnQyt3mAnYw4WziZKdbnacGpu6rOWazsrIUSjWc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=peMXRoduiiTYx5WB6X+w1tb1O1CwgOI2JBV7ttArHJdsTLP48fvRTPV0VGt+fkxEnlTI99UzkUiaZABFGbtiFKdm0Uc9tbzaJ2fJacdOm5zFg0KpWTqFaAq4yTl64b/RlCa20pa2xEEBZh8QlGwO6zkNZ0UAvjwx51u9QAvStVg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=SDuFiYaf; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="SDuFiYaf" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id ED62527D96; Sun, 25 Jan 2026 20:09:01 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 1tjh9D-EX7Wv; Sun, 25 Jan 2026 20:09:00 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1769368140; bh=zC/3rnQyt3mAnYw4WziZKdbnacGpu6rOWazsrIUSjWc=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=SDuFiYafpuryiQ5OYSeCkb5HVjaV3gpAE9JVGCtMh9fNEuLv0RcSWk5ikB24xqMef oE5Oe9Ne+V9dJWN3aymgTacoaU+C5kpjubn2LWi6his1GL+0fkNyS/kzRkJLxyMQ4j o211vuyxap48K1d3pfnB8v9ttWwQDtU37/S6eWOXEsrdnnofylwoCFaKwOADR4AoSV mii1WwIjSGNtBNp+Atx5c5P9TZDubDUFSqMq3ptWQK7wH6azuERQVb92iDz1cJg/VK lWKSD/PAoCXyin56BS45DVbb6C65M0kCM0YLl1XQa6V1USwl2oTnIoqPQT1XRdl78u OjgywB/MUPZlw== From: Kaustabh Chakraborty Date: Mon, 26 Jan 2026 00:37:19 +0530 Subject: [PATCH v2 12/12] power: supply: add support for Samsung S2M series PMIC charger device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260126-s2mu005-pmic-v2-12-78f1a75f547a@disroot.org> References: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> In-Reply-To: <20260126-s2mu005-pmic-v2-0-78f1a75f547a@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add a driver for charger controllers found in certain Samsung S2M series PMICs. The driver has very basic support for the device, with only charger online reporting working. The driver includes initial support for the S2MU005 PMIC charger. Signed-off-by: Kaustabh Chakraborty --- drivers/power/supply/Kconfig | 11 ++ drivers/power/supply/Makefile | 1 + drivers/power/supply/s2m-charger.c | 213 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 225 insertions(+) diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 92f9f7aae92f2..b9a6bdf014586 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -229,6 +229,17 @@ config BATTERY_SAMSUNG_SDI Say Y to enable support for Samsung SDI battery data. These batteries are used in Samsung mobile phones. =20 +config CHARGER_S2M + tristate "Samsung S2M series PMIC battery charger support" + depends on EXTCON_S2M + depends on MFD_SEC_CORE + select REGMAP_IRQ + help + This option enables support for charger devices found in + certain Samsung S2M series PMICs, such as the S2MU005. These + devices provide USB power supply information and also required + for USB OTG role switching. + config BATTERY_COLLIE tristate "Sharp SL-5500 (collie) battery" depends on SA1100_COLLIE && MCP_UCB1200 diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile index 4b79d5abc49a7..795ef40d95311 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_BATTERY_PMU) +=3D pmu_battery.o obj-$(CONFIG_BATTERY_QCOM_BATTMGR) +=3D qcom_battmgr.o obj-$(CONFIG_BATTERY_OLPC) +=3D olpc_battery.o obj-$(CONFIG_BATTERY_SAMSUNG_SDI) +=3D samsung-sdi-battery.o +obj-$(CONFIG_CHARGER_S2M) +=3D s2m-charger.o obj-$(CONFIG_BATTERY_COLLIE) +=3D collie_battery.o obj-$(CONFIG_BATTERY_INGENIC) +=3D ingenic-battery.o obj-$(CONFIG_BATTERY_INTEL_DC_TI) +=3D intel_dc_ti_battery.o diff --git a/drivers/power/supply/s2m-charger.c b/drivers/power/supply/s2m-= charger.c new file mode 100644 index 0000000000000..c212bc59f93cc --- /dev/null +++ b/drivers/power/supply/s2m-charger.c @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Battery Charger Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2025 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct s2m_chgr { + struct device *dev; + struct regmap *regmap; + struct power_supply *psy; + struct extcon_dev *extcon; + struct work_struct extcon_work; + struct notifier_block extcon_nb; +}; + +static int s2mu005_chgr_get_online(struct s2m_chgr *priv, int *value) +{ + u32 val; + int ret =3D 0; + + ret =3D regmap_read(priv->regmap, S2MU005_REG_CHGR_STATUS0, &val); + if (ret < 0) { + dev_err(priv->dev, "failed to read register (%d)\n", ret); + return ret; + } + + *value =3D !!(val & S2MU005_CHGR_CHG); + + return ret; +} + +static int s2mu005_chgr_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct s2m_chgr *priv =3D power_supply_get_drvdata(psy); + int ret =3D 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + ret =3D s2mu005_chgr_get_online(priv, &val->intval); + break; + default: + return -EINVAL; + } + + return ret; +} + +static void s2mu005_chgr_extcon_work(struct work_struct *work) +{ + struct s2m_chgr *priv =3D container_of(work, struct s2m_chgr, + extcon_work); + int ret; + + if (extcon_get_state(priv->extcon, EXTCON_USB_HOST) =3D=3D true) { + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL0, + S2MU005_CHGR_OP_MODE, + S2MU005_CHGR_OP_MODE_OTG); + if (ret < 0) + dev_err(priv->dev, "failed to set operation mode to OTG (%d)\n", + ret); + + goto psy_update; + } + + if (extcon_get_state(priv->extcon, EXTCON_USB) =3D=3D true) { + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL0, + S2MU005_CHGR_OP_MODE, + S2MU005_CHGR_OP_MODE_CHG); + if (ret < 0) + dev_err(priv->dev, "failed to set operation mode to charging (%d)\n", + ret); + + goto psy_update; + } + + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_CHGR_CTRL0, + S2MU005_CHGR_OP_MODE); + if (ret < 0) + dev_err(priv->dev, "failed to clear operation mode (%d)\n", ret); + +psy_update: + power_supply_changed(priv->psy); +} + +static const enum power_supply_property s2mu005_chgr_properties[] =3D { + POWER_SUPPLY_PROP_ONLINE, +}; + +static const struct power_supply_desc s2mu005_chgr_psy_desc =3D { + .name =3D "s2mu005-charger", + .type =3D POWER_SUPPLY_TYPE_USB, + .properties =3D s2mu005_chgr_properties, + .num_properties =3D ARRAY_SIZE(s2mu005_chgr_properties), + .get_property =3D s2mu005_chgr_get_property, +}; + +static int s2m_chgr_extcon_notifier(struct notifier_block *nb, + unsigned long event, void *param) +{ + struct s2m_chgr *priv =3D container_of(nb, struct s2m_chgr, extcon_nb); + + schedule_work(&priv->extcon_work); + + return NOTIFY_OK; +} + +static int s2m_chgr_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *pmic_drvdata =3D dev_get_drvdata(dev->parent); + struct s2m_chgr *priv; + struct device_node *extcon_node; + struct power_supply_config psy_cfg =3D {}; + const struct power_supply_desc *psy_desc; + work_func_t extcon_work_func; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, "failed to allocate driver private\n"= ); + + platform_set_drvdata(pdev, priv); + priv->dev =3D dev; + priv->regmap =3D pmic_drvdata->regmap_pmic; + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + psy_desc =3D &s2mu005_chgr_psy_desc; + extcon_work_func =3D s2mu005_chgr_extcon_work; + break; + default: + return dev_err_probe(dev, -ENODEV, + "device type %d is not supported by driver\n", + pmic_drvdata->device_type); + } + + psy_cfg.drv_data =3D priv; + priv->psy =3D devm_power_supply_register(dev, psy_desc, &psy_cfg); + if (IS_ERR(priv->psy)) + return dev_err_probe(dev, PTR_ERR(priv->psy), + "failed to register power supply subsystem\n"); + + /* MUIC is mandatory. If unavailable, request probe deferral */ + extcon_node =3D of_get_child_by_name(dev->parent->of_node, "extcon"); + priv->extcon =3D extcon_find_edev_by_node(extcon_node); + if (IS_ERR(priv->extcon)) + return -EPROBE_DEFER; + + ret =3D devm_work_autocancel(dev, &priv->extcon_work, extcon_work_func); + if (ret) + return dev_err_probe(dev, ret, "failed to initialize extcon work\n"); + + priv->extcon_nb.notifier_call =3D s2m_chgr_extcon_notifier; + ret =3D devm_extcon_register_notifier_all(dev, priv->extcon, &priv->extco= n_nb); + if (ret) + dev_err_probe(dev, ret, "failed to register extcon notifier\n"); + + return 0; +} + +static const struct platform_device_id s2m_chgr_id_table[] =3D { + { "s2mu005-charger", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_chgr_id_table); + +#ifdef CONFIG_OF +/* + * Device is instantiated through parent MFD device and device matching + * is done through platform_device_id. + * + * However if device's DT node contains proper compatible and driver is + * built as a module, then the *module* matching will be done through DT + * aliases. This requires of_device_id table. In the same time this will + * not change the actual *device* matching so do not add .of_match_table. + */ +static const struct of_device_id s2m_chgr_of_match_table[] =3D { + { + .compatible =3D "samsung,s2mu005-charger", + .data =3D (void *)S2MU005, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, s2m_chgr_of_match_table); +#endif + +static struct platform_driver s2m_chgr_driver =3D { + .driver =3D { + .name =3D "s2m-charger", + }, + .probe =3D s2m_chgr_probe, + .id_table =3D s2m_chgr_id_table, +}; +module_platform_driver(s2m_chgr_driver); + +MODULE_DESCRIPTION("Battery Charger Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_LICENSE("GPL"); --=20 2.52.0