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Sun, 25 Jan 2026 05:13:42 -0800 (PST) From: Svyatoslav Ryhel To: Thierry Reding , Mikko Perttunen , David Airlie , Simona Vetter , Jonathan Hunter , Diogo Ivo , Svyatoslav Ryhel Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30 Date: Sun, 25 Jan 2026 15:13:22 +0200 Message-ID: <20260125131323.45108-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125131323.45108-1-clamor95@gmail.com> References: <20260125131323.45108-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra20 and Tegra30 are fully compatible with existing Tegra DSI driver apart from clock configuration and pad calibration which are addressed by this patch. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/gpu/drm/tegra/drm.c | 2 + drivers/gpu/drm/tegra/dsi.c | 107 +++++++++++++++++++++++++----------- drivers/gpu/drm/tegra/dsi.h | 10 ++++ 3 files changed, 88 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 4596073fe28f..5d64cd57e764 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_= drm_suspend, =20 static const struct of_device_id host1x_drm_subdevs[] =3D { { .compatible =3D "nvidia,tegra20-dc", }, + { .compatible =3D "nvidia,tegra20-dsi", }, { .compatible =3D "nvidia,tegra20-hdmi", }, { .compatible =3D "nvidia,tegra20-gr2d", }, { .compatible =3D "nvidia,tegra20-gr3d", }, { .compatible =3D "nvidia,tegra30-dc", }, + { .compatible =3D "nvidia,tegra30-dsi", }, { .compatible =3D "nvidia,tegra30-hdmi", }, { .compatible =3D "nvidia,tegra30-gr2d", }, { .compatible =3D "nvidia,tegra30-gr3d", }, diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 02a661d86751..ebc78dceaee6 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -53,6 +53,11 @@ to_dsi_state(struct drm_connector_state *state) return container_of(state, struct tegra_dsi_state, base); } =20 +struct tegra_dsi_config { + bool has_multiple_pad_controls; + bool has_mux_parent_clk; +}; + struct tegra_dsi { struct host1x_client client; struct tegra_output output; @@ -82,6 +87,8 @@ struct tegra_dsi { /* for ganged-mode support */ struct tegra_dsi *master; struct tegra_dsi *slave; + + const struct tegra_dsi_config *config; }; =20 static inline struct tegra_dsi * @@ -663,39 +670,46 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) { u32 value; =20 - value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + if (dsi->config->has_multiple_pad_controls) { + /* + * XXX Is this still needed? The module reset is deasserted right + * before this function is called. + */ + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); + + value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + + value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | + DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | + DSI_PAD_OUT_CLK(0x0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); + + value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | + DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); + } else { + value =3D DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) | + DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) | + DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) | + DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + } =20 return 0; } =20 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) { - u32 value; int err; =20 - /* - * XXX Is this still needed? The module reset is deasserted right - * before this function is called. - */ - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); - /* start calibration */ tegra_dsi_pad_enable(dsi); =20 - value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | - DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | - DSI_PAD_OUT_CLK(0x0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); - - value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | - DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - err =3D tegra_mipi_start_calibration(dsi->mipi); if (err < 0) return err; @@ -1568,6 +1582,7 @@ static int tegra_dsi_probe(struct platform_device *pd= ev) if (!dsi) return -ENOMEM; =20 + dsi->config =3D of_device_get_match_data(&pdev->dev); dsi->output.dev =3D dsi->dev =3D &pdev->dev; dsi->video_fifo_depth =3D 1920; dsi->host_fifo_depth =3D 64; @@ -1606,7 +1621,7 @@ static int tegra_dsi_probe(struct platform_device *pd= ev) goto remove; } =20 - dsi->clk_lp =3D devm_clk_get(&pdev->dev, "lp"); + dsi->clk_lp =3D devm_clk_get_optional(&pdev->dev, "lp"); if (IS_ERR(dsi->clk_lp)) { err =3D dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), "cannot get low-power clock\n"); @@ -1627,10 +1642,12 @@ static int tegra_dsi_probe(struct platform_device *= pdev) goto remove; } =20 - err =3D tegra_dsi_setup_clocks(dsi); - if (err < 0) { - dev_err(&pdev->dev, "cannot setup clocks\n"); - goto remove; + if (dsi->config->has_mux_parent_clk) { + err =3D tegra_dsi_setup_clocks(dsi); + if (err < 0) { + dev_err(&pdev->dev, "cannot setup clocks\n"); + goto remove; + } } =20 dsi->regs =3D devm_platform_ioremap_resource(pdev, 0); @@ -1694,11 +1711,39 @@ static void tegra_dsi_remove(struct platform_device= *pdev) tegra_mipi_free(dsi->mipi); } =20 +static const struct tegra_dsi_config tegra20_dsi_config =3D { + .has_multiple_pad_controls =3D false, + .has_mux_parent_clk =3D false, +}; + +/* + * Tegra30 allows DSIA/DSIB to be muxed to either PLL_D or PLL_D2; this is + * simply not modeled in the clock driver yet. If this functionality is + * required, the has_mux_parent_clk flag can be set to true once the clock + * driver is patched. + */ +static const struct tegra_dsi_config tegra30_dsi_config =3D { + .has_multiple_pad_controls =3D false, + .has_mux_parent_clk =3D false, +}; + +static const struct tegra_dsi_config tegra114_dsi_config =3D { + .has_multiple_pad_controls =3D true, + .has_mux_parent_clk =3D true, +}; + +static const struct tegra_dsi_config tegra124_dsi_config =3D { + .has_multiple_pad_controls =3D true, + .has_mux_parent_clk =3D false, +}; + static const struct of_device_id tegra_dsi_of_match[] =3D { - { .compatible =3D "nvidia,tegra210-dsi", }, - { .compatible =3D "nvidia,tegra132-dsi", }, - { .compatible =3D "nvidia,tegra124-dsi", }, - { .compatible =3D "nvidia,tegra114-dsi", }, + { .compatible =3D "nvidia,tegra210-dsi", .data =3D &tegra124_dsi_config }, + { .compatible =3D "nvidia,tegra132-dsi", .data =3D &tegra124_dsi_config }, + { .compatible =3D "nvidia,tegra124-dsi", .data =3D &tegra124_dsi_config }, + { .compatible =3D "nvidia,tegra114-dsi", .data =3D &tegra114_dsi_config }, + { .compatible =3D "nvidia,tegra30-dsi", .data =3D &tegra30_dsi_config }, + { .compatible =3D "nvidia,tegra20-dsi", .data =3D &tegra20_dsi_config }, { }, }; MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h index f39594e65e97..d834ac0c47ab 100644 --- a/drivers/gpu/drm/tegra/dsi.h +++ b/drivers/gpu/drm/tegra/dsi.h @@ -95,6 +95,16 @@ #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) #define DSI_PAD_CONTROL_0 0x4b +/* Tegra20/Tegra30 */ +#define DSI_PAD_CONTROL_PULLDN_ENAB(x) (((x) & 0x1) << 28) +#define DSI_PAD_CONTROL_SLEWUPADJ(x) (((x) & 0x7) << 24) +#define DSI_PAD_CONTROL_SLEWDNADJ(x) (((x) & 0x7) << 20) +#define DSI_PAD_CONTROL_PREEMP_EN(x) (((x) & 0x1) << 19) +#define DSI_PAD_CONTROL_PDIO_CLK(x) (((x) & 0x1) << 18) +#define DSI_PAD_CONTROL_PDIO(x) (((x) & 0x3) << 16) +#define DSI_PAD_CONTROL_LPUPADJ(x) (((x) & 0x3) << 14) +#define DSI_PAD_CONTROL_LPDNADJ(x) (((x) & 0x3) << 12) +/* Tegra114+ */ #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) --=20 2.51.0 From nobody Sun Feb 8 10:04:45 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52BA0318EFC for ; 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Sun, 25 Jan 2026 05:13:43 -0800 (PST) Received: from xeon ([188.163.112.49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435b1c24a8asm21958244f8f.12.2026.01.25.05.13.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 05:13:43 -0800 (PST) From: Svyatoslav Ryhel To: Thierry Reding , Mikko Perttunen , David Airlie , Simona Vetter , Jonathan Hunter , Diogo Ivo , Svyatoslav Ryhel Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] gpu/drm: tegra: dsi: re-add clear enable register if DSI was powered by bootloader Date: Sun, 25 Jan 2026 15:13:23 +0200 Message-ID: <20260125131323.45108-3-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125131323.45108-1-clamor95@gmail.com> References: <20260125131323.45108-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Original commit b22fd0b9639e ("drm/tegra: dsi: Clear enable register if powered by bootloader") was added to address the issue of DSI being in an unknown state after the bootloader, ensuring correct panel configuration. This worked fairly well under the assumption that the bootloader had set up DSI; however, in cases where it did not, the device would hang because a DSI read was called before the DSI hardware was ready. Removing this workaround results in the issue described in the original fix: the panel initialization sequence fails and the panel gets stuck in an undefined state. This is especially noticeable with command mode panels In order to properly address this issue, the original workaround is restored and placed after the DSI hardware is prepared for R/W operations. This fixes behavior for both cases: where DSI is set by the bootloader and where DSI is untouched. I have tested this change on Tegra20 (Motorola Atrix 4G), Tegra114 (NVIDIA Tegra Note 7 and ASUS Transformer Pad TF701T), and Tegra124 (Xiaomi Mi Pad) with U-Boot, using both bootloader-initialized DSI and untouched DSI. Fixes: b22fd0b9639e ("drm/tegra: dsi: Clear enable register if powered by b= ootloader") Fixes: 660b299bed2a ("Revert "drm/tegra: dsi: Clear enable register if powe= red by bootloader"") Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/gpu/drm/tegra/dsi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index ebc78dceaee6..e499822b6030 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -934,6 +934,15 @@ static void tegra_dsi_encoder_enable(struct drm_encode= r *encoder) return; } =20 + /* If the bootloader enabled DSI it needs to be disabled + * in order for the panel initialization commands to be + * properly sent. + */ + value =3D tegra_dsi_readl(dsi, DSI_POWER_CONTROL); + + if (value & DSI_POWER_CONTROL_ENABLE) + tegra_dsi_disable(dsi); + state =3D tegra_dsi_get_state(dsi); =20 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); --=20 2.51.0