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Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 5/7] x86/microcode: Use stop-machine NMI facility Date: Sun, 25 Jan 2026 01:42:20 +0000 Message-ID: <20260125014224.249901-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The existing NMI-based loading logic explicitly sends NMIs to online CPUs and invokes microcode_update_handler() from the NMI context. The stop-machine NMI variant already provides the mechanism on x86. Replace the custom NMI-based mechanism with the common facility to simplify the loader code. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/microcode.h | 1 - arch/x86/kernel/cpu/microcode/core.c | 19 +++---------------- arch/x86/kernel/nmi.c | 3 --- 3 files changed, 3 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 8b41f26f003b..946b0cebed87 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -77,7 +77,6 @@ static inline u32 intel_get_microcode_revision(void) } #endif /* !CONFIG_CPU_SUP_INTEL */ =20 -bool microcode_nmi_handler(void); void microcode_offline_nmi_handler(void); =20 #ifdef CONFIG_MICROCODE_LATE_LOADING diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 28317176ae29..0facadea39d6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -555,22 +555,9 @@ static noinstr int microcode_update_handler(void *unus= ed) * path which must be NMI safe until the primary thread completed the * update. */ -bool noinstr microcode_nmi_handler(void) +static noinstr int microcode_nmi_handler(void *data) { - if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) - return false; - - raw_cpu_write(ucode_ctrl.nmi_enabled, false); - return microcode_update_handler(NULL) =3D=3D 0; -} - -static int load_cpus_stopped(void *unused) -{ - /* Enable the NMI handler and raise NMI */ - this_cpu_write(ucode_ctrl.nmi_enabled, true); - apic->send_IPI(smp_processor_id(), NMI_VECTOR); - - return 0; + return microcode_update_handler(data); } =20 static int load_late_stop_cpus(bool is_safe) @@ -608,7 +595,7 @@ static int load_late_stop_cpus(bool is_safe) =20 if (microcode_ops->use_nmi) { static_branch_enable_cpuslocked(µcode_nmi_handler_enable); - stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); + stop_machine_cpuslocked_nmi(microcode_nmi_handler, NULL, cpu_online_mask= ); static_branch_disable_cpuslocked(µcode_nmi_handler_enable); } else { stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 4bc4b49f1ea7..642469f3be80 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -386,9 +386,6 @@ static noinstr void default_do_nmi(struct pt_regs *regs) if (stop_machine_nmi_handler_enabled() && stop_machine_nmi_handler()) goto out; =20 - if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) - goto out; - /* * CPU-specific NMI must be processed before non-CPU-specific * NMI, otherwise we may lose it, because the CPU-specific --=20 2.51.0