From nobody Mon Feb 9 19:26:45 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 584DD1DEFE9 for ; Sun, 25 Jan 2026 02:06:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306781; cv=none; b=mAs/StiAwNcZr179tSHfwlG8SVOGL7QlZ8iIV0aKv/MblgRJ3BrSKyukA7JCTBjEcqIFqEhUGQb0XZbG4dEHi/YHOgU314Oesrs2vaP3Lo2L8Nx0J/THjz+0hDgoe71dVd9CP99RNB6BnhIERVTrMAEvcdAkU/KiG0sAfzGZ+qE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306781; c=relaxed/simple; bh=DOYTho/fiyxXqBBrzu0t5y3ClyEjIV5R9tG6NVHJtAk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uBz8PwOqlK1j5eIrrl3KyxvFzSyZ667rzHEVsmMbZs9oVZDQY1NglfBIYR1qwh/SnqVH1tSaBkk6d/GETYxR198jGuKe2wL6PUQuTOa4XeGfzlBM14Sf9HYegfl6ppAOc6q+BK2y7wfhI/zEkGG7kUCTlsZuav8j4UD2E9hzOCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JrIS0nMb; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JrIS0nMb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769306780; x=1800842780; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DOYTho/fiyxXqBBrzu0t5y3ClyEjIV5R9tG6NVHJtAk=; b=JrIS0nMbaeJwv2FY9OeQ4LaVi3+pba8zN5PUp6G3ESrsMCo96P1r2yhL R4qQ9MJumWiAW5GUNL4whqbidQ8oayu0rwjUSWkKvNnc4CiMI9KBvOJ5i XEUtnKfV0husNRc6bwvSX9rTcqkN7JOyi+zCNMyWxtQ3kVHFv5UHMh95D 75p6wkMvi+mpmkloiKEsmNRqc0Aq3rQ/LKnEmFy0tlUh207BuZhtD4e60 TaXIZehBfKJ2JlJEC6K+/YcSlNBUrR1WH8hnKfBbvfbbSjVCRZ/y9jYLl sZvHspKe5kSOqlySk66NRgKwNc2MbwGtR2Yzzw4lP30081uKl81qJ9j28 w==; X-CSE-ConnectionGUID: +YpNnqsNSrWhFbIEx29zKg== X-CSE-MsgGUID: 1Q1wyuDYQ2a3XG7s1KLq6Q== X-IronPort-AV: E=McAfee;i="6800,10657,11681"; a="73101888" X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="73101888" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2026 18:06:19 -0800 X-CSE-ConnectionGUID: nk4be7U7S5qSVPdXBcjtOw== X-CSE-MsgGUID: KRXJLrZnRFKC0x9hhICkgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="207783102" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:19 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 4/7] x86/microcode: Distinguish NMI control path on stop-machine callback Date: Sun, 25 Jan 2026 01:42:19 +0000 Message-ID: <20260125014224.249901-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" load_cpus_stopped() currently centralizes the stop_machine() callback for both NMI and NMI-less rendezvous. microcode_update_handler() alone is enough for the latter. While the NMI-based rendezvous finally reaches the same update handler, it requires additional logic to trigger and process NMIs. That machinery will be replaced by stop_machine_nmi(). As preparation for that conversion, split the callback path to make NMI-specific steps explicit and clear. Signed-off-by: Chang S. Bae --- arch/x86/kernel/cpu/microcode/core.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 68049f171860..28317176ae29 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -524,7 +524,7 @@ void noinstr microcode_offline_nmi_handler(void) wait_for_ctrl(); } =20 -static noinstr bool microcode_update_handler(void) +static noinstr int microcode_update_handler(void *unused) { unsigned int cpu =3D raw_smp_processor_id(); =20 @@ -540,7 +540,7 @@ static noinstr bool microcode_update_handler(void) touch_nmi_watchdog(); instrumentation_end(); =20 - return true; + return 0; } =20 /* @@ -561,19 +561,15 @@ bool noinstr microcode_nmi_handler(void) return false; =20 raw_cpu_write(ucode_ctrl.nmi_enabled, false); - return microcode_update_handler(); + return microcode_update_handler(NULL) =3D=3D 0; } =20 static int load_cpus_stopped(void *unused) { - if (microcode_ops->use_nmi) { - /* Enable the NMI handler and raise NMI */ - this_cpu_write(ucode_ctrl.nmi_enabled, true); - apic->send_IPI(smp_processor_id(), NMI_VECTOR); - } else { - /* Just invoke the handler directly */ - microcode_update_handler(); - } + /* Enable the NMI handler and raise NMI */ + this_cpu_write(ucode_ctrl.nmi_enabled, true); + apic->send_IPI(smp_processor_id(), NMI_VECTOR); + return 0; } =20 @@ -610,13 +606,13 @@ static int load_late_stop_cpus(bool is_safe) */ store_cpu_caps(&prev_info); =20 - if (microcode_ops->use_nmi) + if (microcode_ops->use_nmi) { static_branch_enable_cpuslocked(µcode_nmi_handler_enable); - - stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); - - if (microcode_ops->use_nmi) + stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); static_branch_disable_cpuslocked(µcode_nmi_handler_enable); + } else { + stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); + } =20 /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { --=20 2.51.0