From nobody Sat Feb 7 11:38:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29BD88632A for ; Sun, 25 Jan 2026 02:06:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306780; cv=none; b=pff6x5SgnMeRnesb2ii3kWLkOAEJUwiYkLI8eGz6c3ojU0kRvAET3KbnuxG9cLm/HDp9+u0jalsMQo90/SolG8C/Pmt0f+YBFQRbvu7qYS7EheNtnYhFYfV8G3xsBjGa8HDliYN3SLHDmp8SzSTUOVY3vk3ioWrcT3Y51Qox+7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306780; c=relaxed/simple; bh=0UC9Eps27DXtof1R8R7WQbTW4+Vxgn3aQ8gRfuTQD4k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KhanrPabYOktCgoIgfXfZovLkDmF8jxJkbRlRjtC5Ljimc3DNn7J31VKt0Wsc6DOHij/alaRiiouGkv5kRDqNG+MknBuh+/AQ34vxc5a20wyDKEbN6fI7ghCm301HQOPkt+zs2FACjXtDakVwtiFIoa/5IPg5jHbRcmdjaJ2mPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TSZbdjMD; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TSZbdjMD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769306778; x=1800842778; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0UC9Eps27DXtof1R8R7WQbTW4+Vxgn3aQ8gRfuTQD4k=; b=TSZbdjMDaH1Q8KrKjsn9KZqQXIXDWOzq3wq/H4keQgqEA8U+03Y4KyT8 ifjFnZiiwsa39DTveG+SimqKMePfCWpP+PYKnzh6avcAj5WRUyTMBKzzF T6mdGjkIK/Tv/QeQ9jR5UJAM9wLQTRqjArWo+2UJQRtn8yl5iwNXNEkaM DGKI4sS1hSlFTGo1kqPvMLIaN5mPK8bpmQAEbZrdAXlRc3L5d6ILZtPYQ KanSN5L8xsfcwSV20YZxkNxx9gASMw4k6fTWhOKTz8YrtU7NbHSj8kwq2 3DDi0PCHCJWykXHB12re2wlLK4JhSMotPlysZ2AopmNs4ieHpj6xxg0qn w==; X-CSE-ConnectionGUID: DOTthduoSWCIhlYa7i6xIQ== X-CSE-MsgGUID: BT1prIj3Qiq9ypxJAmlvdQ== X-IronPort-AV: E=McAfee;i="6800,10657,11681"; a="73101867" X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="73101867" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2026 18:06:16 -0800 X-CSE-ConnectionGUID: Zl6ts9Z9RMGwG2OubbICaA== X-CSE-MsgGUID: nsikDiucTdaTZ1FqsK/t/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="207783093" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:16 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 1/7] stop_machine: Introduce stop_machine_nmi() Date: Sun, 25 Jan 2026 01:42:16 +0000 Message-ID: <20260125014224.249901-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: David Kaplan stop_machine_nmi() is a variant of stop_machine() that runs the specified function in NMI context. This is useful for flows that cannot tolerate any risk of interruption even due to an NMI. Arch-specific code must handle sending the actual NMI and running the stop_machine_nmi_handler(). Signed-off-by: David Kaplan Signed-off-by: Chang S. Bae --- Update from the original version: * Move static key handling into stop_machine_cpuslocked_nmi() to support core-code users that already hold cpu hotplug locks * Tweak the subject to better reflect the new interface and changelog a bit as well --- include/linux/stop_machine.h | 50 +++++++++++++++++++++ kernel/stop_machine.c | 84 ++++++++++++++++++++++++++++++++++-- 2 files changed, 130 insertions(+), 4 deletions(-) diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h index 72820503514c..86113084456a 100644 --- a/include/linux/stop_machine.h +++ b/include/linux/stop_machine.h @@ -141,6 +141,29 @@ int stop_machine(cpu_stop_fn_t fn, void *data, const s= truct cpumask *cpus); */ int stop_machine_cpuslocked(cpu_stop_fn_t fn, void *data, const struct cpu= mask *cpus); =20 +/** + * stop_machine_nmi: freeze the machine and run this function in NMI conte= xt + * @fn: the function to run + * @data: the data ptr for the @fn() + * @cpus: the cpus to run the @fn() on (NULL =3D any online cpu) + * + * Like stop_machine() but runs the function in NMI context to avoid any r= isk of + * interruption due to NMIs. + * + * Protects against CPU hotplug. + */ +int stop_machine_nmi(cpu_stop_fn_t fn, void *data, const struct cpumask *c= pus); + +/** + * stop_machine_cpuslocked_nmi: freeze and run this function in NMI context + * @fn: the function to run + * @data: the data ptr for the @fn() + * @cpus: the cpus to run the @fn() on (NULL =3D any online cpu) + * + * Same as above. Must be called from within a cpus_read_lock() protected + * region. Avoids nested calls to cpus_read_lock(). + */ +int stop_machine_cpuslocked_nmi(cpu_stop_fn_t fn, void *data, const struct= cpumask *cpus); /** * stop_core_cpuslocked: - stop all threads on just one core * @cpu: any cpu in the targeted core @@ -160,6 +183,14 @@ int stop_core_cpuslocked(unsigned int cpu, cpu_stop_fn= _t fn, void *data); =20 int stop_machine_from_inactive_cpu(cpu_stop_fn_t fn, void *data, const struct cpumask *cpus); + +bool noinstr stop_machine_nmi_handler(void); +DECLARE_STATIC_KEY_FALSE(stop_machine_nmi_handler_enable); +static __always_inline bool stop_machine_nmi_handler_enabled(void) +{ + return static_branch_unlikely(&stop_machine_nmi_handler_enable); +} + #else /* CONFIG_SMP || CONFIG_HOTPLUG_CPU */ =20 static __always_inline int stop_machine_cpuslocked(cpu_stop_fn_t fn, void = *data, @@ -186,5 +217,24 @@ stop_machine_from_inactive_cpu(cpu_stop_fn_t fn, void = *data, return stop_machine(fn, data, cpus); } =20 +/* stop_machine_nmi() is only supported in SMP systems. */ +static __always_inline int stop_machine_nmi(cpu_stop_fn_t fn, void *data, + const struct cpumask *cpus) +{ + return -EINVAL; +} + +static __always_inline bool stop_machine_nmi_handler_enabled(void) +{ + return false; +} + +static __always_inline bool stop_machine_nmi_handler(void) +{ + return false; +} + #endif /* CONFIG_SMP || CONFIG_HOTPLUG_CPU */ + +void arch_send_self_nmi(void); #endif /* _LINUX_STOP_MACHINE */ diff --git a/kernel/stop_machine.c b/kernel/stop_machine.c index 3fe6b0c99f3d..189b4b108d13 100644 --- a/kernel/stop_machine.c +++ b/kernel/stop_machine.c @@ -174,6 +174,8 @@ struct multi_stop_data { =20 enum multi_stop_state state; atomic_t thread_ack; + + bool use_nmi; }; =20 static void set_state(struct multi_stop_data *msdata, @@ -197,6 +199,42 @@ notrace void __weak stop_machine_yield(const struct cp= umask *cpumask) cpu_relax(); } =20 +struct stop_machine_nmi_ctrl { + bool nmi_enabled; + struct multi_stop_data *msdata; + int err; +}; + +DEFINE_STATIC_KEY_FALSE(stop_machine_nmi_handler_enable); +static DEFINE_PER_CPU(struct stop_machine_nmi_ctrl, stop_machine_nmi_ctrl); + +static void enable_nmi_handler(struct multi_stop_data *msdata) +{ + this_cpu_write(stop_machine_nmi_ctrl.msdata, msdata); + this_cpu_write(stop_machine_nmi_ctrl.nmi_enabled, true); +} + +void __weak arch_send_self_nmi(void) +{ + /* Arch code must implement this to support stop_machine_nmi() */ +} + +bool noinstr stop_machine_nmi_handler(void) +{ + struct multi_stop_data *msdata; + int err; + + if (!raw_cpu_read(stop_machine_nmi_ctrl.nmi_enabled)) + return false; + + raw_cpu_write(stop_machine_nmi_ctrl.nmi_enabled, false); + + msdata =3D raw_cpu_read(stop_machine_nmi_ctrl.msdata); + err =3D msdata->fn(msdata->data); + raw_cpu_write(stop_machine_nmi_ctrl.err, err); + return true; +} + /* This is the cpu_stop function which stops the CPU. */ static int multi_cpu_stop(void *data) { @@ -234,8 +272,15 @@ static int multi_cpu_stop(void *data) hard_irq_disable(); break; case MULTI_STOP_RUN: - if (is_active) - err =3D msdata->fn(msdata->data); + if (is_active) { + if (msdata->use_nmi) { + enable_nmi_handler(msdata); + arch_send_self_nmi(); + err =3D raw_cpu_read(stop_machine_nmi_ctrl.err); + } else { + err =3D msdata->fn(msdata->data); + } + } break; default: break; @@ -584,14 +629,15 @@ static int __init cpu_stop_init(void) } early_initcall(cpu_stop_init); =20 -int stop_machine_cpuslocked(cpu_stop_fn_t fn, void *data, - const struct cpumask *cpus) +static int __stop_machine_cpuslocked(cpu_stop_fn_t fn, void *data, + const struct cpumask *cpus, bool use_nmi) { struct multi_stop_data msdata =3D { .fn =3D fn, .data =3D data, .num_threads =3D num_online_cpus(), .active_cpus =3D cpus, + .use_nmi =3D use_nmi, }; =20 lockdep_assert_cpus_held(); @@ -620,6 +666,24 @@ int stop_machine_cpuslocked(cpu_stop_fn_t fn, void *da= ta, return stop_cpus(cpu_online_mask, multi_cpu_stop, &msdata); } =20 +int stop_machine_cpuslocked(cpu_stop_fn_t fn, void *data, + const struct cpumask *cpus) +{ + return __stop_machine_cpuslocked(fn, data, cpus, false); +} + +int stop_machine_cpuslocked_nmi(cpu_stop_fn_t fn, void *data, + const struct cpumask *cpus) +{ + int ret; + + static_branch_enable_cpuslocked(&stop_machine_nmi_handler_enable); + ret =3D __stop_machine_cpuslocked(fn, data, cpus, true); + static_branch_disable_cpuslocked(&stop_machine_nmi_handler_enable); + + return ret; +} + int stop_machine(cpu_stop_fn_t fn, void *data, const struct cpumask *cpus) { int ret; @@ -632,6 +696,18 @@ int stop_machine(cpu_stop_fn_t fn, void *data, const s= truct cpumask *cpus) } EXPORT_SYMBOL_GPL(stop_machine); =20 +int stop_machine_nmi(cpu_stop_fn_t fn, void *data, const struct cpumask *c= pus) +{ + int ret; + + cpus_read_lock(); + ret =3D stop_machine_cpuslocked_nmi(fn, data, cpus); + cpus_read_unlock(); + + return ret; +} +EXPORT_SYMBOL_GPL(stop_machine_nmi); + #ifdef CONFIG_SCHED_SMT int stop_core_cpuslocked(unsigned int cpu, cpu_stop_fn_t fn, void *data) { --=20 2.51.0 From nobody Sat Feb 7 11:38:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 432A517DFE7 for ; Sun, 25 Jan 2026 02:06:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="73101874" X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="73101874" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2026 18:06:17 -0800 X-CSE-ConnectionGUID: KWDW7o7SQs26lZh16M50MQ== X-CSE-MsgGUID: ZKMAAgXGTbmQ73M8VhZ4Uw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="207783096" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:17 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 2/7] x86/apic: Implement self-NMI support Date: Sun, 25 Jan 2026 01:42:17 +0000 Message-ID: <20260125014224.249901-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: David Kaplan Add function to send an NMI-to-self which is needed for stop_machine_nmi(). Note that send_IPI_self() cannot be used to send an NMI so send_IPI() is used. Signed-off-by: David Kaplan Signed-off-by: Chang S. Bae --- Updates from the original version: * Rename the subject to highlight arch-side "implementation" --- arch/x86/kernel/apic/ipi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 98a57cb4aa86..6d4e5aa27529 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -4,6 +4,7 @@ #include #include #include +#include =20 #include =20 @@ -248,6 +249,12 @@ void default_send_IPI_self(int vector) __default_send_IPI_shortcut(APIC_DEST_SELF, vector); } =20 +/* Self-NMI is used in stop_machine_nmi() */ +void arch_send_self_nmi(void) +{ + apic->send_IPI(smp_processor_id(), NMI_VECTOR); +} + #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector) { --=20 2.51.0 From nobody Sat Feb 7 11:38:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A4211C5F1B for ; Sun, 25 Jan 2026 02:06:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306781; cv=none; b=E8T1/wH+JcPyc5FLyCFqbmzZ0ppXlWvRx9MaoWg5RXEtiYD699lq0/iuIq5bMHh53gaUTfDV3VLNxuLmAyDjhK7AknbXu+lqQzFHJI830W4FWZOmvsXyOOlXgBU4vW8I2kdjyVbIGbNSEEXGxKI8TKCvvVATeRwNPwNGIPLQFV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306781; c=relaxed/simple; bh=F9jQlvD6s4FxO1mPHfEv6NIDAxCzyJaCb5LH/ybDeDM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Pve3KV+xxtker0hiJI8NQBtJ64ohhyIKz9eS/nDrAB85KzWVzTy93Kn492GzMIe2jaGHwad4B09fvCvtp7VyKQAZ5Tu6G03OzQjhk56Qux5zr1zdeyoSJ6p6b9fjmwVUrSeXWyW3hsXJTJ80cnHP83O/cdS3jFr2xnkg51YsJM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ufm2voXK; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ufm2voXK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769306779; x=1800842779; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F9jQlvD6s4FxO1mPHfEv6NIDAxCzyJaCb5LH/ybDeDM=; b=Ufm2voXKGlSp7aAAgCaVKuBY9ZEDvNC0hoj56GtYaVNVAWUfpa2sDPB7 ZPoQNu4e4IuMvd/3XOe+yp+sZEXdGZgIir8//mB93Tpi4iLg1l4ZaTg4Y DGaPh27CVAzzFwLIS7xPPO4eSM+BL1sX3HmTYAzJguXKx9t2UmJAW15Af GkDivtNjh+zJgpKwM720hCiruKmtkD1veIw1hmGgpkUrGavaMuESuwUlD fo/JVvFFHBden+ybp575yxRWaKRxhTTrpcLFN9iPZ6wYi6UzjBDdsNkM3 ZucdqDNfsc8kwjRXp6uxOW7j3ELWb1ZI0PrYy5TlCQY8av+Wy4o6V8i1j g==; X-CSE-ConnectionGUID: jJnf9zx9QQKI0TYjBQRYdg== X-CSE-MsgGUID: 4A6js4V+SMKGlQ6Mi6bDsw== X-IronPort-AV: E=McAfee;i="6800,10657,11681"; a="73101881" X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="73101881" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2026 18:06:18 -0800 X-CSE-ConnectionGUID: Q4Jx2MTKSFalfbdoPquS5g== X-CSE-MsgGUID: T2VWu+l5SU6pY/qcq2UyqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="207783099" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:18 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 3/7] x86/nmi: Support stop_machine_nmi() handler Date: Sun, 25 Jan 2026 01:42:18 +0000 Message-ID: <20260125014224.249901-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: David Kaplan Call stop_machine_nmi_handler() from the NMI path when the corresponding static key is enabled, in order to support stop_machine_nmi(). Signed-off-by: David Kaplan Signed-off-by: Chang S. Bae --- Update from the original posting: * Massage the subject and expand changelog a little bit. --- arch/x86/kernel/nmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 3d239ed12744..4bc4b49f1ea7 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -24,6 +24,7 @@ #include #include #include +#include #include =20 #include @@ -382,6 +383,9 @@ static noinstr void default_do_nmi(struct pt_regs *regs) =20 instrumentation_begin(); =20 + if (stop_machine_nmi_handler_enabled() && stop_machine_nmi_handler()) + goto out; + if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) goto out; =20 --=20 2.51.0 From nobody Sat Feb 7 11:38:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 584DD1DEFE9 for ; Sun, 25 Jan 2026 02:06:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306781; cv=none; b=mAs/StiAwNcZr179tSHfwlG8SVOGL7QlZ8iIV0aKv/MblgRJ3BrSKyukA7JCTBjEcqIFqEhUGQb0XZbG4dEHi/YHOgU314Oesrs2vaP3Lo2L8Nx0J/THjz+0hDgoe71dVd9CP99RNB6BnhIERVTrMAEvcdAkU/KiG0sAfzGZ+qE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306781; c=relaxed/simple; bh=DOYTho/fiyxXqBBrzu0t5y3ClyEjIV5R9tG6NVHJtAk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uBz8PwOqlK1j5eIrrl3KyxvFzSyZ667rzHEVsmMbZs9oVZDQY1NglfBIYR1qwh/SnqVH1tSaBkk6d/GETYxR198jGuKe2wL6PUQuTOa4XeGfzlBM14Sf9HYegfl6ppAOc6q+BK2y7wfhI/zEkGG7kUCTlsZuav8j4UD2E9hzOCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JrIS0nMb; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JrIS0nMb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769306780; x=1800842780; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DOYTho/fiyxXqBBrzu0t5y3ClyEjIV5R9tG6NVHJtAk=; b=JrIS0nMbaeJwv2FY9OeQ4LaVi3+pba8zN5PUp6G3ESrsMCo96P1r2yhL R4qQ9MJumWiAW5GUNL4whqbidQ8oayu0rwjUSWkKvNnc4CiMI9KBvOJ5i XEUtnKfV0husNRc6bwvSX9rTcqkN7JOyi+zCNMyWxtQ3kVHFv5UHMh95D 75p6wkMvi+mpmkloiKEsmNRqc0Aq3rQ/LKnEmFy0tlUh207BuZhtD4e60 TaXIZehBfKJ2JlJEC6K+/YcSlNBUrR1WH8hnKfBbvfbbSjVCRZ/y9jYLl sZvHspKe5kSOqlySk66NRgKwNc2MbwGtR2Yzzw4lP30081uKl81qJ9j28 w==; X-CSE-ConnectionGUID: +YpNnqsNSrWhFbIEx29zKg== X-CSE-MsgGUID: 1Q1wyuDYQ2a3XG7s1KLq6Q== X-IronPort-AV: E=McAfee;i="6800,10657,11681"; a="73101888" X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="73101888" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2026 18:06:19 -0800 X-CSE-ConnectionGUID: nk4be7U7S5qSVPdXBcjtOw== X-CSE-MsgGUID: KRXJLrZnRFKC0x9hhICkgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="207783102" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:19 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 4/7] x86/microcode: Distinguish NMI control path on stop-machine callback Date: Sun, 25 Jan 2026 01:42:19 +0000 Message-ID: <20260125014224.249901-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" load_cpus_stopped() currently centralizes the stop_machine() callback for both NMI and NMI-less rendezvous. microcode_update_handler() alone is enough for the latter. While the NMI-based rendezvous finally reaches the same update handler, it requires additional logic to trigger and process NMIs. That machinery will be replaced by stop_machine_nmi(). As preparation for that conversion, split the callback path to make NMI-specific steps explicit and clear. Signed-off-by: Chang S. Bae --- arch/x86/kernel/cpu/microcode/core.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 68049f171860..28317176ae29 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -524,7 +524,7 @@ void noinstr microcode_offline_nmi_handler(void) wait_for_ctrl(); } =20 -static noinstr bool microcode_update_handler(void) +static noinstr int microcode_update_handler(void *unused) { unsigned int cpu =3D raw_smp_processor_id(); =20 @@ -540,7 +540,7 @@ static noinstr bool microcode_update_handler(void) touch_nmi_watchdog(); instrumentation_end(); =20 - return true; + return 0; } =20 /* @@ -561,19 +561,15 @@ bool noinstr microcode_nmi_handler(void) return false; =20 raw_cpu_write(ucode_ctrl.nmi_enabled, false); - return microcode_update_handler(); + return microcode_update_handler(NULL) =3D=3D 0; } =20 static int load_cpus_stopped(void *unused) { - if (microcode_ops->use_nmi) { - /* Enable the NMI handler and raise NMI */ - this_cpu_write(ucode_ctrl.nmi_enabled, true); - apic->send_IPI(smp_processor_id(), NMI_VECTOR); - } else { - /* Just invoke the handler directly */ - microcode_update_handler(); - } + /* Enable the NMI handler and raise NMI */ + this_cpu_write(ucode_ctrl.nmi_enabled, true); + apic->send_IPI(smp_processor_id(), NMI_VECTOR); + return 0; } =20 @@ -610,13 +606,13 @@ static int load_late_stop_cpus(bool is_safe) */ store_cpu_caps(&prev_info); =20 - if (microcode_ops->use_nmi) + if (microcode_ops->use_nmi) { static_branch_enable_cpuslocked(µcode_nmi_handler_enable); - - stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); - - if (microcode_ops->use_nmi) + stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); static_branch_disable_cpuslocked(µcode_nmi_handler_enable); + } else { + stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); + } =20 /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { --=20 2.51.0 From nobody Sat Feb 7 11:38:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 571E21EB5E1 for ; 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a="73101895" X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="73101895" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2026 18:06:20 -0800 X-CSE-ConnectionGUID: KMfx7TvSToer4R/nIVENYA== X-CSE-MsgGUID: AzJLc+l6RpC5tUksC1wFkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="207783105" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:20 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 5/7] x86/microcode: Use stop-machine NMI facility Date: Sun, 25 Jan 2026 01:42:20 +0000 Message-ID: <20260125014224.249901-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The existing NMI-based loading logic explicitly sends NMIs to online CPUs and invokes microcode_update_handler() from the NMI context. The stop-machine NMI variant already provides the mechanism on x86. Replace the custom NMI-based mechanism with the common facility to simplify the loader code. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/microcode.h | 1 - arch/x86/kernel/cpu/microcode/core.c | 19 +++---------------- arch/x86/kernel/nmi.c | 3 --- 3 files changed, 3 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 8b41f26f003b..946b0cebed87 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -77,7 +77,6 @@ static inline u32 intel_get_microcode_revision(void) } #endif /* !CONFIG_CPU_SUP_INTEL */ =20 -bool microcode_nmi_handler(void); void microcode_offline_nmi_handler(void); =20 #ifdef CONFIG_MICROCODE_LATE_LOADING diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 28317176ae29..0facadea39d6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -555,22 +555,9 @@ static noinstr int microcode_update_handler(void *unus= ed) * path which must be NMI safe until the primary thread completed the * update. */ -bool noinstr microcode_nmi_handler(void) +static noinstr int microcode_nmi_handler(void *data) { - if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) - return false; - - raw_cpu_write(ucode_ctrl.nmi_enabled, false); - return microcode_update_handler(NULL) =3D=3D 0; -} - -static int load_cpus_stopped(void *unused) -{ - /* Enable the NMI handler and raise NMI */ - this_cpu_write(ucode_ctrl.nmi_enabled, true); - apic->send_IPI(smp_processor_id(), NMI_VECTOR); - - return 0; + return microcode_update_handler(data); } =20 static int load_late_stop_cpus(bool is_safe) @@ -608,7 +595,7 @@ static int load_late_stop_cpus(bool is_safe) =20 if (microcode_ops->use_nmi) { static_branch_enable_cpuslocked(µcode_nmi_handler_enable); - stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); + stop_machine_cpuslocked_nmi(microcode_nmi_handler, NULL, cpu_online_mask= ); static_branch_disable_cpuslocked(µcode_nmi_handler_enable); } else { stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 4bc4b49f1ea7..642469f3be80 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -386,9 +386,6 @@ static noinstr void default_do_nmi(struct pt_regs *regs) if (stop_machine_nmi_handler_enabled() && stop_machine_nmi_handler()) goto out; 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d="scan'208";a="207783109" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:21 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 6/7] x86/nmi: Reference stop-machine static key for offline microcode handler Date: Sun, 25 Jan 2026 01:42:21 +0000 Message-ID: <20260125014224.249901-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The microcode loader now uses stop-machine facility for NMI-based loading. During the rendezvous, the stop-machine static key is enabled and can be queried via stop_machine_nmi_handler_enabled(). Reference this on the offline handling path. Previously, the microcode-specific static key helper returned false when CONFIG_MICROCODE_LATE_LOADING=3Dn. Since the offline handler is also built only with that option, the helper effectively acted as a guard to avoid referencing the handler symbol when it was not present. With the removal, to avoid build issues, introduce a one-line helper. Signed-off-by: Chang S. Bae --- Note on an alternative option: Rather than keeping this loader-specific handler, stop-machine facility could be extended further to call-back to handle offline cases. Then, the microcode loader however will be the only user of that. Instead, just switching to check the stop-machine helper looks to be simple enough. --- arch/x86/include/asm/microcode.h | 5 +++-- arch/x86/kernel/nmi.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 946b0cebed87..a4e4ea8acf99 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -77,15 +77,16 @@ static inline u32 intel_get_microcode_revision(void) } #endif /* !CONFIG_CPU_SUP_INTEL */ =20 -void microcode_offline_nmi_handler(void); - #ifdef CONFIG_MICROCODE_LATE_LOADING +void microcode_offline_nmi_handler(void); + DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static __always_inline bool microcode_nmi_handler_enabled(void) { return static_branch_unlikely(µcode_nmi_handler_enable); } #else +static __always_inline void microcode_offline_nmi_handler(void) { } static __always_inline bool microcode_nmi_handler_enabled(void) { return f= alse; } #endif =20 diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 642469f3be80..52bc844354de 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -548,7 +548,7 @@ DEFINE_IDTENTRY_RAW(exc_nmi) raw_atomic_long_inc(&nsp->idt_calls); =20 if (arch_cpu_is_offline(smp_processor_id())) { - if (microcode_nmi_handler_enabled()) + if (stop_machine_nmi_handler_enabled()) microcode_offline_nmi_handler(); return; } @@ -711,7 +711,7 @@ DEFINE_FREDENTRY_NMI(exc_nmi) irqentry_state_t irq_state; =20 if (arch_cpu_is_offline(smp_processor_id())) { - if (microcode_nmi_handler_enabled()) + if (stop_machine_nmi_handler_enabled()) microcode_offline_nmi_handler(); return; } --=20 2.51.0 From nobody Sat Feb 7 11:38:07 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59B572066F7 for ; Sun, 25 Jan 2026 02:06:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306784; cv=none; b=SLjBZ4CmhKw0ADAIs+VP1VgwyRvA/FrtX2NBJQTOXBZKs747N6CUT+3BXzsaptjdUw0i1HeXnXP6vWYEGaHti6LRKouhZ30KSmj7wtYX0drUlT6IRnrldSBwTLKDlafyO0WjsPt3FkFYfONF5BVqOG4Kg2ujupO0DfqP8WmNcQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769306784; c=relaxed/simple; bh=9EpnMB99fBJ2xiP0DqgEPLPLXNhfK0CkMkb/JRyLFJ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cYdGbfSj656VeX++Rny5Mo3v4gyZGeqMLw7avSyGc6EWcHSvdFHuOwvfyt6NKDK0y/y2KaTZQdvhENg3pk7kRn8lUWm1GEPx9F2phfnO7DrAj3ztLGcvFrixXW4Vma28qd92zX66d1ZQLXq1wkx3XeCwGYcHcxaMKJN8qENNbac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nHYR/+Tf; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nHYR/+Tf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769306782; x=1800842782; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9EpnMB99fBJ2xiP0DqgEPLPLXNhfK0CkMkb/JRyLFJ4=; b=nHYR/+Tfu/UAv/Ubn6v80t1cRBuCY0jA5/HAhiy9DHbQG2jlJizMzSrh Nv//yoc0zCsth3NZlSlYa3YpdZfoNl8xIhuE0TUD8Ug3sfTZiV+upkjY8 MxUSk2vIvH0x8UDLYmnqYql5SkTSzXhB9tUk0FkXIINPEZpxINtpjfkfU U1QBxan/A4WKLudD7/q7hPFpkIeBduhhNEEWwGX21B2XrmTHtJYMvnmG/ mnLTdqPUC3pFg252Gpxyp6lvTvv3z5CWXjcLW0sW/zApp3Qi73phlT3zE GjmXnOxfwhmQJ7rtj5wFbkcoV3YtMhP4QnFhgv8uowljsrYEfR5P7jx5A A==; X-CSE-ConnectionGUID: OkTMcfneQ3qNc/SQlfbo6Q== X-CSE-MsgGUID: +iC2dVb+THWiRbMVEmaTNg== X-IronPort-AV: E=McAfee;i="6800,10657,11681"; a="73101909" X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="73101909" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2026 18:06:22 -0800 X-CSE-ConnectionGUID: qPIPpo5dS6iEoKKr74IBmQ== X-CSE-MsgGUID: fT9iZ4PERJCaL3leKNkInw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,252,1763452800"; d="scan'208";a="207783114" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa009.fm.intel.com with ESMTP; 24 Jan 2026 18:06:22 -0800 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH 7/7] x86/microcode: Remove microcode_nmi_handler_enable Date: Sun, 25 Jan 2026 01:42:22 +0000 Message-ID: <20260125014224.249901-8-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260125014224.249901-1-chang.seok.bae@intel.com> References: <20260125014224.249901-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove it, as there is no more user. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/microcode.h | 7 ------- arch/x86/kernel/cpu/microcode/core.c | 8 ++------ 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index a4e4ea8acf99..b7e89fc45500 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -79,15 +79,8 @@ static inline u32 intel_get_microcode_revision(void) =20 #ifdef CONFIG_MICROCODE_LATE_LOADING void microcode_offline_nmi_handler(void); - -DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); -static __always_inline bool microcode_nmi_handler_enabled(void) -{ - return static_branch_unlikely(µcode_nmi_handler_enable); -} #else static __always_inline void microcode_offline_nmi_handler(void) { } -static __always_inline bool microcode_nmi_handler_enabled(void) { return f= alse; } #endif =20 #endif /* _ASM_X86_MICROCODE_H */ diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 0facadea39d6..35b1b5d88893 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -316,7 +316,6 @@ struct microcode_ctrl { bool nmi_enabled; }; =20 -DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); static atomic_t late_cpus_in, offline_in_nmi; static unsigned int loops_per_usec; @@ -593,13 +592,10 @@ static int load_late_stop_cpus(bool is_safe) */ store_cpu_caps(&prev_info); =20 - if (microcode_ops->use_nmi) { - static_branch_enable_cpuslocked(µcode_nmi_handler_enable); + if (microcode_ops->use_nmi) stop_machine_cpuslocked_nmi(microcode_nmi_handler, NULL, cpu_online_mask= ); - static_branch_disable_cpuslocked(µcode_nmi_handler_enable); - } else { + else stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); - } =20 /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { --=20 2.51.0