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Sat, 24 Jan 2026 21:48:23 -0800 (PST) From: Guodong Xu Date: Sun, 25 Jan 2026 09:36:06 +0800 Subject: [PATCH v2 1/3] dt-bindings: riscv: Add Supm extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260125-supm-ext-id-v2-1-1e3b9714c860@riscstar.com> References: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> In-Reply-To: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Samuel Holland , Heinrich Schuchardt , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Evan Green , Andrew Jones , Conor Dooley Cc: Paul Walmsley , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Add description for the Supm extension. Supm indicates support for pointer masking in user mode. Supm is mandatory for RVA23S64. Add dependency check that Supm requires either Smnpm or Ssnpm. The Supm extension is ratified in commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. Signed-off-by: Guodong Xu Acked-by: Conor Dooley --- v2: Add dependency check for Sump. Put the check blok after single-letters and before Z*. --- .../devicetree/bindings/riscv/extensions.yaml | 27 ++++++++++++++++++= ++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index c6ec9290fe07..2b0a8a93bb21 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -262,6 +262,23 @@ properties: ratified in RISC-V Profiles Version 1.0, with commit b1d806605= f87 ("Updated to ratified state.") =20 + - const: supm + description: | + The standard Supm extension for pointer masking support in user + mode (U-mode) as ratified at commit d70011dde6c2 ("Update to + ratified state") of riscv-j-extension. + + Supm represents a combination of underlying hardware capability + (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode + software configuration that enables pointer masking for U-mode. + + DO NOT include this property in device trees targeting privile= ged + system software (S-mode or M-mode). + + This property is only appropriate in device trees provided to + U-mode software where the next-higher-privilege-mode supports + Smnpm or Ssnpm and enables it for U-mode. + - const: svade description: | The standard Svade supervisor-level extension for SW-managed P= TE A/D @@ -907,6 +924,16 @@ properties: then: contains: const: b + # Supm depends on Smnpm or Ssnpm + - if: + contains: + const: supm + then: + oneOf: + - contains: + const: smnpm + - contains: + const: ssnpm # Za64rs and Ziccrse depend on Zalrsc or A - if: contains: --=20 2.43.0 From nobody Sat Feb 7 05:14:50 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 011443101B0 for ; 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Sat, 24 Jan 2026 21:48:31 -0800 (PST) Received: from [127.0.1.1] ([2a12:a305:4::30fc]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c635a3f1ebesm5680016a12.19.2026.01.24.21.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jan 2026 21:48:30 -0800 (PST) From: Guodong Xu Date: Sun, 25 Jan 2026 09:36:07 +0800 Subject: [PATCH v2 2/3] riscv: cpufeature: Add ISA extension parsing for Supm Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260125-supm-ext-id-v2-2-1e3b9714c860@riscstar.com> References: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> In-Reply-To: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Samuel Holland , Heinrich Schuchardt , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Evan Green , Andrew Jones , Conor Dooley Cc: Paul Walmsley , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Supm has been ratified in the RISC-V Pointer Masking specification (Version 1.0, 10/2024) and is mandated in RVA23 Profiles (Version 1.0, 2024-10-17) for RVA23U64. Supm indicates userspace pointer masking support. Remove the previous macro aliasing of Supm to Ssnpm/Smnpm in hwcap.h, treating Supm as a distinct RISC-V ISA extension ID. Add ISA parsing logic for Supm, and implement a validator to ensure that Supm is only reported as available if Kconfig allows it and the underlying Ssnpm (for supervisor mode) or Smnpm (for machine mode) extension is present. Supm relies on Ssnpm or Smnpm to provide the underlying hardware implementation. With this change, "supm" will be reported (when available) in /proc/cpuinfo as part of the "isa" and "hart isa" string. Reviewed-by: Conor Dooley Link: https://lore.kernel.org/lkml/20260101-legume-engraved-0fae8282cfbe@sp= ud/#r [1] Link: https://lore.kernel.org/all/4ebbe14b-2579-4ba6-808d-d50c24641d04@sifi= ve.com/#r [2] Signed-off-by: Guodong Xu --- v2: Add Reviewed-by from Conor. Update RISCV_ISA_EXT_SUPM id to solve rebase conflict. --- arch/riscv/include/asm/hwcap.h | 3 +-- arch/riscv/kernel/cpufeature.c | 35 +++++++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ef8e5f55c8d..aa2af21f3bd3 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -112,6 +112,7 @@ #define RISCV_ISA_EXT_ZCLSD 103 #define RISCV_ISA_EXT_ZICFILP 104 #define RISCV_ISA_EXT_ZICFISS 105 +#define RISCV_ISA_EXT_SUPM 106 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 @@ -120,10 +121,8 @@ =20 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA -#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM #else #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA -#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM #endif =20 #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1734f9a4c2fd..e1f7ad882289 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -317,6 +317,27 @@ static int riscv_cfiss_validate(const struct riscv_isa= _ext_data *data, return 0; } =20 +static int riscv_ext_supm_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_SUPM)) + return -EINVAL; + + /* + * Supm requires Ssnpm for S-mode or Smnpm for M-mode to provide + * pointer masking for the U-mode execution environment. + */ + if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SMNPM)) + return 0; + } else { + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSNPM)) + return 0; + } + + return -EPROBE_DEFER; +} + static const unsigned int riscv_a_exts[] =3D { RISCV_ISA_EXT_ZAAMO, RISCV_ISA_EXT_ZALRSC, @@ -450,6 +471,15 @@ static const unsigned int riscv_c_exts[] =3D { RISCV_ISA_EXT_ZCD, }; =20 +/* + * Smnpm and Ssnpm provide pointer masking for the next lower privilege mo= de + * (U-mode), thus enabling Supm. Both extensions imply the same subset. + */ +static const unsigned int riscv_supm_exts[] =3D { + RISCV_ISA_EXT_XLINUXENVCFG, + RISCV_ISA_EXT_SUPM +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -577,12 +607,13 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), - __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), + __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), + __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA_VALIDATE(supm, RISCV_ISA_EXT_SUPM, riscv_ext_supm_va= lidate), __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu= _validate), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), --=20 2.43.0 From nobody Sat Feb 7 05:14:50 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6D2D310777 for ; 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Sat, 24 Jan 2026 21:48:38 -0800 (PST) Received: from [127.0.1.1] ([2a12:a305:4::30fc]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c635a3f1ebesm5680016a12.19.2026.01.24.21.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jan 2026 21:48:37 -0800 (PST) From: Guodong Xu Date: Sun, 25 Jan 2026 09:36:08 +0800 Subject: [PATCH v2 3/3] riscv: cpufeature: Clarify ISA spec version for canonical order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260125-supm-ext-id-v2-3-1e3b9714c860@riscstar.com> References: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> In-Reply-To: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Samuel Holland , Heinrich Schuchardt , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Evan Green , Andrew Jones , Conor Dooley Cc: Paul Walmsley , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Specify that chapter 27 refers to version 20191213 of the RISC-V ISA Unprivileged Architecture. The chapter numbering differs across specification versions - for example, in version 20250508, the ISA Extension Naming Conventions is chapter 36, not chapter 27. Historical versions of the RISC-V specification can be found via Link [1]. Acked-by: Conor Dooley Link: https://riscv.org/specifications/ratified/ [1] Fixes: 99e2266f2460 ("RISC-V: clarify ISA string ordering rules in cpu.c") Signed-off-by: Guodong Xu --- v2: Add Acked-by from Conor. Update the Fixes tag to point to the original commit who added the description. --- arch/riscv/kernel/cpufeature.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e1f7ad882289..63ad6393b2c6 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -482,7 +482,8 @@ static const unsigned int riscv_supm_exts[] =3D { =20 /* * The canonical order of ISA extension names in the ISA string is defined= in - * chapter 27 of the unprivileged specification. + * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged I= SA + * (Document Version 20191213). * * Ordinarily, for in-kernel data structures, this order is unimportant but * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. --=20 2.43.0