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charset="utf-8" Add device tree nodes for the DSI0 controller with their corresponding PHY found on Qualcomm QCS8300 SoC. Signed-off-by: Ayushi Makhija Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco.dtsi | 105 ++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 5d2df4305d1c..7dda05bda3e7 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ =20 +#include #include #include #include @@ -5573,9 +5574,19 @@ port@0 { reg =3D <0>; =20 dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; }; }; + + port@1 { + reg =3D <1>; + + dpu_intf1_out: endpoint { + + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; }; =20 mdp_opp_table: opp-table { @@ -5603,6 +5614,96 @@ opp-650000000 { }; }; =20 + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,qcs8300-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,qcs8300-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg =3D <0x0 0x0ae94400 0x0 0x200>, + <0x0 0x0ae94600 0x0 0x280>, + <0x0 0x0ae94900 0x0 0x280>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; 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Sat, 24 Jan 2026 20:39:32 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 60OKdTCW031206; Sat, 24 Jan 2026 20:39:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4bvq5ke8jb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 24 Jan 2026 20:39:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 60OKdSeF031188; Sat, 24 Jan 2026 20:39:29 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-amakhija-hyd.qualcomm.com [10.213.99.91]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 60OKdSRZ031182 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 24 Jan 2026 20:39:28 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 4090850) id EE1325CB; Sun, 25 Jan 2026 02:09:27 +0530 (+0530) From: Ayushi Makhija To: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ayushi Makhija , robdclark@gmail.com, dmitry.baryshkov@oss.qualcomm.com, sean@poorly.run, marijn.suijten@somainline.org, andersson@kernel.org, robh@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, konradybcio@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonathan@marek.ca, jonas@kwiboo.se, jernej.skrabec@gmail.com, quic_rajeevny@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH v6 2/2] arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node Date: Sun, 25 Jan 2026 02:09:25 +0530 Message-Id: <20260124203925.2614008-3-quic_amakhija@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260124203925.2614008-1-quic_amakhija@quicinc.com> References: <20260124203925.2614008-1-quic_amakhija@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r6wKDZQk-EoOzHAXmjma4B7pO0DfDMJz X-Authority-Analysis: v=2.4 cv=BteQAIX5 c=1 sm=1 tr=0 ts=69752e04 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=PkzH0pPD3_lowiemrhkA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: r6wKDZQk-EoOzHAXmjma4B7pO0DfDMJz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI0MDE2OCBTYWx0ZWRfXwesprPk743QV UaWsxD1jCMSeaRoM7EujvNiUQnVIfYKL6ur9rnEW0ZAjJLr2Fi7o3GMoJRZ9E7wY8wfvmszc7o1 +PPcR0YhvWZAcqwxtiTrAvmcCRPSJPLbBFQVVIdoCCZzourVHK36zXKHT3J9RE5JoXCBXtfJcoE Nd8eJvtYU9ZlkhKR0C5R2c674j3DicjG6lGxfC/R/y7DDtVu/XLqQ5hi21pYWW4Mr2b1VL9k9wY g1QbKL9UyAXXr7qXVbLNExGo3yWqxYHp7DrccmPcIBxv66rz/idh3cEQU+56J6YwnJG2GL7gyGg w8LObUGuVgQbV4uKoFfaYV3099LRdMIhyNotjjHblu0/gmO0JpmS1BWmErnQSGJBut9ZxGiv6vJ GC0At0jjrdsuT/HxwkiySOlXP0dKi8dLEcfhicGNMemq/nTZ8PQ6iQXZtt0+xdSsRQ09p92omru oGEW8fFSmHBM8mP1/bQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-24_03,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601240168 Content-Type: text/plain; charset="utf-8" Add anx7625 DSI to DP bridge device node. Signed-off-by: Ayushi Makhija Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 179 ++++++++++++++++++++++ 1 file changed, 179 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index c04e0ad53eec..36cbcea32881 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -24,6 +24,69 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + vreg_1p0: regulator-vreg-1p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P0"; + + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + vin-supply =3D <&vreg_1p8>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + vin-supply =3D <&vreg_5p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_3p0: regulator-vreg-3p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_3P0"; + + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + vin-supply =3D <&vreg_12p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_5p0: regulator-vreg-5p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_5P0"; + + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + vin-supply =3D <&vreg_12p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_12p0: regulator-vreg-12p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_12P0"; + + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + + regulator-always-on; + regulator-boot-on; + }; + dp0-connector { compatible =3D "dp-connector"; label =3D "DP0"; @@ -36,6 +99,18 @@ dp0_connector_in: endpoint { }; }; =20 + dp-dsi0-connector { + compatible =3D "dp-connector"; + label =3D "DSI0"; + type =3D "full-size"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint =3D <&dsi2dp_bridge_out>; + }; + }; + }; + regulator-usb2-vbus { compatible =3D "regulator-fixed"; regulator-name =3D "USB2_VBUS"; @@ -316,6 +391,75 @@ &gpu_zap_shader { firmware-name =3D "qcom/qcs8300/a623_zap.mbn"; }; =20 +&i2c8 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + io_expander: gpio@74 { + compatible =3D "ti,tca9539"; + reg =3D <0x74>; + interrupts-extended =3D <&tlmm 93 IRQ_TYPE_EDGE_BOTH>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + reset-gpios =3D <&tlmm 66 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&io_expander_intr_active>, + <&io_expander_reset_active>; + pinctrl-names =3D "default"; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + reg =3D <0x70>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + bridge@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupts-extended =3D <&io_expander 2 IRQ_TYPE_EDGE_FALLING>; + enable-gpios =3D <&io_expander 1 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&io_expander 0 GPIO_ACTIVE_HIGH>; + vdd10-supply =3D <&vreg_1p0>; + vdd18-supply =3D <&vreg_1p8>; + vdd33-supply =3D <&vreg_3p0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dsi2dp_bridge_in: endpoint { + + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi2dp_bridge_out: endpoint { + + remote-endpoint =3D <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + &pmm8650au_1_gpios { usb2_en: usb2-en-state { pins =3D "gpio7"; @@ -391,10 +535,31 @@ &pcie1_phy { status =3D "okay"; }; =20 +&mdss_dsi0 { + vdda-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l4a>; + + status =3D "okay"; +}; + +&mdss_dsi0_out { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&dsi2dp_bridge_in>; +}; + &qupv3_id_0 { status =3D "okay"; }; =20 +&qupv3_id_1 { + status =3D "okay"; +}; + &remoteproc_adsp { firmware-name =3D "qcom/qcs8300/adsp.mbn"; status =3D "okay"; @@ -498,6 +663,20 @@ perst-pins { }; }; =20 + io_expander_reset_active: io-expander-reset-active-state { + pins =3D "gpio66"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + io_expander_intr_active: io-expander-intr-active-state { + pins =3D "gpio93"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + dp_hot_plug_det: dp-hot-plug-det-state { pins =3D "gpio94"; function =3D "edp0_hot"; --=20 2.34.1