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Add the clock resets required from the GCC clock controller for Video. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++ include/dt-bindings/clock/qcom,glymur-gcc.h | 1 + include/dt-bindings/clock/qcom,glymur-videocc.h | 45 ++++++++++++++++++= ++++ 3 files changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index e6beebd6a36ee1ce213a816f60df8a76fa5c44d6..7bbf120d928cc506a4f7aaeaa1c= 24e5da760e450 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -15,6 +15,7 @@ description: | domains on SM8450. =20 See also: + include/dt-bindings/clock/qcom,glymur-videocc.h include/dt-bindings/clock/qcom,kaanapali-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h @@ -23,6 +24,7 @@ description: | properties: compatible: enum: + - qcom,glymur-videocc - qcom,kaanapali-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc @@ -63,6 +65,7 @@ allOf: compatible: contains: enum: + - qcom,glymur-videocc - qcom,kaanapali-videocc - qcom,sm8450-videocc - qcom,sm8550-videocc diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindi= ngs/clock/qcom,glymur-gcc.h index 10c12b8c51c34c5931c34b4437be03aea098ba53..6907653c79927f0ff32c98c75d8= 30b719ce14d51 100644 --- a/include/dt-bindings/clock/qcom,glymur-gcc.h +++ b/include/dt-bindings/clock/qcom,glymur-gcc.h @@ -574,5 +574,6 @@ #define GCC_VIDEO_AXI0_CLK_ARES 89 #define GCC_VIDEO_AXI1_CLK_ARES 90 #define GCC_VIDEO_BCR 91 +#define GCC_VIDEO_AXI0C_CLK_ARES 92 =20 #endif diff --git a/include/dt-bindings/clock/qcom,glymur-videocc.h b/include/dt-b= indings/clock/qcom,glymur-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..98c0debef8fa9d67a2fb86a0e42= d6e207ad89c09 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-videocc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_FREERUN_CLK 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_FREERUN_CLK 9 +#define VIDEO_CC_MVS0C_SHIFT_CLK 10 +#define VIDEO_CC_MVS1_CLK 11 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 12 +#define VIDEO_CC_MVS1_FREERUN_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_PLL0 15 +#define VIDEO_CC_SLEEP_CLK 16 +#define VIDEO_CC_SLEEP_CLK_SRC 17 +#define VIDEO_CC_XO_CLK 18 +#define VIDEO_CC_XO_CLK_SRC 19 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 +#define VIDEO_CC_MVS1_GDSC 2 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_BCR 2 +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 3 +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4 +#define VIDEO_CC_MVS1_FREERUN_CLK_ARES 5 +#define VIDEO_CC_XO_CLK_ARES 6 +#define VIDEO_CC_MVS1_BCR 7 +#endif --=20 2.34.1 From nobody Sun Feb 8 22:21:18 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5E7722A4F1 for ; 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Sat, 24 Jan 2026 09:35:35 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a802daa79dsm49036765ad.3.2026.01.24.09.35.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jan 2026 09:35:35 -0800 (PST) From: Taniya Das Date: Sat, 24 Jan 2026 23:05:03 +0530 Subject: [PATCH 2/2] clk: qcom: videocc-glymur: Add video clock controller driver for Glymur Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260124-glymur_videocc-v1-2-668f8b9c63be@oss.qualcomm.com> References: <20260124-glymur_videocc-v1-0-668f8b9c63be@oss.qualcomm.com> In-Reply-To: <20260124-glymur_videocc-v1-0-668f8b9c63be@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=YLGSCBGx c=1 sm=1 tr=0 ts=697502e9 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=AGQeBkLEtNaMSr1_6oIA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: jA0bVeWblOrmTuFpjiHsYOw8B7yzK-S2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI0MDE0MSBTYWx0ZWRfX0BOMoLYWLXCE cuIOzWu8JqchipjoYj8+bdJzDILRJzR/3st3Mq0D6ra9A6bGh7ayN9MlQVKggPamky7RYqy0O3U qRrGRcEtit736QpEOe8i2DpwQfBOVerRP8YKWYDTZIQUKd0Aa8xGaTP+l/Z7iLntXpu6AbBrxut DqSa+radLDibS3KlnScLCG3M89xeekSF4O53Ji+laNl3ObzBeHh7tvMFOjOuyO5XRxDvlQTmDo1 GVWGQLBbLcCFLw7BFK2jp2IjjBsTxHqBVmsC2Rg994TDV7S5nfPjG325m1JbGU9qrzy/ohXWkEu oWJqAGRsA1WMr1wsvckogih1EAjng3FXGCOSlC9BVF5YY8G+mlUVS8mn4JCgwAKYS8Bt/eyTYGr ohmLun4I+u+nn8pjoqPhasRknGGKDR6yEMdxi9D79ILbkiEEHSQ0ltf88zMAG6WajDaqYIHxSOz 4s/jzpmDiPYGiejtRvg== X-Proofpoint-ORIG-GUID: jA0bVeWblOrmTuFpjiHsYOw8B7yzK-S2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-24_02,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601240141 Add support for the video clock controller for video clients to be able to request for videocc clocks on Glymur platform. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-glymur.c | 1 + drivers/clk/qcom/videocc-glymur.c | 526 ++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 537 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a8a86ea6bb7445e396048a5bba23fce8d719281f..20af4340b08f98773eadcc4a97b= 1669f51277eb8 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -46,6 +46,15 @@ config CLK_GLYMUR_TCSRCC Support for the TCSR clock controller on GLYMUR devices. Say Y if you want to use peripheral devices such as USB/PCIe/EDP. =20 +config CLK_GLYMUR_VIDEOCC + tristate "Glymur Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_GLYMUR_GCC + help + Support for the video clock controller on Glymur devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config CLK_KAANAPALI_CAMCC tristate "Kaanapali Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b0ad8832b55f1914079f15323b8cdd1608ad4c0..a71dfd0ddf5122d91b5ab4427a9= e36cdd57f7bbd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_GCC) +=3D gcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o +obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) +=3D videocc-glymur.o obj-$(CONFIG_CLK_KAANAPALI_CAMCC) +=3D cambistmclkcc-kaanapali.o camcc-kaa= napali.o obj-$(CONFIG_CLK_KAANAPALI_DISPCC) +=3D dispcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c index 238e205735ed594618b8526651968a4f73b1104e..cd11470a75f3fec67c1c0cb7fb2= b54a814cfaf65 100644 --- a/drivers/clk/qcom/gcc-glymur.c +++ b/drivers/clk/qcom/gcc-glymur.c @@ -8507,6 +8507,7 @@ static const struct qcom_reset_map gcc_glymur_resets[= ] =3D { [GCC_VIDEO_AXI0_CLK_ARES] =3D { 0x3201c, 2 }, [GCC_VIDEO_AXI1_CLK_ARES] =3D { 0x32044, 2 }, [GCC_VIDEO_BCR] =3D { 0x32000 }, + [GCC_VIDEO_AXI0C_CLK_ARES] =3D { 0x32030, 2 }, }; =20 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { diff --git a/drivers/clk/qcom/videocc-glymur.c b/drivers/clk/qcom/videocc-g= lymur.c new file mode 100644 index 0000000000000000000000000000000000000000..a5045866982554ea46a9d750335= 37e7771df8fd9 --- /dev/null +++ b/drivers/clk/qcom/videocc-glymur.c @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SLEEP_CLK, + P_VIDEO_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco taycan_eko_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1965000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x8120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x80f8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src =3D { + .reg =3D 0x809c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0x8060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src =3D { + .reg =3D 0x80d8, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x807c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_freerun_clk =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x8114, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8114, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8114, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_freerun_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x811c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x811c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x811c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk =3D { + .halt_reg =3D 0x80b8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80b8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_freerun_clk =3D { + .halt_reg =3D 0x80c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_shift_clk =3D { + .halt_reg =3D 0x8118, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8118, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x8034, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x8068, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .parent =3D &video_cc_mvs0c_gdsc.pd, +}; + +static struct gdsc video_cc_mvs1_gdsc =3D { + .gdscr =3D 0x80a4, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *video_cc_glymur_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] =3D &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0_FREERUN_CLK] =3D &video_cc_mvs0_freerun_clk.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs0c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS0C_FREERUN_CLK] =3D &video_cc_mvs0c_freerun_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_MVS1_CLK] =3D &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] =3D &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1_FREERUN_CLK] =3D &video_cc_mvs1_freerun_clk.clkr, + [VIDEO_CC_MVS1_SHIFT_CLK] =3D &video_cc_mvs1_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_glymur_gdscs[] =3D { + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, + [VIDEO_CC_MVS1_GDSC] =3D &video_cc_mvs1_gdsc, +}; + +static const struct qcom_reset_map video_cc_glymur_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x80dc }, + [VIDEO_CC_MVS0_BCR] =3D { 0x8064 }, + [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] =3D { 0x805c, 2 }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8030 }, + [VIDEO_CC_MVS0_FREERUN_CLK_ARES] =3D { 0x808c, 2 }, + [VIDEO_CC_MVS1_FREERUN_CLK_ARES] =3D { 0x80c8, 2 }, + [VIDEO_CC_MVS1_BCR] =3D { 0x80a0 }, +}; + +static struct clk_alpha_pll *video_cc_glymur_plls[] =3D { + &video_cc_pll0, +}; + +static u32 video_cc_glymur_critical_cbcrs[] =3D { + 0x80e0, /* VIDEO_CC_AHB_CLK */ + 0x8138, /* VIDEO_CC_SLEEP_CLK */ + 0x8110, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_glymur_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9f54, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data video_cc_glymur_driver_data =3D { + .alpha_plls =3D video_cc_glymur_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_glymur_plls), + .clk_cbcrs =3D video_cc_glymur_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_glymur_critical_cbcrs), +}; + +static struct qcom_cc_desc video_cc_glymur_desc =3D { + .config =3D &video_cc_glymur_regmap_config, + .clks =3D video_cc_glymur_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_glymur_clocks), + .resets =3D video_cc_glymur_resets, + .num_resets =3D ARRAY_SIZE(video_cc_glymur_resets), + .gdscs =3D video_cc_glymur_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_glymur_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_glymur_driver_data, +}; + +static const struct of_device_id video_cc_glymur_match_table[] =3D { + { .compatible =3D "qcom,glymur-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_glymur_match_table); + +static int video_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_glymur_desc); +} + +static struct platform_driver video_cc_glymur_driver =3D { + .probe =3D video_cc_glymur_probe, + .driver =3D { + .name =3D "videocc-glymur", + .of_match_table =3D video_cc_glymur_match_table, + }, +}; + +module_platform_driver(video_cc_glymur_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC Glymur Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1