From nobody Sun Feb 8 06:05:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FD6D2C21C4; Fri, 23 Jan 2026 18:20:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769192444; cv=none; b=ukw2Ykkdlk/RnwePFOENLrKquLkf37g1wVDCef89Z5vDUQIQr3cnjljlpCZEr4EQ7NDStVJukbNctp+rqA1SYyIdk1kQJsmz7Opy10Q4By1a8SaeWx9iQiU7JwcwzMiSvN/pKKRCtZ/twuHdbeO4WcBQOZqYrkPyfQSMNLUAS1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769192444; c=relaxed/simple; bh=C1HrRs33eYxwgMfsTwS8l4kxnuIa+/Yx9xWlRmLSqbY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jP1wJO179GE+sWlddvGqOWdgXmyDrIztFqjURQKZcoLoUzOJPXitPIqtl13o8CMsunr/r18asbEnWADlmjG1KDfnIOb/q2V3tVRA3Xw4MlM1tW0wuQRcJqhtYxdl62S8MJvYdi3MgQxxwV2vrkvlVXh/PDa/7ncJGXHo7TGK+qA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iYbaShbb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iYbaShbb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 27855C4CEF1; Fri, 23 Jan 2026 18:20:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769192444; bh=C1HrRs33eYxwgMfsTwS8l4kxnuIa+/Yx9xWlRmLSqbY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iYbaShbbFzj4+TJQrT4UFlsd/KuYnqX1C+LEWHSC3DhQehxvSqczGE80PxlpqryBZ EvmEj4vlp3d0DC5yZ2mzpBxBHD9N9/2Yi9PWJvVED9M+N2cNhl1dei8M3cWZ5yQbFR Gg2V6BN/V6tzZCfjqRJ4Q9hHd7bmnKzTlWejKlPyY+zWgF6hM0HQ1H1aNm/gFVEPFz tYtHCndnFI5++6TX9xFzzKt24vsrERqyANrnGORFezvGSBSDPh89Ibbr3d2H4Ab/pN Yn3Dbu/FolhV1WHYq510RPKp1cq2ZxCHppLdvxwxQAtD/11BMaqSSyUNSzGbaHzcdZ EHvJhNisf94IQ== From: Stephen Boyd To: Greg Kroah-Hartman Cc: Jishnu Prakash , linux-kernel@vger.kernel.org, patches@lists.linux.dev, David Collins , Pankaj Patil , Kamal Wadhwa , Jingyi Wang , "Rob Herring (Arm)" Subject: [PATCH 08/10] dt-bindings: spmi: add support for glymur-spmi-pmic-arb (arbiter v8) Date: Fri, 23 Jan 2026 10:20:36 -0800 Message-ID: <20260123182039.224314-9-sboyd@kernel.org> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20260123182039.224314-1-sboyd@kernel.org> References: <20260123182039.224314-1-sboyd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jishnu Prakash SPMI PMIC Arbiter version 8 builds upon version 7 with support for up to four SPMI buses. To achieve this, the register map was slightly rearranged. Add a new binding file and compatible string for version 8 using the name 'glymur' as the Qualcomm Technologies, Inc. Glymur SoC is the first one to use PMIC arbiter version 8. This specifies the new register ranges needed only for version 8. Also document SPMI PMIC Arbiter for Qualcomm Kaanapali SoC, by adding fallback to Glymur compatible string, as it too has version 8 functionality. Signed-off-by: David Collins Signed-off-by: Pankaj Patil Signed-off-by: Kamal Wadhwa Signed-off-by: Jingyi Wang Reviewed-by: Rob Herring (Arm) Signed-off-by: Jishnu Prakash Signed-off-by: Stephen Boyd --- .../spmi/qcom,glymur-spmi-pmic-arb.yaml | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/qcom,glymur-spmi= -pmic-arb.yaml diff --git a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-a= rb.yaml b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.= yaml new file mode 100644 index 000000000000..3b5005b96c6d --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8) + +maintainers: + - David Collins + +description: | + The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI + controller with wrapping arbitration logic to allow for multiple on-chip + devices to control up to 4 SPMI separate buses. + + The PMIC Arbiter can also act as an interrupt controller, providing inte= rrupts + to slave devices. + +allOf: + - $ref: /schemas/spmi/qcom,spmi-pmic-arb-common.yaml + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,kaanapali-spmi-pmic-arb + - const: qcom,glymur-spmi-pmic-arb + - enum: + - qcom,glymur-spmi-pmic-arb + + reg: + items: + - description: core registers + - description: tx-channel per virtual slave registers + - description: rx-channel (called observer) per virtual slave regist= ers + - description: channel to PMIC peripheral mapping registers + + reg-names: + items: + - const: core + - const: chnls + - const: obsrvr + - const: chnl_map + + ranges: true + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^spmi@[a-f0-9]+$": + type: object + $ref: /schemas/spmi/spmi.yaml + unevaluatedProperties: false + + properties: + reg: + items: + - description: configuration registers + - description: interrupt controller registers + - description: channel owner EE mapping registers + + reg-names: + items: + - const: cnfg + - const: intr + - const: chnl_owner + + interrupts: + maxItems: 1 + + interrupt-names: + const: periph_irq + + interrupt-controller: true + + '#interrupt-cells': + const: 4 + description: | + cell 1: slave ID for the requested interrupt (0-15) + cell 2: peripheral ID for requested interrupt (0-255) + cell 3: the requested peripheral interrupt (0-7) + cell 4: interrupt flags indicating level-sense information, + as defined in dt-bindings/interrupt-controller/irq.h + +required: + - compatible + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + arbiter@c400000 { + compatible =3D "qcom,glymur-spmi-pmic-arb"; + reg =3D <0x0 0xc400000 0x0 0x3000>, + <0x0 0xc900000 0x0 0x400000>, + <0x0 0xc4c0000 0x0 0x400000>, + <0x0 0xc403000 0x0 0x8000>; + reg-names =3D "core", "chnls", "obsrvr", "chnl_map"; + + qcom,ee =3D <0>; + qcom,channel =3D <0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + spmi@c426000 { + reg =3D <0x0 0xc426000 0x0 0x4000>, + <0x0 0xc8c0000 0x0 0x10000>, + <0x0 0xc42a000 0x0 0x8000>; + reg-names =3D "cnfg", "intr", "chnl_owner"; + + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + spmi@c437000 { + reg =3D <0x0 0xc437000 0x0 0x4000>, + <0x0 0xc8d0000 0x0 0x10000>, + <0x0 0xc43b000 0x0 0x8000>; + reg-names =3D "cnfg", "intr", "chnl_owner"; + + interrupts-extended =3D <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + }; + }; --=20 https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git