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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a802dce0ccsm19047295ad.32.2026.01.23.04.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 04:00:29 -0800 (PST) From: Varadarajan Narayanan To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Varadarajan Narayanan Subject: [PATCH v2 2/4] arm64: dts: qcom: ipq9574-rdp433: Reorganize DTS to introduce eMMC support Date: Fri, 23 Jan 2026 17:30:14 +0530 Message-Id: <20260123120016.3671812-3-varadarajan.narayanan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260123120016.3671812-1-varadarajan.narayanan@oss.qualcomm.com> References: <20260123120016.3671812-1-varadarajan.narayanan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: MV_oP3bcYg9qoViopihPlBVpoVEXcpAy X-Proofpoint-ORIG-GUID: MV_oP3bcYg9qoViopihPlBVpoVEXcpAy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIzMDA5OCBTYWx0ZWRfX4OkweIIz8GKu pwbjRfgg0Ilgj8aO83mL+MGsZaxYM75qckbK+PVpjmrSh8Sg3YZiWBERlSlpE9GEcn+l0lrxV6v 4bUZw5qpB9XELpGeUvhFf5n4hXGR7KdrA+ZkIaavO0qvchOuHOQmCzeeB4sU6PqQSvBSkh7BmMp 12aPYfWeUA0iUcfHhrasKIOP5DRrT9VvSC/E000YueIIidpbCLI9Wb2ZmxB2BdrH4Jzbs6NCXtN VNJoO7m7Iem+K3cwMiDtYAZUQkGRPwYgUfIHAeTvZKHJCpa1c/aTFEBDabGfxc0Afr1Q6gejR3e wQdZ4m1d/gVapS/SeYOezJ0MZaLPrQL4v8Y0xYuMarH2x6G9cK8ilasw2aPGQXA3NqD2E90xXYF yweHio5H2l9gXeejUTQ04dHmXU72g+SQ9C6Wr3GlASFuVZFGx44k4b6aJ6oOkfHxuFUUu+Dpbtx QqgACZApC0sVEfy4kyQ== X-Authority-Analysis: v=2.4 cv=faSgCkQF c=1 sm=1 tr=0 ts=697362e0 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=TP8aHUymSOKQWh1oKwsA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-23_02,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601230098 Content-Type: text/plain; charset="utf-8" The RDP433 has NAND and eMMC variants. Presently, only NAND variant is supported. To enable support for eMMC variant, move the common nodes from ipq9574-rdp433.dts to ipq9574-rdp433-common.dtsi. ipq9574-rdp433-common.dtsi will be included in rdp433 NAND and eMMC DT files. Signed-off-by: Varadarajan Narayanan Reviewed-by: Konrad Dybcio --- v2: Move common nodes into ipq9574-rdp433-common.dtsi Trim down ipq9574-rdp433.dts and #include rdp433-common.dtsi --- .../boot/dts/qcom/ipq9574-rdp433-common.dtsi | 121 ++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 116 +---------------- 2 files changed, 122 insertions(+), 115 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi b/arch/arm= 64/boot/dts/qcom/ipq9574-rdp433-common.dtsi new file mode 100644 index 000000000000..49c1b83bed10 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP433 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&pcie1_phy { + status =3D "okay"; +}; + +&pcie1 { + pinctrl-0 =3D <&pcie1_default>; + pinctrl-names =3D "default"; + + perst-gpios =3D <&tlmm 26 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 27 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&pcie2_phy { + status =3D "okay"; +}; + +&pcie2 { + pinctrl-0 =3D <&pcie2_default>; + pinctrl-names =3D "default"; + + perst-gpios =3D <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 30 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&pcie3_phy { + status =3D "okay"; +}; + +&pcie3 { + pinctrl-0 =3D <&pcie3_default>; + pinctrl-names =3D "default"; + + perst-gpios =3D <&tlmm 32 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 33 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&tlmm { + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins =3D "gpio25"; + function =3D "pcie1_clk"; + drive-strength =3D <6>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio26"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins =3D "gpio27"; + function =3D "pcie1_wake"; + drive-strength =3D <6>; + bias-pull-up; + }; + }; + + pcie2_default: pcie2-default-state { + clkreq-n-pins { + pins =3D "gpio28"; + function =3D "pcie2_clk"; + drive-strength =3D <6>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio29"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins =3D "gpio30"; + function =3D "pcie2_wake"; + drive-strength =3D <6>; + bias-pull-up; + }; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins =3D "gpio31"; + function =3D "pcie3_clk"; + drive-strength =3D <6>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins =3D "gpio33"; + function =3D "pcie3_wake"; + drive-strength =3D <6>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/= dts/qcom/ipq9574-rdp433.dts index 5a546a14998b..6794c9ac0b67 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -8,124 +8,10 @@ =20 /dts-v1/; =20 -#include #include "ipq9574-rdp-common.dtsi" +#include "ipq9574-rdp433-common.dtsi" =20 / { model =3D "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; compatible =3D "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; }; - -&pcie1_phy { - status =3D "okay"; -}; - -&pcie1 { - pinctrl-0 =3D <&pcie1_default>; - pinctrl-names =3D "default"; - - perst-gpios =3D <&tlmm 26 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 27 GPIO_ACTIVE_LOW>; - status =3D "okay"; -}; - -&pcie2_phy { - status =3D "okay"; -}; - -&pcie2 { - pinctrl-0 =3D <&pcie2_default>; - pinctrl-names =3D "default"; - - perst-gpios =3D <&tlmm 29 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 30 GPIO_ACTIVE_LOW>; - status =3D "okay"; -}; - -&pcie3_phy { - status =3D "okay"; -}; - -&pcie3 { - pinctrl-0 =3D <&pcie3_default>; - pinctrl-names =3D "default"; - - perst-gpios =3D <&tlmm 32 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 33 GPIO_ACTIVE_LOW>; - status =3D "okay"; -}; - -&tlmm { - - pcie1_default: pcie1-default-state { - clkreq-n-pins { - pins =3D "gpio25"; - function =3D "pcie1_clk"; - drive-strength =3D <6>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio26"; - function =3D "gpio"; - drive-strength =3D <8>; - bias-pull-down; - output-low; - }; - - wake-n-pins { - pins =3D "gpio27"; - function =3D "pcie1_wake"; - drive-strength =3D <6>; - bias-pull-up; - }; - }; - - pcie2_default: pcie2-default-state { - clkreq-n-pins { - pins =3D "gpio28"; - function =3D "pcie2_clk"; - drive-strength =3D <6>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio29"; - function =3D "gpio"; - drive-strength =3D <8>; - bias-pull-down; - output-low; - }; - - wake-n-pins { - pins =3D "gpio30"; - function =3D "pcie2_wake"; - drive-strength =3D <6>; - bias-pull-up; - }; - }; - - pcie3_default: pcie3-default-state { - clkreq-n-pins { - pins =3D "gpio31"; - function =3D "pcie3_clk"; - drive-strength =3D <6>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio32"; - function =3D "gpio"; - drive-strength =3D <8>; - bias-pull-up; - output-low; - }; - - wake-n-pins { - pins =3D "gpio33"; - function =3D "pcie3_wake"; - drive-strength =3D <6>; - bias-pull-up; - }; - }; -}; --=20 2.34.1