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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 11:12:52.2367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ecbf723e-e22b-47c1-842e-08de5a7059cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7697 Content-Type: text/plain; charset="utf-8" Add generic SoundWire clock initialization sequence to support different SoundWire bus clock frequencies for ACP6.3/7.0/7.1/7.2 platforms and remove hard coding initializations for 12Mhz bus clock frequency. Signed-off-by: Vijendar Mukunda Reviewed-by: Mario Limonciello (AMD) --- drivers/soundwire/amd_manager.c | 56 ++++++++++++++++++++++++++++----- drivers/soundwire/amd_manager.h | 4 --- 2 files changed, 49 insertions(+), 11 deletions(-) diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manage= r.c index 5fd311ee4107..ee3c37a5a48b 100644 --- a/drivers/soundwire/amd_manager.c +++ b/drivers/soundwire/amd_manager.c @@ -27,6 +27,49 @@ =20 #define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus) =20 +static int amd_sdw_clk_init_ctrl(struct amd_sdw_manager *amd_manager) +{ + struct sdw_bus *bus =3D &amd_manager->bus; + struct sdw_master_prop *prop =3D &bus->prop; + u32 val; + int divider; + + dev_dbg(amd_manager->dev, "mclk %d max %d row %d col %d frame_rate:%d\n", + prop->mclk_freq, prop->max_clk_freq, prop->default_row, + prop->default_col, prop->default_frame_rate); + + if (!prop->default_frame_rate || !prop->default_row) { + dev_err(amd_manager->dev, "Default frame_rate %d or row %d is invalid\n", + prop->default_frame_rate, prop->default_row); + return -EINVAL; + } + + /* Set clock divider */ + dev_dbg(amd_manager->dev, "bus params curr_dr_freq: %d\n", + bus->params.curr_dr_freq); + divider =3D (prop->mclk_freq / bus->params.curr_dr_freq); + + writel(divider, amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL); + val =3D readl(amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL); + dev_dbg(amd_manager->dev, "ACP_SW_CLK_FREQUENCY_CTRL:0x%x\n", val); + + /* Set frame shape base on the actual bus frequency. */ + prop->default_col =3D bus->params.curr_dr_freq / + prop->default_frame_rate / prop->default_row; + + dev_dbg(amd_manager->dev, "default_frame_rate:%d default_row: %d default_= col: %d\n", + prop->default_frame_rate, prop->default_row, prop->default_col); + amd_manager->cols_index =3D sdw_find_col_index(prop->default_col); + amd_manager->rows_index =3D sdw_find_row_index(prop->default_row); + bus->params.col =3D prop->default_col; + bus->params.row =3D prop->default_row; + dev_dbg(amd_manager->dev, "rows_index: %d cols_index: %d\n", + amd_manager->rows_index, amd_manager->cols_index); + dev_dbg(amd_manager->dev, "params.col:0x%x params.row:0x%x\n", + bus->params.col, bus->params.row); + return 0; +} + static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager) { u32 val; @@ -961,6 +1004,9 @@ int amd_sdw_manager_start(struct amd_sdw_manager *amd_= manager) =20 prop =3D &amd_manager->bus.prop; if (!prop->hw_disabled) { + ret =3D amd_sdw_clk_init_ctrl(amd_manager); + if (ret) + return ret; ret =3D amd_init_sdw_manager(amd_manager); if (ret) return ret; @@ -985,7 +1031,6 @@ static int amd_sdw_manager_probe(struct platform_devic= e *pdev) struct resource *res; struct device *dev =3D &pdev->dev; struct sdw_master_prop *prop; - struct sdw_bus_params *params; struct amd_sdw_manager *amd_manager; int ret; =20 @@ -1049,14 +1094,8 @@ static int amd_sdw_manager_probe(struct platform_dev= ice *pdev) return -EINVAL; } =20 - params =3D &amd_manager->bus.params; - - params->col =3D AMD_SDW_DEFAULT_COLUMNS; - params->row =3D AMD_SDW_DEFAULT_ROWS; prop =3D &amd_manager->bus.prop; - prop->clk_freq =3D &amd_sdw_freq_tbl[0]; prop->mclk_freq =3D AMD_SDW_BUS_BASE_FREQ; - prop->max_clk_freq =3D AMD_SDW_DEFAULT_CLK_FREQ; =20 ret =3D sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode); if (ret) { @@ -1348,6 +1387,9 @@ static int __maybe_unused amd_resume_runtime(struct d= evice *dev) } } sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); + ret =3D amd_sdw_clk_init_ctrl(amd_manager); + if (ret) + return ret; amd_init_sdw_manager(amd_manager); amd_enable_sdw_interrupts(amd_manager); ret =3D amd_enable_sdw_manager(amd_manager); diff --git a/drivers/soundwire/amd_manager.h b/drivers/soundwire/amd_manage= r.h index 6cc916b0c820..88cf8a426a0c 100644 --- a/drivers/soundwire/amd_manager.h +++ b/drivers/soundwire/amd_manager.h @@ -203,10 +203,6 @@ #define AMD_SDW_DEVICE_STATE_D3 3 #define ACP_PME_EN 0x0001400 =20 -static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] =3D { - AMD_SDW_DEFAULT_CLK_FREQ, -}; - struct sdw_manager_dp_reg { u32 frame_fmt_reg; u32 sample_int_reg; --=20 2.45.2