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Fri, 23 Jan 2026 01:54:13 -0800 From: "Sheetal ." To: Mark Brown CC: Sander Vanheule , Greg Kroah-Hartman , "Rafael J . Wysocki" , Danilo Krummrich , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , "Thierry Reding" , Jonathan Hunter , Mohan kumar , , , , Sheetal Subject: [RFC PATCH v3 1/4] ASoC: tegra: Add AHUB writeable_reg for RX holes Date: Fri, 23 Jan 2026 15:23:43 +0530 Message-ID: <20260123095346.1258556-2-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260123095346.1258556-1-sheetal@nvidia.com> References: <20260123095346.1258556-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A3:EE_|CH1PR12MB9717:EE_ X-MS-Office365-Filtering-Correlation-Id: a163dc45-22a8-49cc-5e74-08de5a65689b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Myep4L7opyVTIUemNXT/q+4xaxMB8fQi5b/yni5LzXejxQOI4b1L0DDNmyWx?= =?us-ascii?Q?IpQF2FBbLyvi3MsfQkpn2HM/CX6QUNS7QxnvqL0/zA66IUarkiKa48vIlINB?= =?us-ascii?Q?ylay/Xr8PVlqz02tap6tdwL5dMuMHnCEUtbRazH+UZbXIAjpBY+bFCGS9MUc?= =?us-ascii?Q?oFeeoSV4KiWASS/5B0Ptbxlibu2odQZogeWY7WH+7eKmQA+mpzfig21TXH5U?= =?us-ascii?Q?mjlHEKUorjCvuMsQn6Atuy3CTSOzfOobt8lXEc21Qh1fNl1bVP6B2j9yS1N0?= =?us-ascii?Q?cgQM35k/jEkIs/rIwMuAa8/5fRQA3zjE0bwWsB4fVRfu2LnOjBUlABhHAmLD?= =?us-ascii?Q?A8SM4rIesRMeLlST7JWUeXOyLnLRxZ/UCqwDV1r3DTKJdFWSgb637dcrmX+8?= =?us-ascii?Q?syn0P8MGLHvzJ7ryfoQ3tQeWDkhEqNX6vXoYG/eYVelL4/hohmyhUNap9SjV?= =?us-ascii?Q?1b+1nc2ElaRZ2KGtrAaNJ9xLo+KNjPVxf+2WeWL/oxEN/8Dw3wmpsS3wXzJd?= =?us-ascii?Q?OzcJuQnhTgE1viGN4qKEoMfbH9Tej1AF6w/cNdBgnp4uL9FcVs4Dy5tA6Or8?= =?us-ascii?Q?TyXtjaZzZdb0mV4OPpSYbMfoIBbj4AHQomTlSwDtkohQD6S+JZdfx5q2VQSN?= =?us-ascii?Q?YtAhcbsbt1HFdEnujZ6dSo54iWZGlm0mMIWm3gezYGhwpwuhZH8BQLa5MNgF?= =?us-ascii?Q?4V1e6HC7imA8EZaAuazU+wOGrx87mSLbL8L2HtTMUr9MkJsrxk2a8G1hYm0a?= =?us-ascii?Q?gczgsHIOT9ZSFqwG6+/+VzqWa7VHIgzruZQsyGxdcziQ9lKewIyqPdpR6K4L?= =?us-ascii?Q?CSaoQP3Q5FTVdwltgDoWkdpEFR3KYx1McEq549YO98lmcx8RXdAxLH2kZ+Gr?= =?us-ascii?Q?VLxj4H1w3wQWFg6DDjfwpzoXMomYY0XNJkp+yoSEvSdf/vJ0qByElOV/te7z?= =?us-ascii?Q?tPYUSab/wep9guIODCybSzH82aGEi+2STKO30xV1iAZuCh5yyqUni0k2Kxx9?= =?us-ascii?Q?qrQAvi0xemW0WynYDvcinsQBvNkImC8ysc3PwOipeMgbgnf1+4dIZo2sGz/R?= =?us-ascii?Q?X1BFFrRXDbeeZJudprCMePXCOerF/7bvJP1LZYyHRO6goERd+r+Dzjjxb6Ap?= =?us-ascii?Q?v1rvaF77dnk4/LZGL7FaoRwjyK16+jmz6zD1yHNy86CuqGPLp6EhTd/CKwIZ?= =?us-ascii?Q?0yIOiEkEyDbJyXXyjhiKqfpYCjl8psgPpApb82Vhj8I5Fq+YcdNZaDKfdbvz?= =?us-ascii?Q?lxt73Ocmc0RtwiGL1VaspdRYhly0NvOVh47+YeuZr/o+DD5f97FwyRDoNZZ1?= =?us-ascii?Q?pioQ2ZvjcDkcNMgAqeaSsBaA7U4WUB7ZmDe13boVi2eKPdC5UZn3PO43mKvl?= =?us-ascii?Q?+w/Lax2Kf6bhBZB9PQ8egN8D8OIzX927Pik2NklmLg2O3OcTvpb4l9Pmfr/M?= =?us-ascii?Q?bNg4w/EjePqMX3C8OeD3BvxGI+l6C9pqRjpL8ifahI4D7k7xsI0vkHrRYZxX?= =?us-ascii?Q?TbsqKfnAbwRFNJmqyJTfQ+3r3gESICzkFAdsOmNXgTmC+GWSymj4JAxLAE6b?= =?us-ascii?Q?JmSLldO5LLeFKOHeHpY81+JYjJ0wPm7T+zA2Rd0AwkB2pj0TVwMs6WmPef7k?= =?us-ascii?Q?QUYrIXLOUG4iXIGYLa6AQIA4P472573ruF491ausNw34iC1DYcsegbNgLPmP?= =?us-ascii?Q?qcVjWQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 09:54:32.4210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a163dc45-22a8-49cc-5e74-08de5a65689b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9717 Content-Type: text/plain; charset="utf-8" From: Sheetal Add writeable_reg callbacks for Tegra210/186 AHUB RX registers so the flat cache only treats valid RX locations as writable, avoiding holes in the register map. Fixes: 16e1bcc2caf4 ("ASoC: tegra: Add Tegra210 based AHUB driver") Signed-off-by: Sheetal Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- sound/soc/tegra/tegra210_ahub.c | 57 +++++++++++++++++++++++++++++++++ sound/soc/tegra/tegra210_ahub.h | 30 +++++++++++++++++ 2 files changed, 87 insertions(+) diff --git a/sound/soc/tegra/tegra210_ahub.c b/sound/soc/tegra/tegra210_ahu= b.c index e795907a3963..fc5892056f83 100644 --- a/sound/soc/tegra/tegra210_ahub.c +++ b/sound/soc/tegra/tegra210_ahub.c @@ -2049,6 +2049,61 @@ static const struct snd_soc_component_driver tegra26= 4_ahub_component =3D { .num_dapm_routes =3D ARRAY_SIZE(tegra264_ahub_routes), }; =20 +static bool tegra210_ahub_wr_reg(struct device *dev, unsigned int reg) +{ + int part; + + if (reg % TEGRA210_XBAR_RX_STRIDE) + return false; + + for (part =3D 0; part < TEGRA210_XBAR_UPDATE_MAX_REG; part++) { + switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { + case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA210_AXBAR_PART_0_ADMAIF= _RX10_0: + case TEGRA210_AXBAR_PART_0_I2S1_RX1_0 ... TEGRA210_AXBAR_PART_0_I2S5_RX1= _0: + case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1= _0: + case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1= _RX10_0: + case TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 ... TEGRA210_AXBAR_PART_0_SPDIF1= _RX2_0: + case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1= _0: + case TEGRA210_AXBAR_PART_0_OPE1_RX1_0 ... TEGRA210_AXBAR_PART_0_OPE2_RX1= _0: + case TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0: + case TEGRA210_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA210_AXBAR_PART_0_MVC2_RX1= _0: + case TEGRA210_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA210_AXBAR_PART_0_ADX2_RX1= _0: + return true; + default: + break; + } + } + + return false; +} + +static bool tegra186_ahub_wr_reg(struct device *dev, unsigned int reg) +{ + int part; + + if (reg % TEGRA210_XBAR_RX_STRIDE) + return false; + + for (part =3D 0; part < TEGRA186_XBAR_UPDATE_MAX_REG; part++) { + switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { + case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA186_AXBAR_PART_0_I2S6_R= X1_0: + case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1= _0: + case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1= _RX10_0: + case TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 ... TEGRA186_AXBAR_PART_0_DSPK2_R= X1_0: + case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1= _0: + case TEGRA210_AXBAR_PART_0_OPE1_RX1_0: + case TEGRA186_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA186_AXBAR_PART_0_MVC2_RX1= _0: + case TEGRA186_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA186_AXBAR_PART_0_AMX3_RX4= _0: + case TEGRA210_AXBAR_PART_0_ADX1_RX1_0 ... TEGRA186_AXBAR_PART_0_ASRC1_RX= 7_0: + return true; + default: + break; + } + } + + return false; +} + static bool tegra264_ahub_wr_reg(struct device *dev, unsigned int reg) { int part; @@ -2076,6 +2131,7 @@ static const struct regmap_config tegra210_ahub_regma= p_config =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, + .writeable_reg =3D tegra210_ahub_wr_reg, .max_register =3D TEGRA210_MAX_REGISTER_ADDR, .cache_type =3D REGCACHE_FLAT, }; @@ -2084,6 +2140,7 @@ static const struct regmap_config tegra186_ahub_regma= p_config =3D { .reg_bits =3D 32, .val_bits =3D 32, .reg_stride =3D 4, + .writeable_reg =3D tegra186_ahub_wr_reg, .max_register =3D TEGRA186_MAX_REGISTER_ADDR, .cache_type =3D REGCACHE_FLAT, }; diff --git a/sound/soc/tegra/tegra210_ahub.h b/sound/soc/tegra/tegra210_ahu= b.h index f355b2cfd19b..acbe640dd3b5 100644 --- a/sound/soc/tegra/tegra210_ahub.h +++ b/sound/soc/tegra/tegra210_ahub.h @@ -68,6 +68,36 @@ #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \ (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1))) =20 +/* AXBAR register offsets */ +#define TEGRA186_AXBAR_PART_0_AMX1_RX1_0 0x120 +#define TEGRA186_AXBAR_PART_0_AMX3_RX4_0 0x14c +#define TEGRA186_AXBAR_PART_0_ASRC1_RX7_0 0x1a8 +#define TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 0xc0 +#define TEGRA186_AXBAR_PART_0_DSPK2_RX1_0 0xc4 +#define TEGRA186_AXBAR_PART_0_I2S6_RX1_0 0x54 +#define TEGRA186_AXBAR_PART_0_MVC1_RX1_0 0x110 +#define TEGRA186_AXBAR_PART_0_MVC2_RX1_0 0x114 +#define TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0 0x24 +#define TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 0x0 +#define TEGRA210_AXBAR_PART_0_ADX1_RX1_0 0x160 +#define TEGRA210_AXBAR_PART_0_ADX2_RX1_0 0x164 +#define TEGRA210_AXBAR_PART_0_AFC1_RX1_0 0xd0 +#define TEGRA210_AXBAR_PART_0_AFC6_RX1_0 0xe4 +#define TEGRA210_AXBAR_PART_0_AMX1_RX1_0 0x140 +#define TEGRA210_AXBAR_PART_0_I2S1_RX1_0 0x40 +#define TEGRA210_AXBAR_PART_0_I2S5_RX1_0 0x50 +#define TEGRA210_AXBAR_PART_0_MIXER1_RX10_0 0xa4 +#define TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 0x80 +#define TEGRA210_AXBAR_PART_0_MVC1_RX1_0 0x120 +#define TEGRA210_AXBAR_PART_0_MVC2_RX1_0 0x124 +#define TEGRA210_AXBAR_PART_0_OPE1_RX1_0 0x100 +#define TEGRA210_AXBAR_PART_0_OPE2_RX1_0 0x104 +#define TEGRA210_AXBAR_PART_0_SFC1_RX1_0 0x60 +#define TEGRA210_AXBAR_PART_0_SFC4_RX1_0 0x6c +#define TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 0xc0 +#define TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0 0xc4 +#define TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0 0x110 + #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id)) =20 #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32) --=20 2.34.1 From nobody Sat Feb 7 10:07:58 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012049.outbound.protection.outlook.com [40.107.200.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AD6737E308; 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To: Mark Brown CC: Sander Vanheule , Greg Kroah-Hartman , "Rafael J . Wysocki" , Danilo Krummrich , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , "Thierry Reding" , Jonathan Hunter , Mohan kumar , , , , Sheetal Subject: [RFC PATCH v3 2/4] regmap: Add reg_default_cb callback for flat cache defaults Date: Fri, 23 Jan 2026 15:23:44 +0530 Message-ID: <20260123095346.1258556-3-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260123095346.1258556-1-sheetal@nvidia.com> References: <20260123095346.1258556-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|CH3PR12MB7689:EE_ X-MS-Office365-Filtering-Correlation-Id: e1d925ae-709e-4ece-0080-08de5a656b77 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?JreJGHu6i8uPjYWlxfurwW5V8YkmQyewaRuY7Hs+V2kfdmXD2jTDCedKnw0T?= =?us-ascii?Q?7Qn1npZpCgu0L5YfnNo8GCoy4AMiSURPcaiz2C76wztamyqhqsRvQizIUe3v?= =?us-ascii?Q?HnNIpXxuNAocvEnct7RccpWXJX0uxb4CCOW5zH5G/4dYRVDVnzH4od6LSU1p?= =?us-ascii?Q?7tTmcrnvrHPykyEIzCDsOfkZHaMLT4TdAHpVcnLTEC6ZI97kVVS+dXQ8h2RS?= =?us-ascii?Q?PvBzFpUuMqkyKaoK/wl+VH1TipSkl2FTBxM79b5hCacxLlMDbs3lR9rIyb0a?= =?us-ascii?Q?On0rKdh0k4h3d6UpCNShNTQCBu3jgvu1HovqPoSoYDrGZW8oWpq+f8/i4Gzz?= =?us-ascii?Q?HXfrc0fdhqo7s+cqI6BtELI++hy8TpX66y75HE1U8mWYtXqV9nH9yKOD0TRS?= =?us-ascii?Q?k4N5w40nJpVgTwSut7UEEOJjfBb53Wj+MskljlHx09K0/Je1wOss3hr/K5gK?= =?us-ascii?Q?tWkDrVaTd4R1h2168zyk2NdMkRtVsiUrbpidejBzxaXouNGR4qPdUfnDdVb8?= =?us-ascii?Q?cXYcmih7RQK3/fQ6F878YzYs4hAVZzjVwAkatbBK1Gckzh7Tqi5uTossq6SN?= =?us-ascii?Q?48n4BwoxXMwxbt/Jc+4dDRCzCDLtttvZGQpEjFwAZL+tjbhu/2MYAs4rpL66?= =?us-ascii?Q?9e7BQBh+BFXCwmdZgTD/tQLFxwOqPsZNJYHnWrxECT+QlKEfpqHierV2922J?= =?us-ascii?Q?ERVnEQJDTkopCRiIvQ7qHB9/BpP5PVQzdRfhMUxXc6kRS4fXFEe7/XePeyvv?= =?us-ascii?Q?e6c1ByTsh8veSUw0mcyodTKXi//FbuZk9oITsdIOOXwgW4IsooSrjvNiDVH0?= =?us-ascii?Q?7+1CqBwCsM2AzJHDBmdaW67B+WhQlkAFS7zfE3J8N6oI2a9EddOJjGsryqfL?= =?us-ascii?Q?yfYYmyoRjUiVB3xvWHaU52wzRkwJMCmzKUfl6MCM01AaG/NdZRxskPxUnp3m?= =?us-ascii?Q?LrOi7S4uEr+qtBNuBzc2dn8YIIY4cVpiwwISvpKnnEImGEd9hjEeeYj2yBNq?= =?us-ascii?Q?vDiHSoQuAyK/iUtjfwaHP34P8tRCD7rTbJd8YrHYoLyLBRa0ZWFkuCFe8CKE?= =?us-ascii?Q?fFTtrc9eGTopTyKD/RagduOB6h1imWFE0+kce1q1D69FdPoVo+EiQfxkudGA?= =?us-ascii?Q?ZrFv8/CU/QySLPBhwAH4REixTs1ZxNWD0OsTuciov4/K6ntD6Q3+6l6UujW4?= =?us-ascii?Q?NXpv6a0yBGlife8Iyshn8AyGOiKTLhnE8Ring/6CmIl2zsQXGRDE0j++S0Rn?= =?us-ascii?Q?qcChxmSsJbaZ/f3a1zajlIBiIwgoS390vSfBOhcqSzZn7QlIaeSYgCecjaeO?= =?us-ascii?Q?schwquSHarPPuwgc00t2/ZCXoMOjVIOiA85Qd6Gv8x+W7jVmB6q8zUUAdN8Y?= =?us-ascii?Q?haGpr6rVSGvxLuKq7Va5E5LwR508sZkoTXsJKi/CsAbC+PN4BqanecRc83qW?= =?us-ascii?Q?W78pE2IjzvsA9yMzGiqMds65nhE91xYIJeCqtTbECEargbLR5lA3rpAdVWff?= =?us-ascii?Q?9edRiDRYH3ahv1bSmbaatP+kAxBm1zW/VoM2XUAAcZn/NgbMT2ZnWoDs51NO?= =?us-ascii?Q?V2IdJIw0PufluY9EHXzrpa1VdMlW6jgFeGy2oM/vygc30uYrVfl4L+0monx+?= =?us-ascii?Q?9NgVi+tWdmAWvc/d24j8Sp1PJZweZQZeg0OcK2lc2OTuqWPX2X5DC1Ncx5qT?= =?us-ascii?Q?GcHoPg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 09:54:37.3039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1d925ae-709e-4ece-0080-08de5a656b77 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7689 Content-Type: text/plain; charset="utf-8" From: Sheetal Commit e062bdfdd6ad ("regmap: warn users about uninitialized flat cache") warns when REGCACHE_FLAT is used without full defaults. This causes false positives on hardware where many registers reset to zero but are not listed in reg_defaults, forcing drivers to maintain large tables just to silence the warning. Add a reg_default_cb() hook so drivers can supply defaults for registers not present in reg_defaults when populating REGCACHE_FLAT. This keeps the warning quiet for known zero-reset registers without bloating tables. Provide a generic regmap_default_zero_cb() helper for drivers that need zero defaults. The hook is only used for REGCACHE_FLAT; the core does not check readable/writeable access, so drivers must provide readable_reg/ writeable_reg callbacks and handle holes in the register map. Signed-off-by: Sheetal Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/base/regmap/internal.h | 3 +++ drivers/base/regmap/regcache-flat.c | 19 +++++++++++++++++++ drivers/base/regmap/regcache.c | 3 ++- drivers/base/regmap/regmap.c | 2 ++ include/linux/regmap.h | 14 ++++++++++++++ 5 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index 1477329410ec..5bf993165438 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -117,6 +117,9 @@ struct regmap { void *val_buf, size_t val_size); int (*write)(void *context, const void *data, size_t count); =20 + int (*reg_default_cb)(struct device *dev, unsigned int reg, + unsigned int *val); + unsigned long read_flag_mask; unsigned long write_flag_mask; =20 diff --git a/drivers/base/regmap/regcache-flat.c b/drivers/base/regmap/regc= ache-flat.c index 53cc59c84e2f..c924817e19b1 100644 --- a/drivers/base/regmap/regcache-flat.c +++ b/drivers/base/regmap/regcache-flat.c @@ -79,6 +79,25 @@ static int regcache_flat_populate(struct regmap *map) __set_bit(index, cache->valid); } =20 + if (map->reg_default_cb) { + dev_dbg(map->dev, + "Populating regcache_flat using reg_default_cb callback\n"); + + for (i =3D 0; i <=3D map->max_register; i +=3D map->reg_stride) { + unsigned int index =3D regcache_flat_get_index(map, i); + unsigned int value; + + if (test_bit(index, cache->valid)) + continue; + + if (map->reg_default_cb(map->dev, i, &value)) + continue; + + cache->data[index] =3D value; + __set_bit(index, cache->valid); + } + } + return 0; } =20 diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 319c342bf5a0..31bdbf37dbed 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -223,7 +223,8 @@ int regcache_init(struct regmap *map, const struct regm= ap_config *config) goto err_free; } =20 - if (map->num_reg_defaults && map->cache_ops->populate) { + if (map->cache_ops->populate && + (map->num_reg_defaults || map->reg_default_cb)) { dev_dbg(map->dev, "Populating %s cache\n", map->cache_ops->name); map->lock(map->lock_arg); ret =3D map->cache_ops->populate(map); diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index ce9be3989a21..57c5551044ed 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -811,6 +811,7 @@ struct regmap *__regmap_init(struct device *dev, map->precious_reg =3D config->precious_reg; map->writeable_noinc_reg =3D config->writeable_noinc_reg; map->readable_noinc_reg =3D config->readable_noinc_reg; + map->reg_default_cb =3D config->reg_default_cb; map->cache_type =3D config->cache_type; =20 spin_lock_init(&map->async_lock); @@ -1433,6 +1434,7 @@ int regmap_reinit_cache(struct regmap *map, const str= uct regmap_config *config) map->precious_reg =3D config->precious_reg; map->writeable_noinc_reg =3D config->writeable_noinc_reg; map->readable_noinc_reg =3D config->readable_noinc_reg; + map->reg_default_cb =3D config->reg_default_cb; map->cache_type =3D config->cache_type; =20 ret =3D regmap_set_name(map, config); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index b0b9be750d93..51940eeff872 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -359,6 +359,10 @@ typedef void (*regmap_unlock)(void *); * @reg_defaults: Power on reset values for registers (for use with * register cache support). * @num_reg_defaults: Number of elements in reg_defaults. + * @reg_default_cb: Optional callback to return default values for registe= rs + * not listed in reg_defaults. This is only used for + * REGCACHE_FLAT population; drivers must ensure the read= able_reg/ + * writeable_reg callbacks are defined to handle holes. * * @read_flag_mask: Mask to be set in the top bytes of the register when d= oing * a read. @@ -449,6 +453,8 @@ struct regmap_config { const struct regmap_access_table *rd_noinc_table; const struct reg_default *reg_defaults; unsigned int num_reg_defaults; + int (*reg_default_cb)(struct device *dev, unsigned int reg, + unsigned int *def); enum regcache_type cache_type; const void *reg_defaults_raw; unsigned int num_reg_defaults_raw; @@ -1349,6 +1355,14 @@ static inline int regmap_write_bits(struct regmap *m= ap, unsigned int reg, return regmap_update_bits_base(map, reg, mask, val, NULL, false, true); } =20 +static inline int regmap_default_zero_cb(struct device *dev, + unsigned int reg, + unsigned int *def) +{ + *def =3D 0; + return 0; +} + int regmap_get_val_bytes(struct regmap *map); int regmap_get_max_register(struct regmap *map); int regmap_get_reg_stride(struct regmap *map); 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Fri, 23 Jan 2026 01:54:22 -0800 From: "Sheetal ." To: Mark Brown CC: Sander Vanheule , Greg Kroah-Hartman , "Rafael J . Wysocki" , Danilo Krummrich , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , "Thierry Reding" , Jonathan Hunter , Mohan kumar , , , , Sheetal Subject: [RFC PATCH v3 3/4] ASoC: tegra: set reg_default_cb callback Date: Fri, 23 Jan 2026 15:23:45 +0530 Message-ID: <20260123095346.1258556-4-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260123095346.1258556-1-sheetal@nvidia.com> References: <20260123095346.1258556-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|IA0PR12MB8206:EE_ X-MS-Office365-Filtering-Correlation-Id: a146d0fd-0963-4bf2-9153-08de5a656cf3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?dmfm38JqU8GICIVZPuqZy/IXr/9S4L+dtcUzdJxYclDNtlL7vQp/CdbMQTHY?= =?us-ascii?Q?qr3kgzNntB9JbF2A/0q58it1OkQFmGi1VEY+JtxoRKMC7+DR2wHpfuQWJRSZ?= =?us-ascii?Q?dMT6/qULLdOcRq+hiZHrIkjD0M1/a28GaZpDVe7VVYosTHVzbPz5uYOf44Bn?= =?us-ascii?Q?TVdpJS1o8XFljCWbDPo1JXtG3DAr2BFz6N+A4mUhMZHKmRbncUK3qsuc2J3A?= =?us-ascii?Q?opu8thN0fERit23oiM45ngw/exNK/RGHpoNvEoiZFW9PF7VMIfLfiZERhB+R?= =?us-ascii?Q?ah+TXTB9ecSExvWB9yQIgDAzK1USKpJxBiGeygKK4yFPNvxhpLCBP6KjY3c1?= =?us-ascii?Q?y1sigJBRUZ8Aq3lV2xMgsAWhuAJEZgdOQ5bOK+7gqWjnzQvAUjvVnKG8x+ea?= =?us-ascii?Q?U6YZazMi18SpPPUI7PIP1MEuuDYB5NkDGls8ZXtdm2mPD0tGh22CTWWUlmdf?= =?us-ascii?Q?fBmFnjOJ/SWg+x78bWBu7jETY1Q+WsLMTYJ6hhPf02en2dZedEtX9HWrhvYb?= =?us-ascii?Q?AzcgrcEbXGYdVqPtd2PFU4uC9vDWuiUxbn/JaAKZxnPF9RdPnnuHlQiMed/P?= =?us-ascii?Q?KGxaTOSFu9Yb7oduy6Q30BQoGl6roR1b8w/GE4Bl/OtYDj3I4GQ4BxEwASo8?= =?us-ascii?Q?pX77tvi/gSIw3gy0DJV86uauqdMsK75YaRegumj1txa6d/OFWTi86OdZVRYA?= =?us-ascii?Q?jiX0lISXM4KtnLZGN12/5ZFnT7RDptckE7Y8+lW3LA6UC+musFCHEcswEOZ9?= =?us-ascii?Q?57rTABRk5Q0gtEDq+W6wxgk15pqsY/NsBjWjHxTJFEygtCySBzMrOK9hTUfn?= =?us-ascii?Q?fOdV/5I6JwrRdbNaNYsayjWsN2yJ0OC1EOfN24OxoE+XI2RzslQP+aWiaHo+?= =?us-ascii?Q?T5C1hR3mvs1tGt/1Ph+yvnvUT545NRNKTe2vmLD0+Xvkf0EuerOmZLZK35n4?= =?us-ascii?Q?nYkze6kYtJoe8ne47UVctFKwyQ1tMcjZ+1wJdauuZXwv6PIG5TIGRLrlhFRg?= =?us-ascii?Q?cHbDxfDWFS0sSW1GafexlMqjtcWqLFwl8Gdwna/41wxotJeBcx8eOW/gSjNC?= =?us-ascii?Q?YXB1Xjieht3yVJwaOXLyFspcF1PMobIDwCgmtzqNGq2hhYcXbCnjBW0DdUSx?= =?us-ascii?Q?QYye2cF+x/V3VDIVyjx+E+BqAqXJBWZDrPf0hXCniKF9wW0q9AZZQZhQfqdP?= =?us-ascii?Q?/Od0VzQhmHRovpEz9MEX3q5R8CKvU3J232wOYCRuEpMQG36ysd7wq+Wkls19?= =?us-ascii?Q?MMwVKwzTkLMXcteN+n4MId3RwSMJb6yPMsq2mjDrZs0ydHje6QO6I/jmE7z1?= =?us-ascii?Q?Tv8uEzOEQ7OtrMRw4txb8KiLjeznzutn5T/7vtzN8xnwvygpiMw2TpnqvMCf?= =?us-ascii?Q?nHW5JluK/VkPTPW4iS8VzrhRjw5Vdb05JFm/X+G8u/FaI3yeE1B7eN58TSSx?= =?us-ascii?Q?TWBzqgtCF7gmB0TJNaVSUb/jksE5AlAMjJq+nRvx2umELIQxuNlqyBC3oifj?= =?us-ascii?Q?Qzdb/WB3GQNsSQK937zosJm7INWwKtSrZgCWtwwCNFKupxdeY9xMyPvFvvhD?= =?us-ascii?Q?ujnBvcyx5Rzy+t4uoiRNMIExbJuw1fDoXNlKKfz1FRYfYh15xEDDQvgE3Fs3?= =?us-ascii?Q?b6DJGhkgixmvlxxO3Q9HmemRe42gWoJ0zx+XGk5ya2qQe3OnvtL6SB021UCf?= =?us-ascii?Q?Zmirqw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 09:54:39.7473 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a146d0fd-0963-4bf2-9153-08de5a656cf3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8206 Content-Type: text/plain; charset="utf-8" From: Sheetal Set reg_default_cb so REGCACHE_FLAT can supply zero defaults without large reg_defaults tables, simplifying cache initialization for zero-reset registers. Signed-off-by: Sheetal Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- sound/soc/tegra/tegra186_asrc.c | 1 + sound/soc/tegra/tegra186_dspk.c | 1 + sound/soc/tegra/tegra210_admaif.c | 3 +++ sound/soc/tegra/tegra210_adx.c | 2 ++ sound/soc/tegra/tegra210_ahub.c | 3 +++ sound/soc/tegra/tegra210_amx.c | 3 +++ sound/soc/tegra/tegra210_dmic.c | 1 + sound/soc/tegra/tegra210_i2s.c | 2 ++ sound/soc/tegra/tegra210_mbdrc.c | 1 + sound/soc/tegra/tegra210_mixer.c | 1 + sound/soc/tegra/tegra210_mvc.c | 1 + sound/soc/tegra/tegra210_ope.c | 1 + sound/soc/tegra/tegra210_peq.c | 1 + sound/soc/tegra/tegra210_sfc.c | 1 + 14 files changed, 22 insertions(+) diff --git a/sound/soc/tegra/tegra186_asrc.c b/sound/soc/tegra/tegra186_asr= c.c index 2c0220e14a57..d2a5ec7c54cc 100644 --- a/sound/soc/tegra/tegra186_asrc.c +++ b/sound/soc/tegra/tegra186_asrc.c @@ -950,6 +950,7 @@ static const struct regmap_config tegra186_asrc_regmap_= config =3D { .volatile_reg =3D tegra186_asrc_volatile_reg, .reg_defaults =3D tegra186_asrc_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra186_asrc_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra186_dspk.c b/sound/soc/tegra/tegra186_dsp= k.c index a762150db802..8816e4967331 100644 --- a/sound/soc/tegra/tegra186_dspk.c +++ b/sound/soc/tegra/tegra186_dspk.c @@ -467,6 +467,7 @@ static const struct regmap_config tegra186_dspk_regmap = =3D { .volatile_reg =3D tegra186_dspk_volatile_reg, .reg_defaults =3D tegra186_dspk_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra186_dspk_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_admaif.c b/sound/soc/tegra/tegra210_a= dmaif.c index f9f6040c4e34..0976779d29f2 100644 --- a/sound/soc/tegra/tegra210_admaif.c +++ b/sound/soc/tegra/tegra210_admaif.c @@ -241,6 +241,7 @@ static const struct regmap_config tegra210_admaif_regma= p_config =3D { .volatile_reg =3D tegra_admaif_volatile_reg, .reg_defaults =3D tegra210_admaif_reg_defaults, .num_reg_defaults =3D TEGRA210_ADMAIF_CHANNEL_COUNT * 6 + 1, + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -254,6 +255,7 @@ static const struct regmap_config tegra186_admaif_regma= p_config =3D { .volatile_reg =3D tegra_admaif_volatile_reg, .reg_defaults =3D tegra186_admaif_reg_defaults, .num_reg_defaults =3D TEGRA186_ADMAIF_CHANNEL_COUNT * 6 + 1, + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -267,6 +269,7 @@ static const struct regmap_config tegra264_admaif_regma= p_config =3D { .volatile_reg =3D tegra_admaif_volatile_reg, .reg_defaults =3D tegra264_admaif_reg_defaults, .num_reg_defaults =3D TEGRA264_ADMAIF_CHANNEL_COUNT * 6 + 1, + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_adx.c b/sound/soc/tegra/tegra210_adx.c index 6c9a410085bc..95875c75ddf8 100644 --- a/sound/soc/tegra/tegra210_adx.c +++ b/sound/soc/tegra/tegra210_adx.c @@ -625,6 +625,7 @@ static const struct regmap_config tegra210_adx_regmap_c= onfig =3D { .volatile_reg =3D tegra210_adx_volatile_reg, .reg_defaults =3D tegra210_adx_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_adx_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -638,6 +639,7 @@ static const struct regmap_config tegra264_adx_regmap_c= onfig =3D { .volatile_reg =3D tegra264_adx_volatile_reg, .reg_defaults =3D tegra264_adx_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra264_adx_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_ahub.c b/sound/soc/tegra/tegra210_ahu= b.c index fc5892056f83..43a45f785d5b 100644 --- a/sound/soc/tegra/tegra210_ahub.c +++ b/sound/soc/tegra/tegra210_ahub.c @@ -2133,6 +2133,7 @@ static const struct regmap_config tegra210_ahub_regma= p_config =3D { .reg_stride =3D 4, .writeable_reg =3D tegra210_ahub_wr_reg, .max_register =3D TEGRA210_MAX_REGISTER_ADDR, + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -2142,6 +2143,7 @@ static const struct regmap_config tegra186_ahub_regma= p_config =3D { .reg_stride =3D 4, .writeable_reg =3D tegra186_ahub_wr_reg, .max_register =3D TEGRA186_MAX_REGISTER_ADDR, + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -2151,6 +2153,7 @@ static const struct regmap_config tegra264_ahub_regma= p_config =3D { .reg_stride =3D 4, .writeable_reg =3D tegra264_ahub_wr_reg, .max_register =3D TEGRA264_MAX_REGISTER_ADDR, + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_amx.c b/sound/soc/tegra/tegra210_amx.c index c94f8c84e04f..bfda82505298 100644 --- a/sound/soc/tegra/tegra210_amx.c +++ b/sound/soc/tegra/tegra210_amx.c @@ -654,6 +654,7 @@ static const struct regmap_config tegra210_amx_regmap_c= onfig =3D { .volatile_reg =3D tegra210_amx_volatile_reg, .reg_defaults =3D tegra210_amx_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_amx_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -667,6 +668,7 @@ static const struct regmap_config tegra194_amx_regmap_c= onfig =3D { .volatile_reg =3D tegra210_amx_volatile_reg, .reg_defaults =3D tegra210_amx_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_amx_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -680,6 +682,7 @@ static const struct regmap_config tegra264_amx_regmap_c= onfig =3D { .volatile_reg =3D tegra264_amx_volatile_reg, .reg_defaults =3D tegra264_amx_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra264_amx_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_dmic.c b/sound/soc/tegra/tegra210_dmi= c.c index 66fff53aeaa6..93def7ac4fde 100644 --- a/sound/soc/tegra/tegra210_dmic.c +++ b/sound/soc/tegra/tegra210_dmic.c @@ -483,6 +483,7 @@ static const struct regmap_config tegra210_dmic_regmap_= config =3D { .volatile_reg =3D tegra210_dmic_volatile_reg, .reg_defaults =3D tegra210_dmic_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_dmic_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_i2s.c b/sound/soc/tegra/tegra210_i2s.c index b91e0e6cd7fe..d8e02f0a3025 100644 --- a/sound/soc/tegra/tegra210_i2s.c +++ b/sound/soc/tegra/tegra210_i2s.c @@ -997,6 +997,7 @@ static const struct regmap_config tegra210_regmap_conf = =3D { .volatile_reg =3D tegra210_i2s_volatile_reg, .reg_defaults =3D tegra210_i2s_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_i2s_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 @@ -1044,6 +1045,7 @@ static const struct regmap_config tegra264_regmap_con= f =3D { .volatile_reg =3D tegra264_i2s_volatile_reg, .reg_defaults =3D tegra264_i2s_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra264_i2s_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_mbdrc.c b/sound/soc/tegra/tegra210_mb= drc.c index 09fe3c5cf540..6a268dbb7197 100644 --- a/sound/soc/tegra/tegra210_mbdrc.c +++ b/sound/soc/tegra/tegra210_mbdrc.c @@ -763,6 +763,7 @@ static const struct regmap_config tegra210_mbdrc_regmap= _cfg =3D { .precious_reg =3D tegra210_mbdrc_precious_reg, .reg_defaults =3D tegra210_mbdrc_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_mbdrc_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_mixer.c b/sound/soc/tegra/tegra210_mi= xer.c index ff8e9f2d7abf..6d3a2b76fd61 100644 --- a/sound/soc/tegra/tegra210_mixer.c +++ b/sound/soc/tegra/tegra210_mixer.c @@ -608,6 +608,7 @@ static const struct regmap_config tegra210_mixer_regmap= _config =3D { .precious_reg =3D tegra210_mixer_precious_reg, .reg_defaults =3D tegra210_mixer_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_mixer_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_mvc.c b/sound/soc/tegra/tegra210_mvc.c index 779d4c199da9..6cdc5e1f5507 100644 --- a/sound/soc/tegra/tegra210_mvc.c +++ b/sound/soc/tegra/tegra210_mvc.c @@ -699,6 +699,7 @@ static const struct regmap_config tegra210_mvc_regmap_c= onfig =3D { .volatile_reg =3D tegra210_mvc_volatile_reg, .reg_defaults =3D tegra210_mvc_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_mvc_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_ope.c b/sound/soc/tegra/tegra210_ope.c index 27db70af2746..a440888dcdbd 100644 --- a/sound/soc/tegra/tegra210_ope.c +++ b/sound/soc/tegra/tegra210_ope.c @@ -297,6 +297,7 @@ static const struct regmap_config tegra210_ope_regmap_c= onfig =3D { .volatile_reg =3D tegra210_ope_volatile_reg, .reg_defaults =3D tegra210_ope_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_ope_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_peq.c b/sound/soc/tegra/tegra210_peq.c index 9a05e6913276..2f72e9d541dc 100644 --- a/sound/soc/tegra/tegra210_peq.c +++ b/sound/soc/tegra/tegra210_peq.c @@ -306,6 +306,7 @@ static const struct regmap_config tegra210_peq_regmap_c= onfig =3D { .precious_reg =3D tegra210_peq_precious_reg, .reg_defaults =3D tegra210_peq_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_peq_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; =20 diff --git a/sound/soc/tegra/tegra210_sfc.c b/sound/soc/tegra/tegra210_sfc.c index d6341968bebe..b298bf0421b1 100644 --- a/sound/soc/tegra/tegra210_sfc.c +++ b/sound/soc/tegra/tegra210_sfc.c @@ -3569,6 +3569,7 @@ static const struct regmap_config tegra210_sfc_regmap= _config =3D { .precious_reg =3D tegra210_sfc_precious_reg, .reg_defaults =3D tegra210_sfc_reg_defaults, .num_reg_defaults =3D ARRAY_SIZE(tegra210_sfc_reg_defaults), + .reg_default_cb =3D regmap_default_zero_cb, .cache_type =3D REGCACHE_FLAT, }; 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Fri, 23 Jan 2026 01:54:26 -0800 From: "Sheetal ." To: Mark Brown CC: Sander Vanheule , Greg Kroah-Hartman , "Rafael J . Wysocki" , Danilo Krummrich , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , "Thierry Reding" , Jonathan Hunter , Mohan kumar , , , , Sheetal Subject: [RFC PATCH v3 4/4] regmap: add KUnit coverage for reg_default_cb callback Date: Fri, 23 Jan 2026 15:23:46 +0530 Message-ID: <20260123095346.1258556-5-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260123095346.1258556-1-sheetal@nvidia.com> References: <20260123095346.1258556-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|LV2PR12MB6013:EE_ X-MS-Office365-Filtering-Correlation-Id: d78a0c9e-b2e1-47d9-34e2-08de5a656ee7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2IgZMlvHaQPDRGjeQvXvIoSdaj/O8viCMkeBE0xKS1DLEieIgU844peTpGJo?= =?us-ascii?Q?i7VkBvXGYpZNx8D806sRxa4PJBKt6pfPQmvg0DcAufk7QzZ9T94wn4UvDgQ2?= =?us-ascii?Q?oFkBmlNI05PRi0mXBW3lfYmbmt253xSJuUqk/+0r8ZaTaL92XvOj/XRYJ51k?= =?us-ascii?Q?sKuCm6YaAJHoFBrgN2G/NrT1laKKYbeoNDPG9oJlKGnSYpXOJwGIIREY7AJw?= =?us-ascii?Q?SKX+jkyLusewLnARagYmvyVgM787jK5eFT2HA8FcYsz6t7dFhiEqOqerXMUv?= =?us-ascii?Q?7g+kL6t8hjH/k5p6JwQUxncZRa4iFoTqe2a0MdRckiVB2s/4ZF3UDaKZ3+bc?= =?us-ascii?Q?0WVhoC3zxeLppXsTW8XX5rY2/hsHpQwSZjTWuPFG3/o2kLJXgGbSGct+e+uy?= =?us-ascii?Q?J9Uzqsut/cBanT3saKSUU/ronFBJO3zlfsqziId+VTn5G9svwXYYgsUQvBCo?= =?us-ascii?Q?l9l0/GQFA+w2yc2/MuwZZGFM7mfEOcGZwl3a+HyBH4hgDZqVV1vCpKlWHpyf?= =?us-ascii?Q?A4qinu+le9Y3Y2NCFyFriX/FL8B4wi15H09TCSZeTqfWOC0LChVkNBtvwQVX?= =?us-ascii?Q?6yFp/7Old72hCUzYfjlR2xT3vfCN7ZNWQ9XzKANx9Mvpr9sVB85X8K/G5zC/?= =?us-ascii?Q?35RJvtX50lYd7xMkrTuElRaaEUACqijjRk00IQzqK18Eja1zOFmWFl7Dxp/+?= =?us-ascii?Q?1lb6RjoAxgRCtaZoeSX7Uf9Z1BC115Mfb4uck+Q2jZqihwtxQMSTBkx36fX9?= =?us-ascii?Q?jP9Pqw5HhyoI8ZtAWMf8yKCeb9dR1NrxQqoNaNOhx8g54iJ/3vYPs0yAzGKR?= =?us-ascii?Q?yev2rkcfCXzrYn9T5PsDlrcJE3oyIC/EZ+s2ntIkblqQanW85pTvmOqt94QG?= =?us-ascii?Q?ciVEYvWdR5QouXQl3QvNmfxZAVdYivy+aZRzWYqbxw9ZUvNFAgU7DfiMpiL7?= =?us-ascii?Q?GhjAw159rvpSTrShin+vbDUjlHg2jL9E0ruA5deosjD0fFP5SMU+/tz19PPf?= =?us-ascii?Q?/sMVs5Ep+DLyRoJYEIZ6WOiOAlCClDL6VZoj/4fw2XuU1yG+/SVSkyjGtcV0?= =?us-ascii?Q?7odK40aN+Q4E+XSgPdRHWNfWxBiDm4A9ZRllN4iWjIqOVpXUANeS5uBDolBx?= =?us-ascii?Q?osM4py60eJEAueOKvH/9k+VNQOY2XIScTSZzpN3MmN8KCYMUzG6IZOMnwRhJ?= =?us-ascii?Q?yHKqYMLIfwY1pL/evlN4pJXycbJ3ILnundV2yvErBX47ejjpcEK4Tn5P3YaN?= =?us-ascii?Q?5viZpKuMnH/0INhOc8OHjaPiH1TRNSgLeJXQ9NxtUP/kB7WQCJRo876NHdFa?= =?us-ascii?Q?lD9vxPiaGXg8RltfzV2z5NBH94D0aolsgnMyC4BJ6LtsQ5vHZhm2jQ9kPHRk?= =?us-ascii?Q?KCUJGYOQU4PKTL/Gwx9zRUB/r2Wa7i574rU+R9TOsYSDbGzLeYaa/ASrfcgs?= =?us-ascii?Q?ArFoTRGsJVj11Gh03TVQfGKC6BwcNbDW15tQM9rXThhpSjQAMh/HzDE/F/8V?= =?us-ascii?Q?7jHnFij15ujKNWjuIOhbSYGzElLgU5QEtMrWwQPItKwGEGDEaVDplHKCSRAq?= =?us-ascii?Q?Xw8MyLZZD+ScxTn9R2SPsk2DMyVl8OsgMXQr5Z/RszTI8qqBL4eU9gygrXoK?= =?us-ascii?Q?c4n1jQeIx84Sbs300RBZ4vWZEp0y2MXQAj1VTWMtY0y51R7SqzDpd4C5l5rL?= =?us-ascii?Q?Y2ihcw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 09:54:42.9964 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d78a0c9e-b2e1-47d9-34e2-08de5a656ee7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB6013 Content-Type: text/plain; charset="utf-8" From: Sheetal Add a flat-cache KUnit test that verifies reg_defaults are honored while missing entries are populated via the reg_default_cb callback without hardware reads. This exercises the new callback path added for REGCACHE_FLAT defaults. Test: ./tools/testing/kunit/kunit.py run regmap Result: =3D=3D=3D=3D=3D=3D=3D=3D reg_default_callback_populates_flat_cache =3D=3D= =3D=3D=3D=3D=3D=3D [PASSED] flat-default @0x0 [PASSED] flat-default fast I/O @0x0 [PASSED] flat-default @0x2001 =3D=3D=3D=3D [PASSED] reg_default_callback_populates_flat_cache =3D=3D=3D= =3D Signed-off-by: Sheetal --- drivers/base/regmap/regmap-kunit.c | 91 ++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/base/regmap/regmap-kunit.c b/drivers/base/regmap/regma= p-kunit.c index f6fc5ed016da..38c20a09670c 100644 --- a/drivers/base/regmap/regmap-kunit.c +++ b/drivers/base/regmap/regmap-kunit.c @@ -15,6 +15,8 @@ KUNIT_DEFINE_ACTION_WRAPPER(regmap_exit_action, regmap_ex= it, struct regmap *); =20 struct regmap_test_priv { struct device *dev; + bool *reg_default_called; + unsigned int reg_default_max; }; =20 struct regmap_test_param { @@ -118,6 +120,14 @@ static const struct regmap_test_param real_cache_types= _only_list[] =3D { =20 KUNIT_ARRAY_PARAM(real_cache_types_only, real_cache_types_only_list, param= _to_desc); =20 +static const struct regmap_test_param flat_cache_types_list[] =3D { + { .cache =3D REGCACHE_FLAT, .from_reg =3D 0 }, + { .cache =3D REGCACHE_FLAT, .from_reg =3D 0, .fast_io =3D true }, + { .cache =3D REGCACHE_FLAT, .from_reg =3D 0x2001 }, +}; + +KUNIT_ARRAY_PARAM(flat_cache_types, flat_cache_types_list, param_to_desc); + static const struct regmap_test_param real_cache_types_list[] =3D { { .cache =3D REGCACHE_FLAT, .from_reg =3D 0 }, { .cache =3D REGCACHE_FLAT, .from_reg =3D 0, .fast_io =3D true }, @@ -248,6 +258,37 @@ static bool reg_5_false(struct device *dev, unsigned i= nt reg) return reg !=3D (param->from_reg + 5); } =20 +static unsigned int reg_default_expected(unsigned int reg) +{ + return 0x5a5a0000 | (reg & 0xffff); +} + +static int reg_default_test_cb(struct device *dev, unsigned int reg, + unsigned int *def) +{ + struct kunit *test =3D dev_get_drvdata(dev); + struct regmap_test_priv *priv =3D test->priv; + + if (priv && priv->reg_default_called && reg <=3D priv->reg_default_max) + priv->reg_default_called[reg] =3D true; + + *def =3D reg_default_expected(reg); + return 0; +} + +static void expect_reg_default_value(struct kunit *test, struct regmap *ma= p, + struct regmap_ram_data *data, + struct regmap_test_priv *priv, + unsigned int reg) +{ + unsigned int val; + + KUNIT_EXPECT_TRUE(test, priv->reg_default_called[reg]); + KUNIT_EXPECT_EQ(test, 0, regmap_read(map, reg, &val)); + KUNIT_EXPECT_EQ(test, reg_default_expected(reg), val); + KUNIT_EXPECT_FALSE(test, data->read[reg]); +} + static void basic_read_write(struct kunit *test) { struct regmap *map; @@ -628,6 +669,54 @@ static void reg_defaults(struct kunit *test) KUNIT_EXPECT_EQ(test, config.cache_type =3D=3D REGCACHE_NONE, data->read= [i]); } =20 +static void reg_default_callback_populates_flat_cache(struct kunit *test) +{ + const struct regmap_test_param *param =3D test->param_value; + struct regmap_test_priv *priv =3D test->priv; + struct regmap *map; + struct regmap_config config; + struct regmap_ram_data *data; + unsigned int reg, val; + unsigned int defaults_end; + + config =3D test_regmap_config; + config.num_reg_defaults =3D 3; + config.max_register =3D param->from_reg + BLOCK_TEST_SIZE - 1; + config.reg_default_cb =3D reg_default_test_cb; + + priv->reg_default_max =3D config.max_register; + priv->reg_default_called =3D kunit_kcalloc(test, config.max_register + 1, + sizeof(*priv->reg_default_called), + GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, priv->reg_default_called); + + map =3D gen_regmap(test, &config, &data); + KUNIT_ASSERT_FALSE(test, IS_ERR(map)); + if (IS_ERR(map)) + return; + + for (reg =3D 0; reg <=3D config.max_register; reg++) + data->read[reg] =3D false; + + defaults_end =3D param->from_reg + config.num_reg_defaults - 1; + + for (reg =3D param->from_reg; reg <=3D defaults_end; reg++) { + KUNIT_EXPECT_FALSE(test, priv->reg_default_called[reg]); + KUNIT_EXPECT_EQ(test, 0, regmap_read(map, reg, &val)); + KUNIT_EXPECT_EQ(test, data->vals[reg], val); + KUNIT_EXPECT_FALSE(test, data->read[reg]); + } + + if (param->from_reg > 0) + expect_reg_default_value(test, map, data, priv, 0); + + if (defaults_end + 1 <=3D config.max_register) + expect_reg_default_value(test, map, data, priv, defaults_end + 1); + + if (config.max_register > defaults_end + 1) + expect_reg_default_value(test, map, data, priv, config.max_register); +} + static void reg_defaults_read_dev(struct kunit *test) { struct regmap *map; @@ -2058,6 +2147,8 @@ static struct kunit_case regmap_test_cases[] =3D { KUNIT_CASE_PARAM(write_readonly, regcache_types_gen_params), KUNIT_CASE_PARAM(read_writeonly, regcache_types_gen_params), KUNIT_CASE_PARAM(reg_defaults, regcache_types_gen_params), + KUNIT_CASE_PARAM(reg_default_callback_populates_flat_cache, + flat_cache_types_gen_params), KUNIT_CASE_PARAM(reg_defaults_read_dev, regcache_types_gen_params), KUNIT_CASE_PARAM(register_patch, regcache_types_gen_params), KUNIT_CASE_PARAM(stride, regcache_types_gen_params), --=20 2.34.1