From nobody Tue Feb 10 11:13:10 2026 Received: from cstnet.cn (unknown [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 952BF33EB09; Fri, 23 Jan 2026 09:29:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769160572; cv=none; b=ujAmmf+r4Uwc54bSyAvzyEUUK0ugcrrxpBqdifBuxeBgaHrlv3uqD4nPzL+f2IQxL1pgc6KcJ2DIk0tcu2qCQXIklJCftF5at3jo4TyWB/PG0yx+ROY26Pjkyh0KS4/vEnCaY34pU93BePzDIkbLxS9QwbHD779dKSf5xx6WShU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769160572; c=relaxed/simple; bh=LoJOfTU0+98faKBjjbQcKsjpq3/oTVGLzcjdYvVlqJE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UsJQmg2629tufwrXW57OyLAyRybVxRYbAaxjgv4zrXyckoPDzV652buR7E1RK/k5JNnvkXMy1QMQQ0y1OTpVD/klCGuHprXcZnoehLNwkHsYHbEWXjSsLDmx27hEOGiI5TG7fwRahm46GH4RiYPKMd7BvOsRSG8khvDwlnfcjeY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.103.171]) by APP-03 (Coremail) with SMTP id rQCowABXZ85EP3NppX1gBg--.20954S6; Fri, 23 Jan 2026 17:29:01 +0800 (CST) From: Icenowy Zheng To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei Cc: Philipp Zabel , Dmitry Baryshkov , Michal Wilczynski , Luca Ceresoli , Han Gao , Yao Zi , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Icenowy Zheng , Krzysztof Kozlowski Subject: [PATCH v6 4/9] dt-bindings: display/bridge: add binding for TH1520 HDMI controller Date: Fri, 23 Jan 2026 17:28:25 +0800 Message-ID: <20260123092830.4046009-5-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260123092830.4046009-1-zhengxingda@iscas.ac.cn> References: <20260123092830.4046009-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowABXZ85EP3NppX1gBg--.20954S6 X-Coremail-Antispam: 1UD129KBjvJXoWxuF1rJF1xAw47tryUJr48Crg_yoW5tw45pa yfGa18JFyktF17ua1xAF10krZYqrWkAFnYgr17Ww1jyay5WF12qrZIkrn8XFyrJF4xZa43 ZFZ8Xr1fKa1av3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0pRQJ5wUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" From: Icenowy Zheng T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock and two reset controls. Add a device tree binding to it. Signed-off-by: Icenowy Zheng Signed-off-by: Icenowy Zheng Reviewed-by: Krzysztof Kozlowski --- No changes since v3. Changes in v2: - Re-aligned multi-line clocks/resets in example. - Added Krzysztof's R-b. .../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/thead,= th1520-dw-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/thead,th1520-= dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/thead,th152= 0-dw-hdmi.yaml new file mode 100644 index 0000000000000..68fff885ce15b --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi= .yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 DesignWare HDMI TX Encoder + +maintainers: + - Icenowy Zheng + +description: + The HDMI transmitter is a Synopsys DesignWare HDMI TX controller + paired with a DesignWare HDMI Gen2 TX PHY. + +allOf: + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - thead,th1520-dw-hdmi + + reg-io-width: + const: 4 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iahb + - const: isfr + - const: cec + - const: pix + + resets: + items: + - description: Main reset + - description: Configuration APB reset + + reset-names: + items: + - const: main + - const: apb + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port connected to DC8200 DPU "DP" output + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-io-width + - clocks + - clock-names + - resets + - reset-names + - interrupts + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + hdmi@ffef540000 { + compatible =3D "thead,th1520-dw-hdmi"; + reg =3D <0xff 0xef540000 0x0 0x40000>; + reg-io-width =3D <4>; + interrupts =3D <111 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_HDMI_PCLK>, + <&clk_vo CLK_HDMI_SFR>, + <&clk_vo CLK_HDMI_CEC>, + <&clk_vo CLK_HDMI_PIXCLK>; + clock-names =3D "iahb", "isfr", "cec", "pix"; + resets =3D <&rst_vo TH1520_RESET_ID_HDMI>, + <&rst_vo TH1520_RESET_ID_HDMI_APB>; + reset-names =3D "main", "apb"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dp1>; + }; + }; + + port@1 { + reg =3D <1>; + + hdmi_out_conn: endpoint { + remote-endpoint =3D <&hdmi_conn_in>; + }; + }; + }; + }; + }; --=20 2.52.0