From nobody Mon Feb 9 01:34:09 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E4991C84D7 for ; Fri, 23 Jan 2026 08:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.222 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769158008; cv=none; b=aVn4TpejB3e/oVoID3nwh4hYC+PHf1o019umo7qmj/PGk6HFBIRMXYwHsGa2r4rzqAIWJG9AMiNXJZqfFNL2RLprwVtBmr45ZNFIRq72H4qa6JUaUNj+wfjTPqfOOzvNFF1QX3iimS3Pvlaeyu5G/s7pvyVRfIJLnZd524PMAmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769158008; c=relaxed/simple; bh=J4+r2fVPJdVhQx4M6XnL5JaET7VqfcPYc1KHQeg0jpQ=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=QComzciq9jZZ9J0scMbv73lMM0ciYuwjmQ+vJFW6+Ohc5bZQFXda5vGo/1dM0u4IOpr+/RtL3Pb6T69hJHIkqupCdLjvnGUzmiNG0yT2pKkTh2aSJQxl+wVrTHriF8RNHyZDLQJ0K0/wbWzIIXqrDYVBbjwJc1796Cr8tczTSns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=Lo1e7XLq; arc=none smtp.client-ip=113.46.200.222 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="Lo1e7XLq" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=A/boR6Uyi0r2ZVgaxDDkJDllkfEegd54jGl8wl1NFEE=; b=Lo1e7XLqu6B2j7gT3s/LgrgfAaceHfbGb5p0fZQ4FSKSDqMTt7LObP5HkzAdsyr0gmAsPtGtK 6EtbkPIoc0097oZpiQgEf/WPG4M5sHH7qhHb3tXeNPc+cUPu/2zgKa0mZCXP8LyR0JUmC2/IeYq hHK41AtwCZ3NiUql8PphMUk= Received: from mail.maildlp.com (unknown [172.19.163.127]) by canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4dyBKD6l6VzLlTR; Fri, 23 Jan 2026 16:43:12 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 44042402AB; Fri, 23 Jan 2026 16:46:37 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 23 Jan 2026 16:46:36 +0800 From: Jinjie Ruan To: , , , CC: Subject: [PATCH] timers: Replace get_timer_this_cpu_base() with get_timer_cpu_base() Date: Fri, 23 Jan 2026 16:47:15 +0800 Message-ID: <20260123084715.365857-1-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" get_timer_this_cpu_base() is only used in __mod_timer() where the timer base lock is already held via raw_spin_lock_irqsave(). In this context, preemption is disabled and the CPU number cannot change, making raw_smp_processor_id() safe to use. Since get_timer_cpu_base() provides identical functionality using raw_smp_processor_id(), replace get_timer_this_cpu_base() with get_timer_cpu_base() to eliminate code duplication. No functional change intended. Signed-off-by: Jinjie Ruan --- kernel/time/timer.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/kernel/time/timer.c b/kernel/time/timer.c index 1f2364126894..5a827e09cb8f 100644 --- a/kernel/time/timer.c +++ b/kernel/time/timer.c @@ -925,20 +925,6 @@ static inline struct timer_base *get_timer_cpu_base(u3= 2 tflags, u32 cpu) return per_cpu_ptr(&timer_bases[index], cpu); } =20 -static inline struct timer_base *get_timer_this_cpu_base(u32 tflags) -{ - int index =3D tflags & TIMER_PINNED ? BASE_LOCAL : BASE_GLOBAL; - - /* - * If the timer is deferrable and NO_HZ_COMMON is set then we need - * to use the deferrable base. - */ - if (IS_ENABLED(CONFIG_NO_HZ_COMMON) && (tflags & TIMER_DEFERRABLE)) - index =3D BASE_DEF; - - return this_cpu_ptr(&timer_bases[index]); -} - static inline struct timer_base *get_timer_base(u32 tflags) { return get_timer_cpu_base(tflags, tflags & TIMER_CPUMASK); @@ -1098,7 +1084,7 @@ __mod_timer(struct timer_list *timer, unsigned long e= xpires, unsigned int option if (!ret && (options & MOD_TIMER_PENDING_ONLY)) goto out_unlock; =20 - new_base =3D get_timer_this_cpu_base(timer->flags); + new_base =3D get_timer_cpu_base(timer->flags, raw_smp_processor_id()); =20 if (base !=3D new_base) { /* --=20 2.34.1