From nobody Sat Feb 7 08:44:22 2026 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15CCD33B96B for ; Fri, 23 Jan 2026 07:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769154039; cv=none; b=Vwp/AfFV8cPuXqsZjKoX6YleZXbkImOv37o6dYgkwx7E4ZmXI4DebbMwRCNXXrAtuLox7v+8EcML6dzpMzDcPFW9SrO1FAG8g5Qc2Prj9ufzaPIT4lTZBYLJbLIx8Z0hZSN0k645R9P2vu7gaKSxL0icrWRksJAscq0FQarrZLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769154039; c=relaxed/simple; bh=y0NTW9XCVg0FyL5+T5+Jrr9kebCDLQl2SzjyxOzjPxU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ypv2UOc2wf4c7Q+vqWbpuyO2mbTg/ah/X4g402n66Gd0YwwUaF4ENe/l7BrMnmmzylfzQ8ew57IVTyKo8KFPPu9jUbEfJWn3meL0xzeNMcMWFK9DB00PDyImnLaAUf0xeDK3ARym2bRr/KcIlmWp94c4GDA3lOFhdV91APsMq48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com; spf=pass smtp.mailfrom=linux.ibm.com; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b=sQShysjE; arc=none smtp.client-ip=148.163.158.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="sQShysjE" Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 60N2HcKF021309; Fri, 23 Jan 2026 07:40:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h= content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=+dbv/uGTY2AYT4LIO G+sW6cKxWYy/xnUhN6G2aQANWM=; b=sQShysjEACoFXB31JQuhXmq8CnCDq/2zk izJX55KRGynYD4zTGNxlVIePi7TBOHsNBxziJNKlrp1TgdW5FUT7A0udxqMKZFj+ ZxqwVq4t2IzfcAHSF24XbS5bN3U5zgu7qHOUE4A4xB/QF0aO9CLNJCcjOD1qXE9e cwqRYoudh2RPhXTzK9HGodtHTdki0R8GVktU2EDfyrUYOWl4ZEdzEPKSTqNNtn2J eRIt5sg5mt9XXEX1uIm4bPcI32ajp2J3VkqubFE8+Hqv7rfSgkMteeROBiNxLP15 PHmWmWzgMYzxubOH/TiuvLMbqJ4zK/EKd5J/mFHNdhHM/sqQBlc5g== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4bt612ha3w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jan 2026 07:40:07 +0000 (GMT) Received: from m0360072.ppops.net (m0360072.ppops.net [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.0.8) with ESMTP id 60N7e62p012063; Fri, 23 Jan 2026 07:40:06 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4bt612ha3t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jan 2026 07:40:06 +0000 (GMT) Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 60N7VTmk027293; Fri, 23 Jan 2026 07:40:05 GMT Received: from smtprelay04.fra02v.mail.ibm.com ([9.218.2.228]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4brnrnfspf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jan 2026 07:40:05 +0000 Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 60N7e1OK23724734 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 23 Jan 2026 07:40:01 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ACD552004B; Fri, 23 Jan 2026 07:40:01 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0D71520043; Fri, 23 Jan 2026 07:39:56 +0000 (GMT) Received: from li-1a3e774c-28e4-11b2-a85c-acc9f2883e29.ibm.com.com (unknown [9.124.222.171]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 23 Jan 2026 07:39:55 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, chleroy@kernel.org, ryabinin.a.a@gmail.com, glider@google.com, andreyknvl@gmail.com, dvyukov@google.com, vincenzo.frascino@arm.com, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, ruanjinjie@huawei.com, sshegde@linux.ibm.com, akpm@linux-foundation.org, charlie@rivosinc.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, segher@kernel.crashing.org, peterz@infradead.org, bigeasy@linutronix.de, namcao@linutronix.de, tglx@linutronix.de, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com Subject: [PATCH v4 3/8] powerpc: introduce arch_enter_from_user_mode Date: Fri, 23 Jan 2026 13:09:11 +0530 Message-ID: <20260123073916.956498-4-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260123073916.956498-1-mkchauras@linux.ibm.com> References: <20260123073916.956498-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: qrbpVO3rl70azuk5utvgyyZcZ4ho3sGF X-Authority-Analysis: v=2.4 cv=LaIxKzfi c=1 sm=1 tr=0 ts=697325d7 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=hdW59ek6rJpVHQNvHwAA:9 X-Proofpoint-ORIG-GUID: iCWsJd0cUjvJE0H8H5t-LDLDWzcHY5g8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIzMDA1NSBTYWx0ZWRfX29J/mZte8N+u n8SBCPAT3vDCn8isSeenjxmqI2FbsPJaCB3DIHx8Uw7xsO8OPXR54luvxKPgWze0Fu/ZQW3zVlv U35R96jIJhH3zbJxdl3POGAjZrvgbag3NQlxCqRKvHS8wVFswS5Y+vUJQltLPU1Kw74vZVokrMX ojG7tTY/MEgu3EFZA8n/XVeGZ9S/69z/5k2p0B1TpQYPQU9IiB8QZIk3FME7Tp7L7Uwe3/qG04T skET614B5OGMD0/mh86aDmpsZoKuXPh/8/215koWiqo7p5jYUjqV4vGacrvXtQqTgwowLJuE5UI TiMUNr3Y4OkKXZmv7SborLF7sboppl6KPYKzkiIfm/b0cbiD200CI3JJRMjBOg8lsLEq6cEpXj+ Xus6QS3hS61xIocX+aarIhc7Hs1qvZ4OC2Pw/JAkXqRBveGGuoWBeaMmLeYo40k8+17X8nNQA1Q +3ay+b4Qfsjc9mFLF9w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_06,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2601150000 definitions=main-2601230055 Content-Type: text/plain; charset="utf-8" From: Mukesh Kumar Chaurasiya Implement the arch_enter_from_user_mode() hook required by the generic entry/exit framework. This helper prepares the CPU state when entering the kernel from userspace, ensuring correct handling of KUAP/KUEP, transactional memory, and debug register state. This patch contains no functional changes, it is purely preparatory for enabling the generic syscall and interrupt entry path on PowerPC. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 118 ++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index 05ce0583b600..837a7e020e82 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -3,6 +3,124 @@ #ifndef _ASM_PPC_ENTRY_COMMON_H #define _ASM_PPC_ENTRY_COMMON_H =20 +#include +#include #include +#include + +static __always_inline void booke_load_dbcr0(void) +{ +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dbcr0 =3D current->thread.debug.dbcr0; + + if (likely(!(dbcr0 & DBCR0_IDM))) + return; + + /* + * Check to see if the dbcr0 register is set up to debug. + * Use the internal debug mode bit to do this. + */ + mtmsr(mfmsr() & ~MSR_DE); + if (IS_ENABLED(CONFIG_PPC32)) { + isync(); + global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); + } + mtspr(SPRN_DBCR0, dbcr0); + mtspr(SPRN_DBSR, -1); +#endif +} + +static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) +{ + kuap_lock(); + + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + BUG_ON(irq_soft_mask_return() !=3D IRQS_ALL_DISABLED); + + BUG_ON(regs_is_unrecoverable(regs)); + BUG_ON(!user_mode(regs)); + BUG_ON(regs_irqs_disabled(regs)); + +#ifdef CONFIG_PPC_PKEY + if (mmu_has_feature(MMU_FTR_PKEY) && trap_is_syscall(regs)) { + unsigned long amr, iamr; + bool flush_needed =3D false; + /* + * When entering from userspace we mostly have the AMR/IAMR + * different from kernel default values. Hence don't compare. + */ + amr =3D mfspr(SPRN_AMR); + iamr =3D mfspr(SPRN_IAMR); + regs->amr =3D amr; + regs->iamr =3D iamr; + if (mmu_has_feature(MMU_FTR_KUAP)) { + mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); + flush_needed =3D true; + } + if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { + mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); + flush_needed =3D true; + } + if (flush_needed) + isync(); + } +#endif + kuap_assert_locked(); + booke_restore_dbcr0(); + account_cpu_user_entry(); + account_stolen_time(); + + /* + * This is not required for the syscall exit path, but makes the + * stack frame look nicer. If this was initialised in the first stack + * frame, or if the unwinder was taught the first stack frame always + * returns to user with IRQS_ENABLED, this store could be avoided! + */ + irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); + + /* + * If system call is called with TM active, set _TIF_RESTOREALL to + * prevent RFSCV being used to return to userspace, because POWER9 + * TM implementation has problems with this instruction returning to + * transactional state. Final register values are not relevant because + * the transaction will be aborted upon return anyway. Or in the case + * of unsupported_scv SIGILL fault, the return state does not much + * matter because it's an edge case. + */ + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && + unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) + set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); + + /* + * If the system call was made with a transaction active, doom it and + * return without performing the system call. Unless it was an + * unsupported scv vector, in which case it's treated like an illegal + * instruction. + */ +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && + !trap_is_unsupported_scv(regs)) { + /* Enable TM in the kernel, and disable EE (for scv) */ + hard_irq_disable(); + mtmsr(mfmsr() | MSR_TM); + + /* tabort, this dooms the transaction, nothing else */ + asm volatile(".long 0x7c00071d | ((%0) << 16)" + :: "r"(TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT)); + + /* + * Userspace will never see the return value. Execution will + * resume after the tbegin. of the aborted transaction with the + * checkpointed register state. A context switch could occur + * or signal delivered to the process before resuming the + * doomed transaction context, but that should all be handled + * as expected. + */ + return; + } +#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ +} + +#define arch_enter_from_user_mode arch_enter_from_user_mode =20 #endif /* _ASM_PPC_ENTRY_COMMON_H */ --=20 2.52.0