From nobody Sat Feb 7 06:14:42 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2ECC8274B59; Fri, 23 Jan 2026 17:39:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769189958; cv=none; b=AzIvQAvRrnn9it81P2caoR1g0ZPY+o+8MR4sQk3IC1hNsFpe1ed6M6/HwKI6bxSxoBYJLBpbPBbIPC1zdjSEpXesTStlS0eSelf2T7eGwmcwSKeOd8SDlLaihVAkua/gu37wLaSEzE+VdOtJ5ViXkDot6A3AEhRKd5a2sRlSim8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769189958; c=relaxed/simple; bh=l0iWjHbipPa1ijZkFAgcLPQniaiAMUAfDzX0le3Yfso=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GY1WhQG56IGinWYI8CB/XuzckvTL03G0ph+SraU92pRdemynrPv7p1ZqNByHdzthftW807TS1URfhpMP26Z5Sj20TrGM6+WLGx1THgzJ9UmQhL8OelmE7+irargjAbuz+yJ/r7iO61xvap7WLHMYnaQ8HuUK1m7YAz7dGFssO28= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9A17C1515; Fri, 23 Jan 2026 09:39:06 -0800 (PST) Received: from e137876.arm.com (e137876.arm.com [10.33.10.100]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8B00E3F632; Fri, 23 Jan 2026 09:39:11 -0800 (PST) From: Debbie Horsfall Date: Fri, 23 Jan 2026 17:37:46 +0000 Subject: [PATCH 1/2] dt-bindings: arm: Add Zena CSS compatibility Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-zena-css-v1-1-34adb95cdf89@arm.com> References: <20260123-zena-css-v1-0-34adb95cdf89@arm.com> In-Reply-To: <20260123-zena-css-v1-0-34adb95cdf89@arm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Debbie Horsfall X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769189949; l=2085; i=debbie.horsfall@arm.com; s=20260123; h=from:subject:message-id; bh=l0iWjHbipPa1ijZkFAgcLPQniaiAMUAfDzX0le3Yfso=; b=dw/o4m/lNZIwCP4dyBjk5k6HBlbBcZQelmXDl0DeJskrhe7iQMiJXJO9uUzpmKTUtn4Yj0MZS 4JdhJk9mRsjCjUvsRAWxbcPP16kVAqOSQD2+cSX88d2CNFEObwAZRUC X-Developer-Key: i=debbie.horsfall@arm.com; a=ed25519; pk=PHSQwhhwfluuPcWn1fk950OfqGxCy2cjbyQb7dfAcFY= Add compatibility to Arm Zena CSS Fixed Virtual Platform [1]. [1] https://www.arm.com/products/automotive/compute-subsystems/zena Signed-off-by: Debbie Horsfall Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/arm,zena-css.yaml | 31 ++++++++++++++++++= ++++ MAINTAINERS | 5 ++++ 2 files changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,zena-css.yaml b/Docu= mentation/devicetree/bindings/arm/arm,zena-css.yaml new file mode 100644 index 000000000000..42699b4db41e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,zena-css.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,zena-css.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Zena Compute Subsystem Platforms + +maintainers: + - Debbie Horsfall + +description: + Arm Zena Compute Subsystem (CSS) is a compute platform targeting + the automotive sector. Arm Zena CSS is a high-performance Arm + Cortex-A720AE Application Processor system augmented with an Arm + Cortex-R82AE based Safety Island and real-time domain. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Arm Zena CSS Platforms + items: + - enum: + - arm,zena-css-fvp + - const: arm,zena-css + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 6863d5fa07a1..90d88137adf1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3723,6 +3723,11 @@ F: drivers/video/fbdev/vt8500lcdfb.* F: drivers/video/fbdev/wm8505fb* F: drivers/video/fbdev/wmt_ge_rops.* =20 +ARM/ZENA CSS PLATFORM +M: Debbie Horsfall +S: Maintained +F: Documentation/devicetree/bindings/arm/arm,zena-css.yaml + ARM/ZYNQ ARCHITECTURE M: Michal Simek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0 From nobody Sat Feb 7 06:14:42 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A06C626FDAC; Fri, 23 Jan 2026 17:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769189959; cv=none; b=K3yVpuhry74Ma8QZSwcokLULqdTfwgawo0qEm3Gq0R8MAXqiK2i3/fRB8/ctP7thEKyEoXqr2pzHRS8ULkk5UzimUM6kBB4HBi4h+mPzlApu9f9iRsJKgMGRKdydbd+lZ/wTZ6mRcM+Rpa4BiF6tZk2j4z8vi6MrhthgEKe6K/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769189959; c=relaxed/simple; bh=0bl0KqDzZZk7GcEuDtae0fLzTh5nXNwSULKjE7OLTc8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LvZGbvsOhZJ/7Uk8wRykT9BJHTtDngAM9EowAXQAUQsWxU8fzMExnjXysbIuoJounagwxJZSWJvc6RjCgBEy9oWM/k71/zMMtjuWwmST5cJGG72a4CjaFk7AymzAuyK1PFiBK8arWjTAuxNHLyhaItQ8INFLd/HTu2scvaqSZnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AECFF1576; Fri, 23 Jan 2026 09:39:08 -0800 (PST) Received: from e137876.arm.com (e137876.arm.com [10.33.10.100]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7D03C3F632; Fri, 23 Jan 2026 09:39:13 -0800 (PST) From: Debbie Horsfall Date: Fri, 23 Jan 2026 17:37:47 +0000 Subject: [PATCH 2/2] arm64: dts: zena: Add support for Zena CSS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-zena-css-v1-2-34adb95cdf89@arm.com> References: <20260123-zena-css-v1-0-34adb95cdf89@arm.com> In-Reply-To: <20260123-zena-css-v1-0-34adb95cdf89@arm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Debbie Horsfall X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769189949; l=23488; i=debbie.horsfall@arm.com; s=20260123; h=from:subject:message-id; bh=0bl0KqDzZZk7GcEuDtae0fLzTh5nXNwSULKjE7OLTc8=; b=UAL+LdTWYJOs/9WyCChu6L+J0xoUGbreNdiBaA8wQE8F2hCIh1dBxh8DcqirqQ29n/rP2hoGz sFwA9BIt7YZA7urc5YkXjpc7rxwySjHpyz2mdsrtLwQISUp+A5krkKS X-Developer-Key: i=debbie.horsfall@arm.com; a=ed25519; pk=PHSQwhhwfluuPcWn1fk950OfqGxCy2cjbyQb7dfAcFY= Introduce the Zena CSS Fixed Virtual Platform (FVP) dts. This is currently the only Zena CSS variant, however the common definitions are included in a common dtsi for extensibility. Signed-off-by: Debbie Horsfall --- MAINTAINERS | 1 + arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/zena-css-fvp.dts | 55 ++ arch/arm64/boot/dts/arm/zena-css.dtsi | 826 +++++++++++++++++++++++++++= ++++ 4 files changed, 883 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 90d88137adf1..d1d2dae6a71e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3727,6 +3727,7 @@ ARM/ZENA CSS PLATFORM M: Debbie Horsfall S: Maintained F: Documentation/devicetree/bindings/arm/arm,zena-css.yaml +F: arch/arm64/boot/dts/arm/zena-css* =20 ARM/ZYNQ ARCHITECTURE M: Michal Simek diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index f30ee045dc95..770fb145b4a9 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -8,3 +8,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.d= tb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb morello-fvp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D zena-css-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/zena-css-fvp.dts b/arch/arm64/boot/dts= /arm/zena-css-fvp.dts new file mode 100644 index 000000000000..d3c649e894d1 --- /dev/null +++ b/arch/arm64/boot/dts/arm/zena-css-fvp.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arm Limited. All rights reserved. + */ + +/dts-v1/; + +#include "zena-css.dtsi" + +/ { + model =3D "Zena CSS Fixed Virtual Platform"; + compatible =3D "arm,zena-css-fvp", "arm,zena-css"; + + chosen { + stdout-path =3D &soc_serial0; + }; +}; + +&soc { + virtio@30060000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x30060000 0x0 0x10000>; + interrupts =3D ; + }; + + virtio@30020000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x30020000 0x0 0x10000>; + interrupts =3D ; + }; + + virtio@30030000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x30030000 0x0 0x10000>; + interrupts =3D ; + }; + + virtio@30040000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x30040000 0x0 0x10000>; + interrupts =3D ; + }; + + virtio@30050000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x30050000 0x0 0x10000>; + interrupts =3D ; + }; + + virtio@30080000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x30080000 0x0 0x10000>; + interrupts =3D ; + }; +}; diff --git a/arch/arm64/boot/dts/arm/zena-css.dtsi b/arch/arm64/boot/dts/ar= m/zena-css.dtsi new file mode 100644 index 000000000000..7825e93df0a6 --- /dev/null +++ b/arch/arm64/boot/dts/arm/zena-css.dtsi @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + /* + * The latency and residency numbers below are for illustrative + * purpose only and may vary on actual silicon. These values are + * considered just to demonstrate that the cpuidle governor + * logic works. + */ + idle-states { + entry-method =3D "psci"; + + CPU_SLEEP: cpu-sleep { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x0010000>; + local-timer-stop; + entry-latency-us =3D <800>; + exit-latency-us =3D <3200>; + min-residency-us =3D <4200>; + }; + CLUSTER_SLEEP: cluster-sleep { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x1010000>; + local-timer-stop; + entry-latency-us =3D <1000>; + exit-latency-us =3D <3200>; + min-residency-us =3D <4500>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + }; + + cluster1 { + + core0 { + cpu =3D <&CPU4>; + }; + + core1 { + cpu =3D <&CPU5>; + }; + + core2 { + cpu =3D <&CPU6>; + }; + + core3 { + cpu =3D <&CPU7>; + }; + }; + + cluster2 { + + core0 { + cpu =3D <&CPU8>; + }; + + core1 { + cpu =3D <&CPU9>; + }; + + core2 { + cpu =3D <&CPU10>; + }; + + core3 { + cpu =3D <&CPU11>; + }; + }; + + cluster3 { + + core0 { + cpu =3D <&CPU12>; + }; + + core1 { + cpu =3D <&CPU13>; + }; + + core2 { + cpu =3D <&CPU14>; + }; + + core3 { + cpu =3D <&CPU15>; + }; + }; + }; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x00>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL0_L2_0>; + + CL0_L2_0: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL0_L3>; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x100>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL0_L2_1>; + + CL0_L2_1: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL0_L3>; + }; + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x200>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL0_L2_2>; + + CL0_L2_2: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL0_L3>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x300>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL0_L2_3>; + + CL0_L2_3: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL0_L3>; + }; + }; + + CPU4: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x10000>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL1_L2_0>; + + CL1_L2_0: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL1_L3>; + }; + }; + + CPU5: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x10100>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL1_L2_1>; + + CL1_L2_1: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL1_L3>; + }; + }; + + CPU6: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x10200>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL1_L2_2>; + + CL1_L2_2: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL1_L3>; + }; + }; + + CPU7: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x10300>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL1_L2_3>; + + CL1_L2_3: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL1_L3>; + }; + }; + + CPU8: cpu@20000 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x20000>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL2_L2_0>; + + CL2_L2_0: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL2_L3>; + }; + }; + + CPU9: cpu@20100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x20100>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL2_L2_1>; + + CL2_L2_1: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL2_L3>; + }; + }; + + CPU10: cpu@20200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x20200>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL2_L2_2>; + + CL2_L2_2: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL2_L3>; + }; + }; + + CPU11: cpu@20300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x20300>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL2_L2_3>; + + CL2_L2_3: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL2_L3>; + }; + }; + + CPU12: cpu@30000 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x30000>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL3_L2_0>; + + CL3_L2_0: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL3_L3>; + }; + }; + + CPU13: cpu@30100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x30100>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL3_L2_1>; + + CL3_L2_1: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL3_L3>; + }; + }; + + CPU14: cpu@30200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x30200>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL3_L2_2>; + + CL3_L2_2: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL3_L3>; + }; + }; + + CPU15: cpu@30300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720ae"; + reg =3D <0x00 0x30300>; + enable-method =3D "psci"; + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <0x40>; + i-cache-sets =3D <0x100>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <0x40>; + d-cache-sets =3D <0x100>; + clocks =3D <&scmi_dvfs 0x00>; + cpu-idle-states =3D <&CPU_SLEEP &CLUSTER_SLEEP>; + next-level-cache =3D <&CL3_L2_3>; + + CL3_L2_3: l2-cache { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x02>; + /* 512KB */ + cache-size =3D <0x80000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 8-way set */ + cache-sets =3D <0x400>; + next-level-cache =3D <&CL3_L3>; + }; + }; + + CL0_L3: l3-cache0 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x03>; + /* 4MB */ + cache-size =3D <0x400000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 16-way set */ + cache-sets =3D <0x1000>; + }; + + CL1_L3: l3-cache1 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x03>; + /* 4MB */ + cache-size =3D <0x400000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 16-way set */ + cache-sets =3D <0x1000>; + }; + + CL2_L3: l3-cache2 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x03>; + /* 4MB */ + cache-size =3D <0x400000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 16-way set */ + cache-sets =3D <0x1000>; + }; + + CL3_L3: l3-cache3 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <0x03>; + /* 4MB */ + cache-size =3D <0x400000>; + /* 64B */ + cache-line-size =3D <0x40>; + /* 16-way set */ + cache-sets =3D <0x1000>; + }; + }; + + dsu-pmu-0 { + compatible =3D "arm,dsu-pmu"; + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3>; + interrupts =3D ; + }; + + dsu-pmu-1 { + compatible =3D "arm,dsu-pmu"; + cpus =3D <&CPU4 &CPU5 &CPU6 &CPU7>; + interrupts =3D ; + }; + + dsu-pmu-2 { + compatible =3D "arm,dsu-pmu"; + cpus =3D <&CPU8 &CPU9 &CPU10 &CPU11>; + interrupts =3D ; + }; + + dsu-pmu-3 { + compatible =3D "arm,dsu-pmu"; + cpus =3D <&CPU12 &CPU13 &CPU14 &CPU15>; + interrupts =3D ; + }; + + memory@80000000 { + device_type =3D "memory"; + + /* Bank 0: start =3D 0x0000_0000_8000_0000, size =3D ~2 GiB (0x7F00_0000= ) */ + reg =3D < + 0x00000000 0x80000000 0x00000000 0x7F000000 + 0x00000200 0x00000000 0x00000000 0x80000000 + >; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; + + soc_clk24mhz: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "refclk24mhz"; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + timer@1a810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x1a810000 0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + /* Map child space [0x0..0x30000) to parent @ 0x1a810000 */ + ranges =3D <0x0 0x0 0x1a810000 0x00030000>; + + frame@20000 { + frame-number =3D <0>; + interrupts =3D ; + reg =3D <0x20000 0x10000>; + }; + }; + + gic: interrupt-controller@20800000 { + compatible =3D "arm,gic-v3"; + #redistributor-regions =3D <16>; + reg =3D <0x0 0x20800000 0x0 0x10000>, /* GICD */ + <0x0 0x20880000 0x0 0x40000>, /* 16 * GICR */ + <0x0 0x208c0000 0x0 0x40000>, + <0x0 0x20900000 0x0 0x40000>, + <0x0 0x20940000 0x0 0x40000>, + <0x0 0x20980000 0x0 0x40000>, + <0x0 0x209c0000 0x0 0x40000>, + <0x0 0x20a00000 0x0 0x40000>, + <0x0 0x20a40000 0x0 0x40000>, + <0x0 0x20a80000 0x0 0x40000>, + <0x0 0x20ac0000 0x0 0x40000>, + <0x0 0x20b00000 0x0 0x40000>, + <0x0 0x20b40000 0x0 0x40000>, + <0x0 0x20b80000 0x0 0x40000>, + <0x0 0x20bc0000 0x0 0x40000>, + <0x0 0x20c00000 0x0 0x40000>, + <0x0 0x20c40000 0x0 0x40000>; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + interrupt-controller; + interrupts =3D ; + + its1: msi-controller@20840000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x20840000 0x0 0x40000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + /* UART is fixed as 24MHz, both UARTCLK and PCLK */ + soc_serial0: serial@1a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x1a400000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&soc_clk24mhz>, <&soc_clk24mhz>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + watchdog@1a420000 { + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x0 0x1a420000 0x0 0x10000>, + <0x0 0x1a430000 0x0 0x10000>; + interrupts =3D ; + }; + + rtc@300d0000 { + compatible =3D "arm,pl031", "arm,primecell"; + reg =3D <0x0 0x300d0000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&soc_clk24mhz>; + clock-names =3D "apb_pclk"; + }; + + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method =3D "smc"; + cpu_suspend =3D <0xc4000001>; + cpu_off =3D <0x84000002>; + cpu_on =3D <0xc4000003>; + }; + + sram: sram@104000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x104000 0x0 0x00001000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x104000 0x00001000>; + + scmi_shmem_tx: scpshmem-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + scmi_shmem_rx: scpshmem-sram-section@100 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x100 0x100>; + }; + }; + + mbox_db_tx: mailbox@40020000 { + compatible =3D "arm,mhuv3"; + reg =3D <0x0 0x40020000 0x0 0x30000>; + clocks =3D <&soc_clk24mhz>; + #mbox-cells =3D <3>; + interrupts =3D ; + interrupt-names =3D "combined"; + }; + + mbox_db_rx: mailbox@40060000 { + compatible =3D "arm,mhuv3"; + reg =3D <0x0 0x40060000 0x0 0x30000>; + clocks =3D <&soc_clk24mhz>; + #mbox-cells =3D <3>; + interrupts =3D ; + interrupt-names =3D "combined"; + }; + + firmware { + scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 2>; + shmem =3D <&scmi_shmem_tx &scmi_shmem_rx>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + }; + }; +}; --=20 2.43.0