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X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: o8eMUe+RvmSmqS3giCgPmHQyvYr2216Gz6yyKcA0h//ZJrFp1poJnkQ+t5MxGfjmM3HfNC0gM/4Msk6MM8NR1iFpqIYy64xC1JLFCuJXwbVWmqCckzxP7VjRFZb4Vcaj3LWGJAUx/maCgGlrAl1FkqLjaS9qqEBwCr/viSrItNjesn0IaymfkG0upZTYFp1zVQ+IJhF+VJFBBmdGsZ1MYSOvwKcNGZF6mfsDNIjJunz9HUvwdykPgVMj7lV1xVOopV/0P9i1MatVuwoTTgsozhtF46i7pLT0F7MvvsDMrgf2SCK67pVfdNZBoaNFUpxDDKm7SvqN0Fg/Lb2mR9hwARa3/3UN0yBI8hw9GiDiHM5D3Yln9rCfShLpGPSw6B4S+bNEhOz3T8DmefpAmZ30QnMt2ClcbojLy7DIJ1fYgqaGn5xoTXyobjU2elzm7lwxyo2xNyzNYkslY8slg/GiBMajbBIze+v4l6F313i1mUkUrgOF9CKDudjqM9gJzB3sWZmWZgT2tt9iNQGUPHJTD/OHnlLT2smoiy7g8ZQiRFrawSfkNHu69gVEe//tF3uItalTybhtSEGcxHvqWrghksY2ewOIidHu2uhe//elrACNGIu07JkBL3Gtg4n8TECpqi0AAf5C61dVpij/neZg8tC2zPQXNjz/X5c9lLSKiqMVoHdgwESHnU/8jOPLZ3TMa2SqKmEZcrEnyFXGRPT3lA== X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 10:14:22.5431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 969e1a59-b172-4b17-9992-08de5a682de9 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB3PEPF0000885E.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR10MB3130 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32746g-eval.dts | 10 +++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 75 ++++++++++++++++++++++++++++= +++ arch/arm/boot/dts/st/stm32f746.dtsi | 2 +- arch/arm/boot/dts/st/stm32f769-disco.dts | 76 ++++++++++++++++++++++++++++= ++-- 4 files changed, 158 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st= /stm32746g-eval.dts index e9ac37b6eca0..26c5796a81fb 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -213,6 +213,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/s= t/stm32f746-disco.dts index b57dbdce2f40..ed0facce5841 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -140,6 +140,51 @@ panel_in_rgb: endpoint { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &i2c1 { @@ -169,6 +214,7 @@ touchscreen@38 { <dc { pinctrl-0 =3D <<dc_pins_a>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; =20 port { @@ -178,6 +224,22 @@ ltdc_out_rgb: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&soc { + bootph-all; +}; + &sdio1 { status =3D "okay"; vmmc-supply =3D <&vcc_3v3>; @@ -193,6 +255,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -204,9 +267,21 @@ &timers5 { &usart1 { pinctrl-0 =3D <&usart1_pins_b>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; }; =20 + +&usart1_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode =3D "host"; pinctrl-0 =3D <&usbotg_fs_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm= 32f746.dtsi index 208f8c6dfc9d..1fede5bdc347 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -75,7 +75,7 @@ clk_i2s_ckin: clk-i2s-ckin { }; }; =20 - soc { + soc: soc { timers2: timers@40000000 { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/s= t/stm32f769-disco.dts index 535cfdc4681c..b3a9e31f1da6 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -116,10 +116,6 @@ vcc_3v3: vcc-3v3 { }; }; =20 -&rcc { - compatible =3D "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - &cec { pinctrl-0 =3D <&cec_pins_a>; pinctrl-names =3D "default"; @@ -128,11 +124,13 @@ &cec { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; }; =20 &dsi { #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 ports { @@ -169,6 +167,50 @@ dsi_panel_in: endpoint { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 =3D <&i2c1_pins_b>; pinctrl-names =3D "default"; @@ -178,6 +220,7 @@ &i2c1 { }; =20 <dc { + bootph-all; status =3D "okay"; =20 port { @@ -187,6 +230,19 @@ ltdc_out_dsi: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + compatible =3D "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; + bootph-all; +}; + &rtc { status =3D "okay"; }; @@ -207,6 +263,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -218,9 +275,20 @@ &timers5 { &usart1 { pinctrl-0 =3D <&usart1_pins_a>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; --=20 2.43.0