From nobody Mon Feb 9 06:19:24 2026 Received: from GVXPR05CU001.outbound.protection.outlook.com (mail-swedencentralazon11013069.outbound.protection.outlook.com [52.101.83.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF76737D123; Fri, 23 Jan 2026 10:14:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.83.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163272; cv=fail; b=Vk6fqVsSWqZnNVVY5iVBbQQPhsTatLr2vmC8G0GQJblmKNnEIoL8mJMamWrhOKO4qZ6VllxheIjIHFC5Vf9DlZjk57EjsRPA7a/S5Hha2oTJZidZCtceD7EK9Gb3Crk1rSBQSvVb8gq0EZaPQx4zcRCzWhURC+Cl0c/FE5nwUw0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163272; c=relaxed/simple; bh=tSAb46IvfHy2cYPeOUN3z8p6WwWr5+JjfWnW6VsVmN0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ruZide2IKYrACzbw2g+R8OwfZMlnPy1xLiT4y5mBwxvmfrIDFl0OyC36Nb/SM9CAug20XWtuEX5LPUysefjxjPkM0pWZHwOAI6ay2IDySsfJDBoMesPA2R21wGaSKstbpAi5wVI/zBfUKmm8e6ZJ+nvzFlyCBGi9WV8ueoncaz8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=AAY3Jtvu; arc=fail smtp.client-ip=52.101.83.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="AAY3Jtvu" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pWDWXN6ptNCHDkUHPRyp9RlAzey1VNfZdVZORQhppUp3kRmaGuzqkwx8Q4/c2yAJjokasHeat+49/R0rxDZpryRd51BteOaKipCG//mp4IMRSFEZJbDjb43nKMUHydaekbvIP5HuZNIX/QiEk9GYtom+oe7+MmtnDy5kDjUB7DGDveqTRdmeqbOVwDvmKPOlJBZxKQ7nkAajw09TZad2Muy4L0fl7ZWRD4GhMhqSWq/tEvKIGfujg0JieuvJ+e/hqlfpLrz8eh0xGuB3SkmMiPTAlrP1KKSXlGQkZhfh3D8kiHkoFkp3ntEGeTGsxUySkrmysUGzzU4e162axiyHSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pbI2pYoXWbyIs+8vi4PX5+0ck2F6/PE3QP7yAWmyBvo=; b=WM8FP5VQdnPm6js4KgxmAWtK8P1ShVFl47rpuNfwb+LSoJqosNWT4O+3zuZYYzb8jjbKivmVnrw4Pk0X/vfX3Rs8ghttqSIYmkHSU6KH9MhDV310+x+tDwCDaUtshDUahXVd6XUQuz0JkBpeTAHFTo0FetnMRw3urNkjqA3+TikEO4kfTIcyYGNc8++MOg81gux68vR3oM31nrh/aeRIBA8YMYQl/Lbr5wxyH7mAsI98iKtQOPVdHMFB4a0yqgsE6h9/HFUdyh5U2j4/tVz8ec5q/hLJIJB+v6/bdMgW3sWeiUThr4Tj0sqfNDDn8bxwu9tbzV445487XBum0BGrvw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 164.130.1.59) smtp.rcpttodomain=dh-electronics.com smtp.mailfrom=foss.st.com; dmarc=fail (p=none sp=none pct=100) action=none header.from=foss.st.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pbI2pYoXWbyIs+8vi4PX5+0ck2F6/PE3QP7yAWmyBvo=; b=AAY3JtvuiJGXRrp9PPgosN5h2wtOpU65agvl3yStIwwZnb0NDU3YrVB6EwiT6t3swUlr6K71znrLbBpDVAGp7dEVYFThbu4vKrnOjl+xywMfryvpC4070/aatiHxw5tW3eoG/bBisgtgtSey+kT8lii2+Vu3Qu3GJ12b4ViYrnegYWzM11u1sBkFL+IQzsJvrCBMeq6FdaO3nAAPvoTA/QS/l5ZOA53pQx42ht3nYaz/Y+2dBqy7PJ9Lb59l9vRe5zguf7DvBstNviryYgNpOXAKQJ93Te119EBKqRFBZtreZD1n3hqGx+wq53qXMhVRSeCMgoLgc2J6/pkWeCtjfw== Received: from DU2PR04CA0081.eurprd04.prod.outlook.com (2603:10a6:10:232::26) by AM0PR10MB3490.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:154::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.11; Fri, 23 Jan 2026 10:14:21 +0000 Received: from DB3PEPF0000885E.eurprd02.prod.outlook.com (2603:10a6:10:232:cafe::18) by DU2PR04CA0081.outlook.office365.com (2603:10a6:10:232::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.12 via Frontend Transport; Fri, 23 Jan 2026 10:14:00 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 164.130.1.59) smtp.mailfrom=foss.st.com; dkim=none (message not signed) header.d=none;dmarc=fail action=none header.from=foss.st.com; Received-SPF: Fail (protection.outlook.com: domain of foss.st.com does not designate 164.130.1.59 as permitted sender) receiver=protection.outlook.com; client-ip=164.130.1.59; helo=smtpO365.st.com; Received: from smtpO365.st.com (164.130.1.59) by DB3PEPF0000885E.mail.protection.outlook.com (10.167.242.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 23 Jan 2026 10:14:20 +0000 Received: from STKDAG1NODE1.st.com (10.75.128.132) by smtpo365.st.com (10.250.44.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:15:36 +0100 Received: from localhost (10.252.18.201) by STKDAG1NODE1.st.com (10.75.128.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:14:04 +0100 From: Patrice Chotard Date: Fri, 23 Jan 2026 11:14:03 +0100 Subject: [PATCH v5 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260123-upstream_uboot_properties-v5-1-5167929d5af5@foss.st.com> References: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> In-Reply-To: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB3PEPF0000885E:EE_|AM0PR10MB3490:EE_ X-MS-Office365-Filtering-Correlation-Id: 703045d0-1ff1-4158-86db-08de5a682cac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?cm5kS1U0U0JlUHh3UzFydk9JRDlsNHhEalpweWxXR0k3c0pFbzFUOUZ4TTF0?= =?utf-8?B?U2ZsYWF5Mkp0TWNZK1B5ajd1Zk42ZzJPVXpwK0xhZ3RvZkljRXpWUEJ5SGVt?= =?utf-8?B?ZVJ6V2pMU2ovcC9WKzB6VG02SUZaYW5LOEtkSms5aGROaS9XSUt0eGJ2Tkx0?= =?utf-8?B?ZXFjeXhBMmhkRmM3UlVlL1pnWkFzVmtVc2IyckpBQmpWU01IYjhxdEFrdWpE?= =?utf-8?B?THBvTlFnV1YwcUFsc2hGVlVCZEdyRTZWTTlGTkRQOXdUQlNpQWRKV3FtejUw?= =?utf-8?B?WE43ZjJ5NWhiSC81YXczL0hBcnY4d0lLSHVvRUJpK3Zxc242bHFmNVJSbktW?= =?utf-8?B?NVdwR1R3SXNWZjlhQk5CU3U0dEhTcmlUZlpYeDdURWtTMC92R0ZJY2krMUZW?= =?utf-8?B?TXlVK2Z5YUZWRzIyeWFCWGhkMGtLOER4cnFXc1RqcjRCRlIzbENYQ2JHOE1F?= =?utf-8?B?akZBbGpsUVJaOUNvakl6SHV5SXpENmlBZmJROVZsbHpXbGxkTVdhUENXYUp0?= =?utf-8?B?QkMxZGhWMndiblhMa0tuZmV6UEZmY0ZRL0c3V1ZJendZb0NENFplYzlaMUVy?= =?utf-8?B?TUp3bGt2eVBzTTA1RTB3dE5ON2h3eTVtbVRPOHd0WGxRSEhKVGdaL2tmZFBM?= =?utf-8?B?NG9GWVlDS2VqeGxBM2VhMGNOcFVZSzBwSUtMTmpuMzh5QjQ0MjRpT09wUjVK?= =?utf-8?B?Z1RxbHBpU2pKWG1oTVhIM0o5L3NpODcxK1dqNDhpdVIvRE02RUVEb3dWTngx?= =?utf-8?B?TGRUcHVoK2tydHEveDJmL21SS3pzUjVZa0ZPR1pMbHNaTWFISVc2SXk3OUxF?= =?utf-8?B?NXArVlptSGJ2SUZvU3NzLzYxQ2tFVHgyZW0xTGtpRFF5bEgrUDNqWUZXSkhC?= =?utf-8?B?QnlYVDVvRjh3b0NyTCtSUEdkbE5xOGRBQ2FjV1pFdWVFd0hXeG9mTmQ3VlN3?= =?utf-8?B?Zm8rUTFvNi9DYmR1VTREQlVzVzFUTldtQUM1UmZrZHBGcWl5Y2dpZFBEeVpn?= =?utf-8?B?eWcvdmp3VmRxMW01TWJWTTVORFBrNHZVZTV3NTlFZStBQnkzdDFJTHZRamZE?= =?utf-8?B?eXdBbG5VeUQrejdZQ21QckZNQ2lYQ2JQaXI5TjFoVmFxQStjL0M3dlJRSGVs?= =?utf-8?B?aXJjTDdoY09QV0p4Si9ZdFI1OGdIblhCOEllQlYvWlpuQVZaYWxRWktZOENJ?= =?utf-8?B?Rlp4a1NuMm5EN0FZRlMzMlNRRkZkN0I3OGovd2ZmQnduM2pJVlVzbGdWUVJU?= =?utf-8?B?N1hoVmFOa0pMRzZNVEdzUjFCTHRlUHRwM0c1aldhaHB5TlpuSDBSK0UzUGpR?= =?utf-8?B?eTRkWDh3K05vWG1QOXlLR241ZWc0VS9BWHl6UzRZUmpxTzI3ODJUYllvV3Bh?= =?utf-8?B?dm1wczZKckdrSDNNMFpyMnFUbVFKMGttbmRYSVBjcFhvREJiS3NoMWpzeFMr?= =?utf-8?B?SFQxbjFVTFZqK050bFVwZ0thZmRWV1MycEdYdVF4QkRRQzIya0Nrcjg3YTVu?= =?utf-8?B?U1czRmR3NU1wU3F3YXU1YnF2MGFzL0F5MmxSclNQRExCNHlZckpReGtyUWVM?= =?utf-8?B?NFJLWHRJRGhmdHJQYWQyUXBJUVdIZDdJdGd5a1V1MUZGQjF6Q0ZxTkExSnJq?= =?utf-8?B?MDRrOUlkRTd6OU1rcDd3eFpPOFVXSmJ6bld6VHBWY3g5M3AvSHZoczJpcVky?= =?utf-8?B?NUxQNVlxUmtTaE0yVVgwWEVjaER2VURJYXhxM1g3eTVGdjZBNFdJYnhvWE10?= =?utf-8?B?aXlEcEhEQi91Wk0rbDU3ZXJrSFZUM1hwRzJ5WGFsZ1FnTkNJY2M3ZG9pNDdK?= =?utf-8?B?MEdmU3JVSlp5QTNGY2pPcmlJMUEvVFhJMG42SUlLSWpkNGhrRXI2ZjhEdnpI?= =?utf-8?B?NUZyMXMzUG9IY3ovb1ozZjk2WHcrMnlqTFJma3lVajhhbWE2VjBDdG5xQ1Rr?= =?utf-8?B?K1V5RkJjVHFDd0x4VFhpYlBuV0dlMDFkWnhWMjd6bDdxclAwZHNjL0JvQlFi?= =?utf-8?B?OWx1eXYvUDRRQWI0Q0REOTdJdlVNQ080RlFGLzIzMEFva1lGN2ZuSFQ0MVll?= =?utf-8?B?UVhTVFJldmFVUUZ4VkN3ZytjTTZDRHNRdlJlUDU1M3EvK3hhb0Z0VnNGOE5h?= =?utf-8?B?MzFxRlVhUHJPNStDNjFWQVJBQ3pZS2ZpYWFBS3ZDeUJJZFMrdkV2U0hWek9z?= =?utf-8?B?TDFEeUdvWUJwYnN4bXBCLysyWHVibmlrbTJKVEs2SlJKU215aXNsUWduNlBW?= =?utf-8?B?Z2REdCtYVkV4L1p4ei9NelpjNlZnPT0=?= X-Forefront-Antispam-Report: CIP:164.130.1.59;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: TSKLI1NRQ2Lsq1whfCxpZfjsPDw/0aT9Z5jQTqPd8J8DrC+Ptb8yGK/0LkRnTpwbhubcG37/od8a9586cqbAirWNrBnAWJgQUVVF918Y6M0NYUzPzApfJVQxo+C9Mdh4e+435QUMsdW/GGE2A8dT1lZE64PM8IJwrcX8TIKCwH0ZdUsAC6apmmf893CUQ0K42zTJ2PMgDmq+uERovQ7RODbfTiFjQOPCPptvXqQv3zfxjHGIKwFMM8NfeKvfnZHFKFyPprylCLR7XCVJb7/+w7Zlv4fvcU8fvIX+lBLZtlhQSAvJVYiVoGCrqb+KpoXpv33oHTEF9S9gH/8SBNVr2dvttKCZ96c5zdiiON61v2zzsqcF+kH5QvS06xWnA69uKwqBONhsF1i/aMb0x/kKUAld2FxdDmq72impE2d1zqbVBLdbsIhtJvbdF5vvpgg2BzoSOLDBitpBM3I1SPKZURi6id+1ZF6PBqhMbBD4Qkbl4PZ/RfiydA+ntHeSXaeWR/3agpxVvMmT5tgzSRiN7Br3pjPFmEg1kKAdDRRdQL8x55WhOPNC9/sKb/zdz8iSfjPec7bu0FixDafntwg90V20IqpHG/m2iAVDHfiPDeqUSpqsM55hND8PK5V5ehknEvkbSupSfbhJ+Yh8Flk/WBqdOIX1m8ebcTHcdqr2x2IG6RSWvGh4Yz03H/hDM2PKpCBFjdetMJsjHlozYe64IA== X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 10:14:20.4692 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 703045d0-1ff1-4158-86db-08de5a682cac X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB3PEPF0000885E.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR10MB3490 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32429i-eval.dts | 80 ++++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32f429-disco.dts | 80 ++++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32f469-disco.dts | 72 ++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st= /stm32429i-eval.dts index afa417b34b25..05cdc3d9d015 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -175,6 +175,15 @@ adc3: adc@200 { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; =20 &crc { @@ -196,6 +205,50 @@ dcmi_0: endpoint { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 =3D <&i2c1_pins>; pinctrl-names =3D "default"; @@ -265,6 +318,18 @@ phy1: ethernet-phy@1 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status =3D "okay"; }; @@ -280,6 +345,10 @@ &sdio { max-frequency =3D <12500000>; }; =20 +&syscfg { + bootph-all; +}; + &timers1 { status =3D "okay"; =20 @@ -312,6 +381,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -326,6 +396,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "host"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/s= t/stm32f429-disco.dts index a3cb4aabdd5a..75c1de0b0496 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -102,12 +102,65 @@ vcc5v_otg: vcc5v-otg-regulator { =20 &clk_hse { clock-frequency =3D <8000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; =20 &crc { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c3 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c3_pins>; @@ -165,6 +218,18 @@ ltdc_out_rgb: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { assigned-clocks =3D <&rcc 1 CLK_RTC>; assigned-clock-parents =3D <&rcc 1 CLK_LSI>; @@ -205,10 +270,15 @@ panel_in_rgb: endpoint { }; }; =20 +&syscfg { + bootph-all; +}; + &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -223,6 +293,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { compatible =3D "st,stm32f4x9-fsotg"; dr_mode =3D "host"; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/s= t/stm32f469-disco.dts index 8a4f8ddd083d..8d089546c0cf 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -168,7 +168,52 @@ dsi_panel_in: endpoint { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + <dc { + bootph-all; status =3D "okay"; =20 port { @@ -178,10 +223,26 @@ ltdc_out_dsi: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &timers1 { status =3D "okay"; =20 @@ -225,6 +286,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -239,6 +301,16 @@ &usart3 { status =3D "okay"; }; =20 +&usart3_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode =3D "host"; pinctrl-0 =3D <&usbotg_fs_pins_a>; --=20 2.43.0 From nobody Mon Feb 9 06:19:24 2026 Received: from DU2PR03CU002.outbound.protection.outlook.com (mail-northeuropeazon11011032.outbound.protection.outlook.com [52.101.65.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EB7B37E2E9; Fri, 23 Jan 2026 10:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.65.32 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163283; cv=fail; b=e/IzMq2uLn2PFV8j72eC4Ly8BTUvV4QMpamCJ8mvALTuPv3GMOh8f5P/cYgGgkG4qxyYA7V2R4eHV7qP1QJWe1aRJ70OE1OCVEvz73GDHawxeWS49KU9yzZ43uZaLNlCeIGyXYcyE4ZpqOSO6s8aNYMGyxnNb/E/MHLzHhwMk6I= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163283; c=relaxed/simple; bh=o21G7jrGQMXeD+iuCPP4ZSdggnHTpMDP8p+RG+KKfAM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=BocvkqAKPCnCJjfL4ljJRGa1yJA/hRcD+VUtA0/b57JyLeSYiYHEuiG7vr4czyGZ70XdAjI3Am4/kOzwkJivmwOsZdW4DK+ZPtChF74OK/oPVfq76GMPYCcuP1D/Zh7uvWKqKWsVx1um4nPuE2IG9gPy9PFW2XpsLCVIbKky91I= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=MhwGzFSQ; arc=fail smtp.client-ip=52.101.65.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="MhwGzFSQ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=mkuQcVD+jrrT7S8lr67XmO+/SL6XSgV1lZNo+Gq8gPDTs70ach+AQhmZzONiOr89qZQ5cYsBjzehg/ftQ5WZXsoRMdUeM9YiL447zLd2rEuoutuFC/AfHiDhImsSbQUm0gNEDPzgKyp7brTEOnlvvmwOJh0Ddba6CgAbeKuQECVL16sElRwGYCLn6mMa5W4od0E1RtbzyrqTxgD6pRt+G06PHobFw8mvWwdKalfsNR46ohF56V9SO/8JbgPMMRY0UfPKhSleyBFuVof3WGVb1ghye1oGklCXndqQxIfQIWd1Uo9aU1vlUNLnPDJ/qtzAGP0XEUVG3M1Ov7cW9hULwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0vztEXZgLuFMZzQdH6REOvr7/N82B/oV2IH8pAdK5I0=; b=ohpST5qdrpA0dReJFnjCKgt933alSznc9cl4EJATlQgjbSeSuhnx3v4LNTVcXfeTrrnRp/QzhZ8oz8cZe5daymg+5k0A81rTiQLYfs+jg/H8P8h9SjkZ/yy9/gH6gxSofqmBzneeh6AyKppQ7LwK8CBH+mRHJzfzUU55+IF5chjn4q8S6RI34u6THdX2x4nldo4jYW4OLrmILX5YyCmEVRziV8oOSK/k3ff4zeefcuusroyscSwOJji2Qpyo+1uActusUs9OTBUKLoPGNICOYt+Omk5Q8Oq5MRR/Ogqep4Zq9tzUO9GflBvfpZWuRsqtQu5rg/2GtsVkO6YkssoUTw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 164.130.1.59) smtp.rcpttodomain=dh-electronics.com smtp.mailfrom=foss.st.com; dmarc=fail (p=none sp=none pct=100) action=none header.from=foss.st.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0vztEXZgLuFMZzQdH6REOvr7/N82B/oV2IH8pAdK5I0=; b=MhwGzFSQo2ppwGXqBPor68wKhrZwv0DUnS9dkQisYqItHzKAvK53d61zGCDuE3jg+HNeisKIXLcOkD9JVRYMioefdeTEQ2TppT1jgvjaXMdTeqoo03azxlbhjapYC6oMCLF3hGIhNeD3IBos4LEgZQ5P4Qf9PAAV9/yVt45vdNf5Bm7nivoPdNSxF6GXo8YhAwJCPD14peqRTq90sEJEPFPd533NzIqhq5fBCAHEvFHnIKMJtwXdptkhdIPXKjFvz5Z1+IIbh4ucQAmhMF0ipaDpsIp0P8HWbfMSrn4curUAM8Z5sUJG9/W2JAcphe92sGEcVM+6Pr7Yt5pWQ+9TQA== Received: from DU2PR04CA0075.eurprd04.prod.outlook.com (2603:10a6:10:232::20) by DB8PR10MB3130.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:10:f9::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.9; Fri, 23 Jan 2026 10:14:22 +0000 Received: from DB3PEPF0000885E.eurprd02.prod.outlook.com (2603:10a6:10:232:cafe::8c) by DU2PR04CA0075.outlook.office365.com (2603:10a6:10:232::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.11 via Frontend Transport; Fri, 23 Jan 2026 10:14:19 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 164.130.1.59) smtp.mailfrom=foss.st.com; dkim=none (message not signed) header.d=none;dmarc=fail action=none header.from=foss.st.com; Received-SPF: Fail (protection.outlook.com: domain of foss.st.com does not designate 164.130.1.59 as permitted sender) receiver=protection.outlook.com; client-ip=164.130.1.59; helo=smtpO365.st.com; Received: from smtpO365.st.com (164.130.1.59) by DB3PEPF0000885E.mail.protection.outlook.com (10.167.242.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 23 Jan 2026 10:14:22 +0000 Received: from STKDAG1NODE1.st.com (10.75.128.132) by smtpo365.st.com (10.250.44.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:15:36 +0100 Received: from localhost (10.252.18.201) by STKDAG1NODE1.st.com (10.75.128.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:14:05 +0100 From: Patrice Chotard Date: Fri, 23 Jan 2026 11:14:04 +0100 Subject: [PATCH v5 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260123-upstream_uboot_properties-v5-2-5167929d5af5@foss.st.com> References: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> In-Reply-To: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB3PEPF0000885E:EE_|DB8PR10MB3130:EE_ X-MS-Office365-Filtering-Correlation-Id: 969e1a59-b172-4b17-9992-08de5a682de9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?VEF0Ym5iRlBNRmZhVjMzNnhEY0tvUy90UWFUOC9vUU93ait0NkxKZkxWM2JU?= =?utf-8?B?S0pUdU9sMTZ0OW1TeEtQbDN0MVhuTFdMbjdKYTBoS04ySHMyVThNWnNzSWJL?= =?utf-8?B?ekE4a1MvaENBVGUxL0ZSQnJ6Z3IwTkV4Mm9NR2pmS0poWXovTUROS0hQZkVF?= =?utf-8?B?N21HVmpLTlhxVDBvZDZSYVcxOEpZb1AzbEtsTHRjNWZQZWVRTUlYVkdIQnN3?= =?utf-8?B?L25pYzd2akV5TTlad2FvbHRpeHJ6bHJUcE1ITXBBZytzWHBMSllxRDR5SmtK?= =?utf-8?B?MjJZOVVvV25YOXNxQmk1N29RQUxGUi9YMWZ0MFZ1RGU5TGNvRm9XeVBWbmlq?= =?utf-8?B?a09JTHhFcTBLM2NyeE5xTm04MlI3ck9yWVJZU0Jka0V0R0RWQXowNld5RnlQ?= =?utf-8?B?djExMklhcGw4dzBZakhMRVB6Zmwvd0R3eVEvbno3QlQ0OHIzMEtRT0J5WUF6?= =?utf-8?B?UHh3YVl1bnc5aDM1Z0paMm1mMFphc09xaE5IWDhweElWN3ZmOG1QQTU4ayti?= =?utf-8?B?QVZpWFRJY2tSVGFLQlgxdTVUeXJ4cCs5RnBJckdBMk5NZmhFekoxTlE3eFAx?= =?utf-8?B?UGxVWk9uVW1YRUFiVHN6SWRLSlA3M1c1L29rdHU1NGkybHNCeGFxMVBTNXk0?= =?utf-8?B?RmZySy9iZ3dEeUFmM09aZ3puRFhJMkVmeTdlbkVUNldJVFVJV1pSa29JWURW?= =?utf-8?B?UlNNSFVmNHdVdUg0cGN3YTRwK2IxVzdIeSt6RjBZUGZHellyOGIyczJjYUFN?= =?utf-8?B?NmcyUjRJYm5qdlA3Wk5qcGw2KzQrRVA2Kyt3TU5kN3pQOEJIU2ZGdHBHckFS?= =?utf-8?B?L21CWnV4aFF5Q1Z6dC92emp6YWc1cytxWU10SDVHQndrNGg3ZmM2MjVoaHNX?= =?utf-8?B?MlVHQ241UEFFcjJ3TW1YZzNvSVllUDZzcEVkUmI2NFA5WmZPNXNxUzlFeDVH?= =?utf-8?B?aE9aV1AwWlRaU1JYTlRtem15N2ZRSmd1dEhYeXlCSHFLSUdsUTRreDVCUU1S?= =?utf-8?B?ZEtDYzE4ZWk0c3oxM05FeDYrS091cXpxQkFNMVhWZ3phQUU1SnFFa2owbXIy?= =?utf-8?B?dUJsd1FiVlc2TTluS0VKaVBXbXRpOVNFc2F5blNmT2MwU0l4eTdzcjFFUU9H?= =?utf-8?B?dU43V3lQbitaN05qZUdEdFF6RWc0ZC82L2t3akhhR0xwMGcwblZSR1A2VXdK?= =?utf-8?B?ZmFZZWwzSWtrSDhTRkppWXZxa25XSzhKQTZkYVRCQVVXbDJ3NitGUkZ1WWdB?= =?utf-8?B?b1Y3REx0bGdBU1JZeDd5YXhKWkdEVWNpQ1c1WW9OWlQxZlhpRUdHRTdYQVZK?= =?utf-8?B?ZVpMUFVycGp4ZkhFeldQeDAraWlhbmlhTng4N1JkMDNkNGlUZWlRNXdmMTBE?= =?utf-8?B?bHBjRkJYTDBpSkloLzU3b3lpaG4wT29tN2VtZ0tXNS92UVZqL0VhVm1SZjgv?= =?utf-8?B?MVpPdjVqRDdYeDMrTFh2eitCRUJrbDVVejY3Y2RYWmlnTjFKSldsRU15MWVH?= =?utf-8?B?b2xwTUN2clEvUWVtdGI3S2ZYelh0cjdoWFduZ2k0eHVpdWxwa0p3U3g2eXMy?= =?utf-8?B?MXg0aTJoZzhFVzZZTnBBcFYwL2hxWE1TNE1NL0RBeEZVUHFHaTduYzcrbklt?= =?utf-8?B?SCtEUnJncVRmcWZ6Sng1eDFSSm94MDRqOHFsN0VGOVpRdWlhV2JQWXd1RVF2?= =?utf-8?B?TmNVVXF1NWZmYjl6dkJQczhOaXR2ZW5zRGl1Y3ZsYmpCR3haY29mZ29HbmZB?= =?utf-8?B?OGIzYUVsVm9MLzhWRkpsZE1xYlQzWlhabDByTnhpTUJRcjhhejFMZ2Vnemdz?= =?utf-8?B?NVY1RUNTdUVQK3BiMTBuOWw1RUhOMFIzaG45YldGSlNhaUhXQWZUcVZpQ1Js?= =?utf-8?B?dWFSSld1R1A5Qzh3QjYwYjdnMnM2V2UwOHZvRFlNTzdDbDhZRzVSd3JackpC?= =?utf-8?B?T1VOaXVZZ1h1ZDdMckFNN2d5WWEvVER5Uk91endlejlwbXhuMmZqYUxRRnNJ?= =?utf-8?B?cXd5TXZYcVVlaVJMNVVBSFYwVnJoTHoxdEJ1RVZvY2o4UTBKeGJSS09KQWVQ?= =?utf-8?B?WDFrL1lwUFhIZGZTRzRvZlJEVWdJeFJkTG5HdTlEeklrNU5sTnJmU0VpbzhC?= =?utf-8?B?ZE5KQkZvbGlhT25ON1JidFVBay9aVGQ2TGNNNkpxVEFwMWlhWmZld2xlVGpn?= =?utf-8?B?dktGMGcwa0Y3MjNBa1VGN21DOU9OTzdoSlJLRU5yWXQweWlFZ1ZSWlpuUFNG?= =?utf-8?B?YkFUMG9abC8xRTd5Rmg0TExnYUV3PT0=?= X-Forefront-Antispam-Report: CIP:164.130.1.59;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: o8eMUe+RvmSmqS3giCgPmHQyvYr2216Gz6yyKcA0h//ZJrFp1poJnkQ+t5MxGfjmM3HfNC0gM/4Msk6MM8NR1iFpqIYy64xC1JLFCuJXwbVWmqCckzxP7VjRFZb4Vcaj3LWGJAUx/maCgGlrAl1FkqLjaS9qqEBwCr/viSrItNjesn0IaymfkG0upZTYFp1zVQ+IJhF+VJFBBmdGsZ1MYSOvwKcNGZF6mfsDNIjJunz9HUvwdykPgVMj7lV1xVOopV/0P9i1MatVuwoTTgsozhtF46i7pLT0F7MvvsDMrgf2SCK67pVfdNZBoaNFUpxDDKm7SvqN0Fg/Lb2mR9hwARa3/3UN0yBI8hw9GiDiHM5D3Yln9rCfShLpGPSw6B4S+bNEhOz3T8DmefpAmZ30QnMt2ClcbojLy7DIJ1fYgqaGn5xoTXyobjU2elzm7lwxyo2xNyzNYkslY8slg/GiBMajbBIze+v4l6F313i1mUkUrgOF9CKDudjqM9gJzB3sWZmWZgT2tt9iNQGUPHJTD/OHnlLT2smoiy7g8ZQiRFrawSfkNHu69gVEe//tF3uItalTybhtSEGcxHvqWrghksY2ewOIidHu2uhe//elrACNGIu07JkBL3Gtg4n8TECpqi0AAf5C61dVpij/neZg8tC2zPQXNjz/X5c9lLSKiqMVoHdgwESHnU/8jOPLZ3TMa2SqKmEZcrEnyFXGRPT3lA== X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 10:14:22.5431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 969e1a59-b172-4b17-9992-08de5a682de9 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB3PEPF0000885E.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR10MB3130 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32746g-eval.dts | 10 +++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 75 ++++++++++++++++++++++++++++= +++ arch/arm/boot/dts/st/stm32f746.dtsi | 2 +- arch/arm/boot/dts/st/stm32f769-disco.dts | 76 ++++++++++++++++++++++++++++= ++-- 4 files changed, 158 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st= /stm32746g-eval.dts index e9ac37b6eca0..26c5796a81fb 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -213,6 +213,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/s= t/stm32f746-disco.dts index b57dbdce2f40..ed0facce5841 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -140,6 +140,51 @@ panel_in_rgb: endpoint { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &i2c1 { @@ -169,6 +214,7 @@ touchscreen@38 { <dc { pinctrl-0 =3D <<dc_pins_a>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; =20 port { @@ -178,6 +224,22 @@ ltdc_out_rgb: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&soc { + bootph-all; +}; + &sdio1 { status =3D "okay"; vmmc-supply =3D <&vcc_3v3>; @@ -193,6 +255,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -204,9 +267,21 @@ &timers5 { &usart1 { pinctrl-0 =3D <&usart1_pins_b>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; }; =20 + +&usart1_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode =3D "host"; pinctrl-0 =3D <&usbotg_fs_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm= 32f746.dtsi index 208f8c6dfc9d..1fede5bdc347 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -75,7 +75,7 @@ clk_i2s_ckin: clk-i2s-ckin { }; }; =20 - soc { + soc: soc { timers2: timers@40000000 { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/s= t/stm32f769-disco.dts index 535cfdc4681c..b3a9e31f1da6 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -116,10 +116,6 @@ vcc_3v3: vcc-3v3 { }; }; =20 -&rcc { - compatible =3D "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - &cec { pinctrl-0 =3D <&cec_pins_a>; pinctrl-names =3D "default"; @@ -128,11 +124,13 @@ &cec { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; }; =20 &dsi { #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 ports { @@ -169,6 +167,50 @@ dsi_panel_in: endpoint { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 =3D <&i2c1_pins_b>; pinctrl-names =3D "default"; @@ -178,6 +220,7 @@ &i2c1 { }; =20 <dc { + bootph-all; status =3D "okay"; =20 port { @@ -187,6 +230,19 @@ ltdc_out_dsi: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + compatible =3D "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; + bootph-all; +}; + &rtc { status =3D "okay"; }; @@ -207,6 +263,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -218,9 +275,20 @@ &timers5 { &usart1 { pinctrl-0 =3D <&usart1_pins_a>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; --=20 2.43.0 From nobody Mon Feb 9 06:19:24 2026 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11013041.outbound.protection.outlook.com [40.107.159.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21B1935D607; Fri, 23 Jan 2026 10:14:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.159.41 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163276; cv=fail; b=ohgJSAd9dCd+nBgZpMvfjSXzYIcR6F1mK23jrVJS0AfCo1Sbp6XMD2LdfrOC/m51KExWGfNNZ3TiJW6oZ3OjgGiG4YfszvMmWnPC3YMjh3b/EJViYM85OXNgGSEvNM2roSyW2qsCpCk/83YDnUVrcIUJOluxlYoh+OvGt2a+ofY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163276; c=relaxed/simple; bh=TqGU0o6u4NtqOKVZF5LwZtD2/CP7Tf8jfoNo1arjF9I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=KWi6V5tb63ThmGfWniqrAmj+SYRLGc8RM4DkvGPPt4fHTGa6FQiQo0xXIZYkZ74bj0iOjQimCv9QtlsIIkr6lxKZTVz3lypSdqvVJSsm3Bir4wBoAmwSmcwA1CaHt3geje+NyzP+Quknw+scVW9XHr2/iuyHL16RzSUK0k6czgE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=augjAaoE; arc=fail smtp.client-ip=40.107.159.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="augjAaoE" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=u0AEooozk4hMZR6x8Nv0A5GopYmjzfDostTy4eueuPkgxpRMfTDwKKpH53YnMO8Mb94IkSaHvhvg+BusBBh6Rvz5cKtFbrcU/meyHz8WWb42QFMAqdhTCsa7eYnULcLYJds8jwTBri4W8T2Lo1wKyzD9YSojVHNY2tOsaYGtc4inY4EPOWqh/6z+UpCocJDIUMasa9t4OzlOtje5b0xOxB7Ol+wFEu4xsuxPUi8qjqnCchV93Ov9qLgYw2BWeObOO3AC1TafRPvFEET0LpYwaqwQfITA9pDPYhw9pia5kT9ggGHBaG0Z+9XzSQ8YgBv8leNSClVNl4xd09XwfKhxhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pjRn17qTj5JIzb79hd2QW4bSxWOXcG7YBW2By7jO6Ro=; b=xaXEvOsrKGYC+due4bjDUyb7o+1rZY0ZC2Pey+HepmwuMu87ZOUeCq3NtdV2rd3zrTxrvgFSKE1th1IYzbAtosw5dyuc5PxbJMf/P+d/jMgcmbnKTy8TjtXIswh31i57vBM+DC76OFegmgUtNUlxDG6WRAJtMTVNtiCY4mLipCttbd0mMLnxT8+fSf9cET4lchvN/Ej+5z777O6vC2pX+2ffrfQkA2LGVrPx62gBxupNZPjwnpBnTVl0HC0Wr4YGpAJI17M5dTqMCewhxXWku9ryIk4Nyx6Fa6kX/wQzYeTyyTVbqgCZNf4vuC5s45ksO5SOKc8bPxhpRpIeC/n5fA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 164.130.1.60) smtp.rcpttodomain=dh-electronics.com smtp.mailfrom=foss.st.com; dmarc=fail (p=none sp=none pct=100) action=none header.from=foss.st.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pjRn17qTj5JIzb79hd2QW4bSxWOXcG7YBW2By7jO6Ro=; b=augjAaoEUW3lkQw8N1sosV8CJwUClydgsBoHQ01TgoN/RdRk7TaoYkZMu1Nf+ZqaUUYgTIT7nNWSx7hJ8+y3E3VVtNNUrj7sAg0IHtROqzYCliYDum/8w5UHrLzaB2H0PSmF0mZszpMg3qM/SX2lSPvneBFRA85Ef1ZzqYBUTfgbQKmTtwsWAbMtyjX4W++u+3A2kPdj0j3W/OUjLANQDyrEivzLX4nVnFpSOrqXlQKQqPege/B/dVUjyz2hKGOO8ZmRvmIc4lmUDFkzIuJ9Ym1nZo4lKV/6PV6y3R4xM/IV99WnPPx+Km1HzLOXOcog3skXVZhIN7ZMIGc5a22dsQ== Received: from AM0P190CA0017.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::27) by AM7PR10MB3939.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:171::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.11; Fri, 23 Jan 2026 10:14:18 +0000 Received: from AM4PEPF00027A6B.eurprd04.prod.outlook.com (2603:10a6:208:190:cafe::3c) by AM0P190CA0017.outlook.office365.com (2603:10a6:208:190::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.10 via Frontend Transport; Fri, 23 Jan 2026 10:14:05 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 164.130.1.60) smtp.mailfrom=foss.st.com; dkim=none (message not signed) header.d=none;dmarc=fail action=none header.from=foss.st.com; Received-SPF: Fail (protection.outlook.com: domain of foss.st.com does not designate 164.130.1.60 as permitted sender) receiver=protection.outlook.com; client-ip=164.130.1.60; helo=smtpO365.st.com; Received: from smtpO365.st.com (164.130.1.60) by AM4PEPF00027A6B.mail.protection.outlook.com (10.167.16.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 23 Jan 2026 10:14:17 +0000 Received: from STKDAG1NODE1.st.com (10.75.128.132) by smtpO365.st.com (10.250.44.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:15:27 +0100 Received: from localhost (10.252.18.201) by STKDAG1NODE1.st.com (10.75.128.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:14:06 +0100 From: Patrice Chotard Date: Fri, 23 Jan 2026 11:14:05 +0100 Subject: [PATCH v5 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260123-upstream_uboot_properties-v5-3-5167929d5af5@foss.st.com> References: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> In-Reply-To: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A6B:EE_|AM7PR10MB3939:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b8e7a83-b4b2-450a-ec30-08de5a682af5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?cysrajAxQm9rNWpTNkNaLzE4RUNDamVQczkyamRpaGc0cmlwb0tlc2dZUHpk?= =?utf-8?B?VnZsY1ppVzkrQTJBeklUV2lBWE52cUo4L2k3V1BsV0pKdUhjWVdwUW5BdGNw?= =?utf-8?B?VEQxc1hyVCtGRWY4QWR5WjdrRlhScHpDT2Zmck8wNTMwOVhzQjlWSng0T3NM?= =?utf-8?B?b0FIcWlwanV3dC8rZUN0VVRnYzBXcWRCVjYyK1JzZzZ6bW1LemlvbFJxdGtO?= =?utf-8?B?Q2hETDhERG8rMUVlK3FYRHd6WVl4S3FuakJwZXhDOUtHNERlQlI4eERnS1FR?= =?utf-8?B?Y0owSDY5dmZoYjVSTk43b0RpcmVPN20zTTM3VHh6WDI2MDFrOVFlOC9XeG9T?= =?utf-8?B?U1V4MTV5ZnMya2hlejRreGlpK2tiZTd5dVFJNTdwUTNRdnpPM3AySzN0bHlY?= =?utf-8?B?VHRoZmN0b3JlaVVOb0ttMGQ3ZXZ0MUJFT1cwRis1dVQ5WFNGQTZuUk5CUElV?= =?utf-8?B?dDNiVVQzOTFTT1Z1ekI4ZHNHYjJWU0lCV21QSjZiWTBvVHkzTjkza2lLSVk1?= =?utf-8?B?ci9kK2c0U29iU0hRUEs3RXJPZFJOaitrSFRPaldVM0pOd3d5YXRSNlcvTGVV?= =?utf-8?B?c2RpM0hFZjhVY3orbVppY2hibmJPZlpKU3M5cXpnZmNOOStGQldBTEZOakZs?= =?utf-8?B?MDhtV29rR3FZVlNCakNxcHVCWGM4QURFSUVkclhKcEJQRzRsZDVaMmJRUkZm?= =?utf-8?B?SGhWaHhXQjB4VC9TeUF1a3FrYk1XSDFjTDZPNWFDcXpJWWRIYk94ZFd1V0pa?= =?utf-8?B?Slo5UURRVWFYM3NCMFoxUStULzRmeStvTWVTRXdCand5TSt5Vmtla3kvK0FN?= =?utf-8?B?QmhvQ05XNy9vcnczYmRkR09FWXJMbVpxNjhlTkZzNGdyeURkcThJK0ZFNWVj?= =?utf-8?B?TTlwTUtSUVFsNTBGeDhwdUtaRjc3MWhIQXlIOEJHc09IWHVFVGN2OG8xaGl1?= =?utf-8?B?eFZabGlmWFJVclZhbXBvUWx2QmxqL3lOVjh0UW9tUUtpUVZoMUFlK3JmRDI1?= =?utf-8?B?THhEcElNdTV5Tmo5d3VZWjFDM1RVTG9UTnR4bEVEbkJodXN4NzNlUCtRU0tx?= =?utf-8?B?azZlWDJ1V1RWZEZERGE1U2dTdUtLNi9RWjhlM3NmK2VyTWRrWkk2NkVoTTFi?= =?utf-8?B?WHFncEUwYUJJVVJXN25ZcmRYc3E5cldIUy9iem9BR0drV3R0L2VDQmtBWTlv?= =?utf-8?B?OWI0RkxXS1JCNmpIZXpiVWtJZll4cTJoWEhHR0E5OU12Yk1rVFJra3cvSUZJ?= =?utf-8?B?TlNkMEhRUUpXK1c2cmx4dEFhRjdUYnVsWjFCWHNHaEF1R1RqaWRmaWpvM3hr?= =?utf-8?B?eStnSWNGM0c1WVhPbm01SjNncmNad2w5K2xOQnhGUTlTSzJkZjNHbUdsTCs0?= =?utf-8?B?WGFsTWQvRENzckljQmxFWW1Xb3JBelcyR2dURXF5SzlvRmk1NUZhRjNHM2c2?= =?utf-8?B?QktSR0tleEdHVWxYNHZ1ditTOFhrdExqc1BmVjRTeHhualMybm1sMnkvYzMv?= =?utf-8?B?bUJWdHhRYUk3ZnluM21oTDNkRFlod1lHeVBZUUIrTUhxTmVPN0lNem1BQ2Nr?= =?utf-8?B?RExKTHBZNUtxZ0hMREM2Smxyc2pIRW5rSDFqbFdSbDN4bFQ1SVo3eHFyRnNn?= =?utf-8?B?ZlluZEpiT3IyV3BaUXhaclVJQmxqS0R6c3dvSUx0Q1lTT21iaGxKL1VzMzl2?= =?utf-8?B?NlVlOWJNZmJnQTJkV3pxRGY3UDJiWXpHZGluVjI3ME53NXB5RmlHQVZGT2lW?= =?utf-8?B?dmlHUDZtSDd5a3N4Q1ZBTjVwOHFvVWJEZVl1UFRpOWFpNTU5bzduZFl1WXVY?= =?utf-8?B?RHBTY0lmQldMZWlZSmx3aDMzOTQrYnZQN2hpa2IySy9OeWJmY0pTTzRSMjBs?= =?utf-8?B?akJQUnZDcHpUbjl2SjZWaVJZQjVXbmJ4WHBWc2loQXNNNWMxdjRob1E4M0hv?= =?utf-8?B?cE9LSlpkQ2kvYlVRWE15QTZWRXF3UmQ2MWpLQkdIamlWN0NqaE9aNXFHM0U1?= =?utf-8?B?VzFJMmUzODlia2Z0bitidDZPMEN6TGxDYllxTG1lWlJrUHA5MlM4WVlBUHA1?= =?utf-8?B?VXkxb2lxOThidlZFM0FNQmxCRVpXMFRwYW8zVDdmUVZ5WEp3NFlsSWVwdG9a?= =?utf-8?B?MHkzcWs4VG5VOHdzKzZkNDNLNjdXUUpOd3EyUmF3S1N5ek1TL21mZ1hRdmgx?= =?utf-8?B?cHJPYWt4N2I3SFF6RHJJamFnN2JNL0tzWTdiT1FSODVTVVJvZk0vRjdVZ3lz?= =?utf-8?B?MGJLRzJweGQ2SDdIdmlYV3hlSFd3PT0=?= X-Forefront-Antispam-Report: CIP:164.130.1.60;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: asbhLMhgYyttAjku9ceUqI/FVwTWtD6N/dqMvI5A0VkI5HcDUYGPb+H0SziNn+RcUIfzT7vYpcHfnsf30KQkGLk7Xk3oJgxHvSBE7xHR1etqYKcbqJ03CLAK48q0CYL1SJnMGJnlanrS0NzzqH8M6mEv5NxcsXBcQCgaDWQk6jJAlNDjeSEXJ4tCFH9cPVx04B43UqDVVZhP2Ie3V79T3h8WsfJGZSaUmbZkCUScZ2FDvdTYcD21Xhr9Xmg53izjPkfpq8Xoojx5BDzj89+9shtbVQAZWSrcVtNLD0TbPiHkFgBxUuhSF6fAJrhdqdY62Laio01NyBlcp52KIgRaZVRQoXc9fFci4e4po+0INFhzYqJJ4aZAS9eX0y30rwS95QEnhGFjlQOJ9OAbTkm4ieKyRCleLKXioqjtmEiR3sy10VPYsMmdQVzXvYUvQHL2bk8P7a4XrAZ2hwNoHzEyWuDlwd+7bDnHic8/FzkgQmWo5MUr+sSmcuamQBwQUS3+BSp6xOMN96NSkFO5galIK9z9woadHpRDFNZD018Owq2HujsKHLbTemplGEnds22wm0HwkqrLzfoyal8MMFCBYgRorhioKKelp7Gjyp7oWh2HEi5smjqczOIdILmvgdTIgFN5JYsB9HUQ6/U2ZLA210hHNVx79x613WV+x4SsPKOhDbChuhs5Wu3BHvDSN/j5RlfXWpqwd4A4RvSqMHir3g== X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 10:14:17.6171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b8e7a83-b4b2-450a-ec30-08de5a682af5 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A6B.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3939 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32h743i-disco.dts | 69 ++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32h743i-eval.dts | 69 ++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32h747i-disco.dts | 69 ++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 69 ++++++++++++++++++++++++++= ++++ 4 files changed, 276 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/= st/stm32h743i-disco.dts index 8451a54a9a08..368035d96158 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -73,6 +73,59 @@ v3v3: regulator-v3v3 { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &mac { @@ -92,6 +145,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -104,6 +169,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&timer5 { + bootph-all; +}; + &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/s= t/stm32h743i-eval.dts index 4b0ced27b80e..ec525411431a 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -99,6 +99,59 @@ adc1: adc@0 { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &i2c1 { @@ -130,6 +183,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; @@ -144,6 +209,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&timer5 { + bootph-all; +}; + &usart1 { pinctrl-0 =3D <&usart1_pins_a>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/= st/stm32h747i-disco.dts index 99f0255dae8e..a481326ad9e6 100644 --- a/arch/arm/boot/dts/st/stm32h747i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -91,6 +91,59 @@ button-5 { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &mac { @@ -110,6 +163,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -123,6 +188,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&timer5 { + bootph-all; +}; + &usart1 { pinctrl-0 =3D <&usart1_pins_b>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts= /st/stm32h750i-art-pi.dts index 56c53e262da7..8dddc70c37a1 100644 --- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts @@ -114,6 +114,15 @@ wlan_pwr: regulator-wlan { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; }; =20 &dma1 { @@ -124,6 +133,50 @@ &dma2 { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &mac { status =3D "disabled"; pinctrl-0 =3D <ðernet_rmii>; @@ -141,6 +194,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -196,6 +261,10 @@ partition@0 { }; }; =20 +&timer5 { + bootph-all; +}; + &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-names =3D "default"; --=20 2.43.0 From nobody Mon Feb 9 06:19:24 2026 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11013019.outbound.protection.outlook.com [40.107.159.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7372237E31C; Fri, 23 Jan 2026 10:14:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.159.19 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163290; cv=fail; b=ONoBOk4Md0Kzy/ZNLqDv5QDlzUmkQy5w5CXOFwn6cgEKaYIunjl90KMv6MVM3EiiYL/0TgheBxnoKiouD2PfnscporL51HGbwrCsKZ6qcnkv7zY1Xq+5ZmI5oP2JnpZs+PXZXO5CbOtRm8MhdJ95cNQl+4Wyrb0blzplVfB8Z3o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163290; c=relaxed/simple; bh=tTEFPBWYnN0cnN/07ISDa+9JpxIxGRXrZPJUUoAd/So=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=PL7Hwl1Xe9DT4z3E/NSuXWIajmDJe1f4R9sY/864vdlofTHrlcTehbk8bALShpgPJlH8UFySkxdwQDEmqDucwc2npx4QhWtwnIJK7QPDoHPCW9QJzt4ybcewYj40wuM8AHgo7h/Cn/G45ki3G4gbWNFC5gCyv0jWWR7SGl+lQLY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=iV29Z4M6; arc=fail smtp.client-ip=40.107.159.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="iV29Z4M6" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Ey5aE+7VAoniTbCYW49hFyGriswJapvFxMMFXK0YTUfdV9wC19XXKKxPHaZw8C5ZsTxuLpasWPkVnKCvUv/ytFh8AIZDEJkBzy4CcenbC3YqzccnB2q0t1FJFS2+x2kv1+t8QfYSkt1cxjCfTZ6g+T2TXDp7hDm6lsJQxgX2dB4nE6iE11WyDRo8jhBJoYJBcKM3grvDomhhtiqUJ88NdjtZgloG17xKaiyc8MSrbp+XiwFZhB6kgkWuwfIuc0m4pFzUEnpJ19t0vg50L+AcB+8PBpEl8YviG6J3nIcjbr7wgi0EF7XfesMTgea3AuBdcyj5+4i4MYO7kTFmZy9ylg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6v/PI7R1mVhQR8EuPqU7o9W3qgnM8/sNOtT1B/C6FUw=; b=pGf4TD9r1wwwZ+B71k+Cc60NPkVVUhW9ii1ifVxZ8UpcDp5cItpzk123Bi+PxzjtSl+rBKULVCxew7SkPtiZky/pjQXAmqGT9ZT9D/CA42J9ltLVEpCrkpgCq8Q72esUcE5fBjBaznBVWzMkUucNJ92lvp5Bf/857173VbLTN1Rbu1KnO5M2BZvyz28S/j8FJd4oMKXnTUxonTdPK8b5SgpqYh4d/Ay5Uoz0d2hHFKW0EQslK3Itesd70Rjk2NsXWx8kLehl3ccf9h4OHFpdC/b+OQ8ImFJJzd7+XJMNbwHJKasSJ2BTzCVVrDkkVvXkzB+zVq20eG56nCOFtCNskA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 164.130.1.59) smtp.rcpttodomain=dh-electronics.com smtp.mailfrom=foss.st.com; dmarc=fail (p=none sp=none pct=100) action=none header.from=foss.st.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6v/PI7R1mVhQR8EuPqU7o9W3qgnM8/sNOtT1B/C6FUw=; b=iV29Z4M6I7+nnC7jtMuFd2+6jZbP+H7BLWjeq8hYr+SN/Vb6d5SNhR2NkDcoGU4T6xESoibdACrMUagwrhQ09qW5ipncvDInyg3iHpddiGbILwp+L3TrzOR30sUN88TLX1+8QjnwFXqxUMRAD9jCRVt79vO1gBlbK4Cl95qwMAx+p3G5iZq7PYlkzsIvrXj30dnugNb6AK17cS42jPvr7AbSVUJEWPyPp82uxOlqIf9vQ80LpTiTBGwpfOH+AgrOVjaGOIxlPKc6P/i0hHXOlWotq2aJhA0CvjGaQu6PX8OaskD/dK4ozYEqg+pO6HNKieZ7qQe6/gPxXrqfPWXzDA== Received: from DUZP191CA0056.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:4fa::14) by AM9PR10MB4104.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:1f2::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.11; Fri, 23 Jan 2026 10:14:27 +0000 Received: from DB3PEPF0000885D.eurprd02.prod.outlook.com (2603:10a6:10:4fa:cafe::4f) by DUZP191CA0056.outlook.office365.com (2603:10a6:10:4fa::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.11 via Frontend Transport; Fri, 23 Jan 2026 10:14:23 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 164.130.1.59) smtp.mailfrom=foss.st.com; dkim=none (message not signed) header.d=none;dmarc=fail action=none header.from=foss.st.com; Received-SPF: Fail (protection.outlook.com: domain of foss.st.com does not designate 164.130.1.59 as permitted sender) receiver=protection.outlook.com; client-ip=164.130.1.59; helo=smtpO365.st.com; Received: from smtpO365.st.com (164.130.1.59) by DB3PEPF0000885D.mail.protection.outlook.com (10.167.242.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 23 Jan 2026 10:14:25 +0000 Received: from STKDAG1NODE1.st.com (10.75.128.132) by smtpo365.st.com (10.250.44.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:15:38 +0100 Received: from localhost (10.252.18.201) by STKDAG1NODE1.st.com (10.75.128.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:14:06 +0100 From: Patrice Chotard Date: Fri, 23 Jan 2026 11:14:06 +0100 Subject: [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260123-upstream_uboot_properties-v5-4-5167929d5af5@foss.st.com> References: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> In-Reply-To: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB3PEPF0000885D:EE_|AM9PR10MB4104:EE_ X-MS-Office365-Filtering-Correlation-Id: f452d2b7-cb29-4429-8f61-08de5a682f6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?VHZMcEhscS9BWkp3NytCUnN4ZWFQblM0SjJmZldpRDdKLzZsd1hUQU5saDdx?= =?utf-8?B?K3Y1T2d3Yk0rTnZCL1R2cGZKOThGb2c4UVFnM1k1MFZVdFpLUGR5MWh0a21w?= =?utf-8?B?c3RWdkpvU1hZaldsMnoyM3hvNXF3NGRhSVJac09tV2NBVXlqNEU3VTc3d2dB?= =?utf-8?B?Q2JhSkRhb3doOVhTSEZObXYxb3ZGcW5HVmgrTVVrcDBDaXF5eEl2ZVF2REI4?= =?utf-8?B?WHlUOTcvbUJjSUx1VHZMa1BTMytKYk5QaFoyajJ2cVRaZmJ2cHFjM08vdzYx?= =?utf-8?B?aHFjUzNQeDBaZDBaVHlYMmF6MEtGbEpYVDQ1TXFOUWVmU1NwcDdEcGNTdDlp?= =?utf-8?B?RXVTZGtpcWRMeFJKeUE5NGlwMndyVHZrVWtTZkRNdWVYNnBjU2VpVnhFRnB4?= =?utf-8?B?eHRMUDljUHBqVXVETHV3UmI5VE13RUdEVmJ6YUEyblk4RGxNYkdSaERHUUhV?= =?utf-8?B?L1ZBRzFSYWJFK0VKM0UxNGNadGVGYUVlR2NYOUdOcnA0U2d4Y1JEYjJSRDBw?= =?utf-8?B?b1NxZTVXdUgwUzdiem5obUV2OHFHZUJFUnJzMFRnRm94OExRVzB0RThmVDJ0?= =?utf-8?B?U3p4VVBla3JiaGJKYW8vTXNpVmRHbSt0WkV1NEJJU3FTMVhqaTBQOGZXbVpa?= =?utf-8?B?SWFlczQ3SXNnbzdEdzRhMWVVZExsTUxIeGg0OS9NMHd6WWgvNnFwNzJld2Fw?= =?utf-8?B?SkxFT3NnSVc3Z1RDVmhYSUJNL2EwSTc0clROZ2RTL05lRkVNbEpRNkxoYzN3?= =?utf-8?B?Tk5JTDVnVUN4dm10bURTYlVMRWl3UUJjby84Rlk3azBYTkVxcTVmRWIwZTNI?= =?utf-8?B?S2FsMUx0VUNnVHNsNnNFRXFqUDV4dW5xZHN4TDFOVGJaOXpNOU5TakNGNGhh?= =?utf-8?B?YSt2eU1zeTVjei8xVUZVekVXbDJmMmZSRksyYTJLTUpwMkJqbGI4cHlmalJN?= =?utf-8?B?VERSc1VzNDdhN2krUjdEaFprM0lKcFR3T1NaOHZlaEtuM0VOdFNxOXI1ZTVo?= =?utf-8?B?QlJGakdvYnRrY0QxdGRwcFd6SmVTYXJEMTB0Z2V5WnphRDFkR0NhejBMclBo?= =?utf-8?B?MElxTHF2dkVJelY5bzVXQVJUbEJMTmJ6RXl4VlRRRDFaU3J4Qkh0THpQV1gr?= =?utf-8?B?SUw5Ympxb3FVWUQ5TDhFdXVNVjlOSG5BOTg0M3lnakNQRWM4TGFNVzRMSWRr?= =?utf-8?B?Y3I3bHpLdTk4QW1CaFFwbFIyUUk0cGdldFFHZjNzOUhUSklvcnhFZFpGQlFx?= =?utf-8?B?ZHF1a0xGWHNHQks2eHVQenN0cEsrclA5cWhZS2tlRVFSQnU5U1BNSmNXL0Nl?= =?utf-8?B?aFlIa1ZQSklLQ2hxWTY2c1haSnlWMyt3QlRCajQwbzZjd3hQU0k5R1o2alJ0?= =?utf-8?B?c2g0T2dhSVFhbTZUakJRQTVMbkwzSmtaMXRvZWppbWJtTFZXa0pXYzhoTFNO?= =?utf-8?B?RnV3MkJFSndEek1od1g0cjN4MGc5WTNObnU5dVpUM3FsQmhxTSszV01zSXpn?= =?utf-8?B?WlBoU29EM3MzU25GV3R2WlVya0d1dEJKQU10L084RnpIN0xhUldwT3E0U25V?= =?utf-8?B?UmxvOTFjSTkvZFpwYVlHT2kyT3VNQjNXQnRXS2psRE5NSWxiM0hEQ3RNYkFZ?= =?utf-8?B?RHprZkNQT2N2czFCY0hOeEhwRGg2djBUMGNTZWhPNG1VNkt5ajFsSCs4WU9K?= =?utf-8?B?Ti9rRVA1Ym5pcGdseHJoYXJ2WittT0gzWU01VVV6aldlbjZJaGg2b2VodjVw?= =?utf-8?B?dUdGdmRmSVVwT3pxbTRldkhhVzZCa2tQeDNNR2RsZ1dWVUJqeXhjTngzVW5v?= =?utf-8?B?WnV1alk1b244d01Lc2QzVmxlN1NZbUp6aVpnTVpqYlExN3NSRk1rQTNwQ0lr?= =?utf-8?B?Q3BGMGdyZVIrdDVBMmVzNElpdytaUElVeUNPeVJ4bm9PL3JabHRCRGt5SGp6?= =?utf-8?B?dFBLY2NOM21KYlcvdkF1RnF2em1kWkc4TnU4ZkpTUWxTWTV1MmNIZ1RBTEFK?= =?utf-8?B?QzNBYkFSdnBnb2tQb2Q0TnRNTEpFOG9jb2RieitIOTJSV0RmV3oxY3U3TS9s?= =?utf-8?B?YXNESi9YTE8rNkowcUlMdThja2k5bXZybURCOXROZmY2bVpCN0xLTS9ITUlP?= =?utf-8?B?YnBzMG5kbDBhR1ZIUnlZV3VhbnNmbGNic2tQb3RJZys5OHRDMHhyeWdiWnlV?= =?utf-8?B?THcvRkhwK0pRbm9SaVZLZ1B5SHg3N093ZGgyREg3d0lBTkFEanJidk5YMUMy?= =?utf-8?B?NGkvdlFqZVlFYjVibDBRd2lrQUhBPT0=?= X-Forefront-Antispam-Report: CIP:164.130.1.59;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: ipkEoszTd7vhX/Sj/Rre7fuAMeaB30Ia5TQIPbRJfE3AY+bsutQdJOWlJFw3HKA6TF7G5jwattERBW6T5W/wA7pObj+cw3DomNQEkVelTUxafxLyKmZ06hYn/bi3YoFaRQnLNxEang7XjXImkVrkYL2b7Qrxxfl18lXl9eA+jwev7IDXyyioONYv1dqG//w9sjIutQeMnCzcjtQ7jN/D8hNmhC1pVTni7QGdWafMFFUH2UnrOERDI6IlG0iK3ydFpelhkraz0yvrsGX50W4JSXcxc4FXXhxyhVNEQ8Q3Ybahw0mhRMFe0hk0cB2NILODc5tEj15BASVHZBUxZdpZYaXsdctF2DxxTT7ZC9C0a5VEWAygFxedwNztmAo0eMcoA97FeGHVycYZz9IVkpKMPxfFYGj9ZyClqxqqZ6Yw5N0kVwnUGvHJwDATd+r+XsVa8cPw4dYGSHWLxQEkHW5fMo/pU4DwVIe9kFlHSRhBW4v5YSoibA9vpND2+vDIr0X4eoZ/UddMR20YlVPs5Jxxf9F74tK6WGedAyXXnNEiSSsA9UKYTM8c4H8IPANBD9+OWl6Tmk4hjrJmCZE8k1j9vFV6jyy2x1PX7fN/j5Wt5ad051NKJBT5OrjTpwlB5irDzHrMTnOqCVPQbjUPp52Evmumw5CKQWKG5wHquP9AR3qfaKJ9SvWHGdqlkbdujIpoLkj0Y2wIM51+5bW44rzGdg== X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 10:14:25.0746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f452d2b7-cb29-4429-8f61-08de5a682f6a X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB3PEPF0000885D.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR10MB4104 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 ++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 ++++++++++++++++ arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 145 +++++++++++++++++++= ---- 4 files changed, 247 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index fd730aa37c22..80c97bc830eb 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -30,7 +30,7 @@ arm-pmu { }; =20 firmware { - optee { + optee: optee { method =3D "smc"; compatible =3D "linaro,optee-tz"; interrupt-parent =3D <&intc>; @@ -85,7 +85,7 @@ intc: interrupt-controller@a0021000 { <0xa0022000 0x2000>; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/bo= ot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 9902849ed040..526ab2e1a93c 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -350,6 +350,21 @@ timer@12 { }; }; =20 +&uart4 { + bootph-all; +}; + +&uart4_pins_b { + bootph-all; + + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&usart1_pins_b>; @@ -367,6 +382,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS= :pin11 CTS:pin36 */ status =3D "okay"; }; =20 +&usbphyc { + bootph-all; +}; + &usbh_ehci { phys =3D <&usbphyc_port0>; status =3D "okay"; @@ -432,6 +451,7 @@ connector { =20 /* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.2= 00 */ &vdd_ldo2 { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <3300000>; @@ -440,6 +460,7 @@ &vdd_ldo2 { =20 /* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ &vdd_sd { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <3300000>; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st= /stm32mp135f-dk.dts index 9764a6bfa5b4..83bc5ea90c3a 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -161,6 +161,10 @@ channel@12 { }; }; =20 +&bsec { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -208,6 +212,42 @@ phy0_eth1: ethernet-phy@0 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c1 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c1_pins_a>; @@ -342,6 +382,7 @@ goodix: goodix-ts@5d { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -349,6 +390,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_a>; pinctrl-1 =3D <<dc_sleep_pins_a>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -358,6 +400,22 @@ ltdc_out_rgb: endpoint { }; }; =20 +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&rcc { + bootph-all; +}; + &rtc { pinctrl-names =3D "default"; pinctrl-0 =3D <&rtc_rsvd_pins_a>; @@ -369,6 +427,14 @@ rtc_lsco_pins_a: rtc-lsco-0 { }; }; =20 +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vdd_adc: regulator@10 { reg =3D ; @@ -392,6 +458,10 @@ scmi_v3v3_sw: regulator@19 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; @@ -402,9 +472,24 @@ &sdmmc1 { st,neg-edge; bus-width =3D <4>; vmmc-supply =3D <&scmi_vdd_sd>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&sdmmc1_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + /* Wifi */ &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; @@ -436,6 +521,10 @@ &spi5 { status =3D "disabled"; }; =20 +&syscfg { + bootph-all; +}; + &timers3 { /delete-property/dmas; /delete-property/dma-names; @@ -517,9 +606,20 @@ &uart4 { pinctrl-2 =3D <&uart4_idle_pins_a>; /delete-property/dmas; /delete-property/dma-names; + bootph-all; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart8 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart8_pins_a>; @@ -583,6 +683,7 @@ usbotg_hs_ep: endpoint { }; =20 &usbphyc { + bootph-all; status =3D "okay"; }; =20 diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boo= t/dts/st/stm32mp13xx-dhcor-som.dtsi index c18156807027..4efaca84a72c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -54,6 +54,46 @@ vin: vin { }; }; =20 +&bsec { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c3 { i2c-scl-rising-time-ns =3D <96>; i2c-scl-falling-time-ns =3D <3>; @@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &qspi { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&qspi_clk_pins_a @@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a &qspi_cs1_sleep_pins_a>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 flash0: flash@0 { @@ -238,37 +288,35 @@ flash0: flash@0 { spi-max-frequency =3D <108000000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; }; }; =20 -/* Console UART */ -&uart4 { - pinctrl-names =3D "default", "sleep", "idle"; - pinctrl-0 =3D <&uart4_pins_b>; - pinctrl-1 =3D <&uart4_sleep_pins_b>; - pinctrl-2 =3D <&uart4_idle_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status =3D "okay"; +&qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; }; =20 -/* Bluetooth */ -&uart7 { - pinctrl-names =3D "default", "sleep", "idle"; - pinctrl-0 =3D <&uart7_pins_a>; - pinctrl-1 =3D <&uart7_sleep_pins_a>; - pinctrl-2 =3D <&uart7_idle_pins_a>; - uart-has-rtscts; - status =3D "okay"; +&qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; =20 - bluetooth { - compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; - max-speed =3D <3000000>; - device-wakeup-gpios =3D <&gpiog 9 GPIO_ACTIVE_HIGH>; - shutdown-gpios =3D <&gpioi 2 GPIO_ACTIVE_HIGH>; +&qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; }; }; =20 +&rcc { + bootph-all; +}; + /* SDIO WiFi */ &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; @@ -312,3 +360,56 @@ &sdmmc2 { vqmmc-supply =3D <&vdd>; status =3D "okay"; }; + +&syscfg { + bootph-all; +}; + +/* Console UART */ +&uart4 { + pinctrl-names =3D "default", "sleep", "idle"; + pinctrl-0 =3D <&uart4_pins_b>; + pinctrl-1 =3D <&uart4_sleep_pins_b>; + pinctrl-2 =3D <&uart4_idle_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status =3D "okay"; +}; + +/* Bluetooth */ +&uart7 { + pinctrl-names =3D "default", "sleep", "idle"; + pinctrl-0 =3D <&uart7_pins_a>; + pinctrl-1 =3D <&uart7_sleep_pins_a>; + pinctrl-2 =3D <&uart7_idle_pins_a>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed =3D <3000000>; + device-wakeup-gpios =3D <&gpiog 9 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpioi 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&vdd { + bootph-all; +}; + +&vddcpu { + bootph-all; +}; + + +&vddcore { + bootph-all; +}; + +&vdd_ddr { + bootph-all; +}; + +&vref_ddr { + bootph-all; +}; --=20 2.43.0 From nobody Mon Feb 9 06:19:24 2026 Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazon11013012.outbound.protection.outlook.com [40.107.162.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC34837AA6A; Fri, 23 Jan 2026 10:14:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.162.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163275; cv=fail; b=ODXmnSwF1FFuKdTX9r/3nGAe5IGHvzibrsCjirJ1Fzpw7veuqs1QjvC4IWAqHStNt2rKBjPBr5cg8O9IkenuNDDWkAyLyz0eSOR9II6mybUWu4tMcx2Q98Vn8oxLHOhjTnoJCpJcMVpEn7KnMl1ZHwzyCoYfYxr7QwIXwqKwbxw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163275; c=relaxed/simple; bh=qgoLg8g13lRwu5bZPmYCljL5vw9Vs+mn5pek8f23Q3s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=R2qPkqwq8zz0Kg5lOS7DAN1kZJsCto2sjmYJX/ZNwOJl9/hh6Qy0wkQ1k9NlRMBd/TtNZ0cBJjkfURkR3nVhpluad6JBz1PrzjEiabVRbCHR0cCqmbs++PGGLX8zcI4+8gIFARnMV8galrkeahxHeHTlA5hJX00weDlMCLcXAtY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=DYpsTEtm; arc=fail smtp.client-ip=40.107.162.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="DYpsTEtm" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PklI4wasoVEVQ20u6sN5LVdw7VQMlzF+MlF0guuVvVDSbbE/ROB0tlrYMXJWXI2OwG0rs8WlIXtbWH7a6zdCIZ+MQGUUnJnYqQT3qhvCrvs/ccQSk2MgxRjGDGR184zAU+4+Vm7SDvSt+Q1qKpGq6O29DT9tZUlh3aAtrfPgIAdTrS7XqhzSHWNOmOSQ/pBFkPocE698gpmCjAijmvnwnlbWnFMgpxVEH/Rthd4E0NILJMi923W13Br2snRSQCckTNrVEONqqckyfEFoBrt7JHkXs4ZaqhOxhy+44ddOTPZuD5zFdjboVc3sr6o55MLzsDYn15D0lOY0xW6P/2T/Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Qf4/7AyVrq/PU5rn7RvQqR9loC0PPaiuuPMP464kAcw=; b=ygkW/n7WH3vdaeRur9bIusE00WJrLzc+cFJ6/WAOq4n9RmuUIJZHp1VdcgL5+K0XBZxV0s+P7/nQLyNasnXEO4BfbNJHLdW3iLPcfvHHvvuF6Z+mN9rkRLyBwy8NO+fvBjvv2cUxESKcCuR4rgckgcVuD6LVbjzrRogkrxx4AUBTPRTjsXECf80j9oBaDRrRKPGT1wUblSsLNcbOQwl424psav0WmH1FRwexEgsZ8g55wVfC6cKsU5CwuQwHh/Mx11+XLvuTFx0Cms+M4VAkiS4Yr+9ZV65n0z6RA2nvThqbHY0fZBAHqd6mb/THYy3RGybummnwwFp+LjRemroVkg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 164.130.1.60) smtp.rcpttodomain=dh-electronics.com smtp.mailfrom=foss.st.com; dmarc=fail (p=none sp=none pct=100) action=none header.from=foss.st.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Qf4/7AyVrq/PU5rn7RvQqR9loC0PPaiuuPMP464kAcw=; b=DYpsTEtmYJskpUmK2+Y4FMYiREzY66qbQnhBUXOXyqkyiGmIcpObkZQkbsRER1flGtpwlak5FgZ9Wg7v73A/ChJYNA7rchBFiJxJbjrH/uAUxQaVpPdSKxhMhowSCOIp8XNtTHNMrUVREIfs/ZjZT0lqnD15DPVvgsTaR/GbGMSqrIB2w5eoAsNyX9NqgAez3jdJLChrxcxQjxafUSCgGAeBE+c+UWYEOrPJU/l1tKykQVYSCd5FyOpRWvZShscxxWQ5opJ9oUhZZ8hkrsr+d00nsegVFXDrzgYhoNC63OWeuZy8vfsR7Yd/eaGexGZdWgd8Tv4UJKpGImYR9ZDQOQ== Received: from AM0P190CA0006.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::16) by AM4PR10MB9424.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:6cc::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.9; Fri, 23 Jan 2026 10:14:18 +0000 Received: from AM4PEPF00027A6B.eurprd04.prod.outlook.com (2603:10a6:208:190:cafe::c0) by AM0P190CA0006.outlook.office365.com (2603:10a6:208:190::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.11 via Frontend Transport; Fri, 23 Jan 2026 10:14:14 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 164.130.1.60) smtp.mailfrom=foss.st.com; dkim=none (message not signed) header.d=none;dmarc=fail action=none header.from=foss.st.com; Received-SPF: Fail (protection.outlook.com: domain of foss.st.com does not designate 164.130.1.60 as permitted sender) receiver=protection.outlook.com; client-ip=164.130.1.60; helo=smtpO365.st.com; Received: from smtpO365.st.com (164.130.1.60) by AM4PEPF00027A6B.mail.protection.outlook.com (10.167.16.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 23 Jan 2026 10:14:18 +0000 Received: from STKDAG1NODE1.st.com (10.75.128.132) by smtpO365.st.com (10.250.44.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:15:29 +0100 Received: from localhost (10.252.18.201) by STKDAG1NODE1.st.com (10.75.128.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:14:07 +0100 From: Patrice Chotard Date: Fri, 23 Jan 2026 11:14:07 +0100 Subject: [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260123-upstream_uboot_properties-v5-5-5167929d5af5@foss.st.com> References: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> In-Reply-To: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A6B:EE_|AM4PR10MB9424:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b6e5505-fe60-4099-e4c0-08de5a682b5e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?dXZSU20wQ20xMkFyclMrcVhDVzBESjdPRjJYS2FpNU5tNHpCcldORHJ3b1ho?= =?utf-8?B?WklXWC93L2JoWU5WaDdvT0x3aDcvRmQzQnpVWXFkUTQ0bER6TUVJU3JmM2hi?= =?utf-8?B?TENXVUt5ditHeEh0MStpdDdQL2oxUnpBVmxzRGRLdFAzRGt4WUhDVE9JNHV5?= =?utf-8?B?a2NnL2pscFdSbU9zeVNsYmw2M0dCbnJ6RmduWUlaR05jZXpFRy84dmV2bS95?= =?utf-8?B?M1dhS3VqVlV0Z29wOHIwbXdIODBCZnE0ZnRyVEc0alV6d2gydG05SE81THVX?= =?utf-8?B?akg4L3EyTXpaWS9aamFxUy9LWE4wQzJLZlQwSkpzQXViV0UxUm9peEx5dkh0?= =?utf-8?B?ck1yOVBlSDdRMGpuQmdMQjhnQ3VaaXpxWXVhWE5Qank2YndOR2RWREY5RkJl?= =?utf-8?B?NXdkOW81OHBwU0RPNEFGYWw4ayt4aVpjM2hRUFVmZFZEWGZuUGlyajVWcEVD?= =?utf-8?B?alMrNVZBK1ovcW9RMEJpSDg4VFlLNVh2UUtRSC9OZ2NWVlBzaDlyaTZ2V3Yv?= =?utf-8?B?dDVMeWd5K05SV241bjk0N2lSbUt4L3YvSmZrdDZDRE53KytkMnpSNmtPdTlJ?= =?utf-8?B?Q2lYM01yeC9pNHpVeC85UTNiSjhjcWJrSFEreHh5MUUrUmZrZFlvY3ZqL1VG?= =?utf-8?B?S3NnOUtpclQwTUpSNFpWOGpTS3hPSnJpYUFXNWJoZUREYStDVkpwUkthODQ2?= =?utf-8?B?aEMxNGlwYWxGWC8xL2FrVzNkbStCWUZ4bm1YSTFXWitrN2oxTnkwU2FMM2pL?= =?utf-8?B?SzB2Rnl0eERsV0pnMHd4SEZJaXZHdW9Fb09GaHFBaEtLODhxYWRrTlVMbFlw?= =?utf-8?B?OXRqU29KeDgrOXR4bkQ0V1pFUDJOemdtT0JWQ2hGWko5cXBxWE9YWjVaYXlX?= =?utf-8?B?UWNoQTNGTmNrbllaSi94NWEzMi9BZVRtaXJwVnVJcTB4bk9tYUx4dlNuTjAz?= =?utf-8?B?TW9JTDdZK2gwaC9jUlVHaHRja3MyS1g4WU4wV1VUbHVQSnNaR3FXWnFvbmdy?= =?utf-8?B?cVN0emhaSHpSQVkwbjBGb2FUWTZKS3dFaG5xRW1lUnlZSlRrRXcyL3dHVmJK?= =?utf-8?B?aGRUREY4Q2lMVU5zMGhhVGtUdkE2Ynplcy9OUytpVzBMcVJvWXBFL2xTdWxX?= =?utf-8?B?NHNyZUZnTTU1b0dWYS9teHFsK0NQVkczYWg4Qmcwb0JYTG9tdmxHQUxLRGxB?= =?utf-8?B?Q0s4R0xkTllKWUxydGxjS0dzLzFnVGdXR01URG5tcGNYRm9KL0V4amVYY1Vv?= =?utf-8?B?TGpidmJ3YS9GbG80Sy9IaHJJRVhEdUN5a2IwQWpjSTh1V0MvVThkaXZmN2F0?= =?utf-8?B?SzNwOVNsVTVwR3loTzB2cDZ5Q0xaRkpzMFZyU0h2MkN2R2xNRGtRd3hVYmsx?= =?utf-8?B?RUswTzNKUUNwaU5zdnk5QUppTGlFazNibDN3WW5EL05VT3dLRDJjbUg2S3Jy?= =?utf-8?B?N21rdDhkVnZXcWJEdWdPNjZBaHlmQTRhVU1uaU5xcUVPUHBCaTFDNjViSm1O?= =?utf-8?B?b0lTUTZZdDRyRTZ2dGdLdElXUTNUa2JsZzM1clZxN29CNVlkak5MeGtNbldI?= =?utf-8?B?dlJ4WXpIbkVhbkFLMFpRTDBCS1VGanZpbnJKMm5Kbk4rMFB5bGUwa29MeUVI?= =?utf-8?B?dFBoWVEyYXNYMk1oSTJ4NG5kbDZvRUpNVkI0L01JS2wyR3pKQ2RWZzRCSVNQ?= =?utf-8?B?czFQYmNHMEJocWpaai9hTXhCT2tkSTV4bytJZzk3U0dWeUQ1TnppRFlpRkVX?= =?utf-8?B?RmpaMFU1R29mM2UvOEZIdDVFVU5iVHFWd25ISDNtNmFMeTBjN1JkbzFGNk9V?= =?utf-8?B?czRaaWFHQ0hmWHJjRVdqQ1NzR2dOKzB6dlpjSlNiRUdxT0FjdHZtc0hrM2ls?= =?utf-8?B?K1hTUXg5bHNac2FvV3RIYnk3Z3lYSTZFOUdSNkdZY1RKd1VaVGJpSXh4KzFw?= =?utf-8?B?ZTQzLzNYNG9QY09uUlUwaCtKczdON1lMNUpYazI3c29MVW5RT2JxS2daYjVs?= =?utf-8?B?S3czWE4vbFlpRDk5c1M5QWVQQWZoYzFpTmgzS25OMTNrckxrSFFPUnE2RkxB?= =?utf-8?B?elVSR2F1UkVLais5UHRuRWhVWFE2KzkydjlLKy9HMEh1T2V1OENWQVFWby9o?= =?utf-8?B?YlFiVTAyY01oejM4WlVPdy9VVHAybFB1eU5tMUZrNkFMSmFEN0RTMGl0TGlR?= =?utf-8?B?dmlFcEdEYUNDMjJJMmJkSThQRmQ3Nmo0M1dpMEMwZ0FrN1REc1I0NU13Zk9r?= =?utf-8?B?b2FrdnFONlNnd2cyWFV2dFJmWldnPT0=?= X-Forefront-Antispam-Report: CIP:164.130.1.60;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: gEyi4bqabmdcan3E5enExVT8pjPHInsm9sRbIsJfaUOr/62BJc+LexM/pR5u5y+QupsKQ5BljnaqzHpTeunqOGnGLnkNH+56yiRazLlNDWhuw9V1IaHHVW328SGOZ+VESiqCbhoNNpQC4IO+nNV0TZbcy07/WGfhjssC/2VPGGlqoOTK/NyZbzAYmLJpfDpiEpjBjOsTGHZWmIAj0FDNSdtAFessSx7GB4rfg5Kz5RDuqLBdQA48dc6MJiJRtguPbffJ5ERSYK9lgMHqrKmHmeJWm+NE8iYpkStHaYQtNOYjtqD8bJ61RngSiOzOdcf6xsqC0oER8Ke5htFBaCuTka4TZXWtB457lAgq1R1VyJ2lPHYG0bAuHYRRQKtoVWkRwrL4Zj6aSUMBsuMoxz4sejBKvP0xRiShkPxL1Hj0/KpXWgmUVlf7ZvJnv1R80sAnZLudlYYCTyka+TcKzdLR1LONZAk4ihFvDtJc3NQownDT7gy4hu3KrSQOBurRgCPaNgf4eKcHiAIW3xoMS73N57J/LBXCTobtqAVv68Y4VUXIjtIW0pGkBkjOiwUwpqAjweRXv0esmqfBJywM/bq/JJ23SOZLUDowVZfh8f0e2+QLFnRaKw25uZ3UOEpCVc/NbaMAXxhsOjfxZ2OblrS4Gm1kdU3giZsnpPWraEYqF/z1RkySN59PzzJeiatM+8yfJ4LnUS4m57S3o0k31BExNg== X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 10:14:18.3095 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b6e5505-fe60-4099-e4c0-08de5a682b5e X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A6B.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR10MB9424 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp151.dtsi | 2 +- arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 19 +++ .../st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 1 + .../dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts | 25 +++ .../dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 26 ++++ .../boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi | 100 ++++++++++++ ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 27 ++++ .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 27 ++++ .../boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi | 97 ++++++++++++ arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 1 + arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 19 +++ arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 151 ++++++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 + arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 38 +++++ arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 1 + arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 119 ++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-odyssey.dts | 21 +++ arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 1 + arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi | 5 + arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 1 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 1 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 172 +++++++++++++++++= ++++ .../boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 55 +++++++ .../boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi | 50 ++++++ arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 157 +++++++++++++++++= ++ .../boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi | 50 ++++++ arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++ 28 files changed, 1297 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index b1b568dfd126..ada55b2c1aa2 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -30,7 +30,7 @@ arm-pmu { interrupt-parent =3D <&intc>; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157a-dk1-scmi.dts index 847b360f02fc..b81b6e168b67 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -65,6 +65,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -85,3 +86,21 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.d= ts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index df97e03d2a5a..4ad1313efca9 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -92,6 +92,7 @@ bridge_out: endpoint { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts b/= arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts index 60ce4425a7fd..ac4e313ca371 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -35,15 +35,40 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&v3v3>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b= /arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts index f8e404346396..cc24a29fba15 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -92,6 +92,7 @@ bridge_out_panel: endpoint { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { @@ -110,15 +111,40 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&v3v3>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi b/arch/ar= m/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi index 569a7e940ecc..db93934019d1 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi @@ -61,6 +61,7 @@ vddcore: regulator-vddcore { regulator-min-microvolt =3D <1200000>; regulator-max-microvolt =3D <1200000>; regulator-always-on; + bootph-all; }; =20 vdd: regulator-vdd { @@ -69,6 +70,7 @@ vdd: regulator-vdd { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 vdd_usb: regulator-vdd-usb { @@ -77,6 +79,7 @@ vdd_usb: regulator-vdd-usb { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 vdda: regulator-vdda { @@ -85,6 +88,7 @@ vdda: regulator-vdda { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 vdd_ddr: regulator-vdd-ddr { @@ -93,6 +97,7 @@ vdd_ddr: regulator-vdd-ddr { regulator-min-microvolt =3D <1350000>; regulator-max-microvolt =3D <1350000>; regulator-always-on; + bootph-all; }; =20 vtt_ddr: regulator-vtt-ddr { @@ -102,6 +107,7 @@ vtt_ddr: regulator-vtt-ddr { regulator-max-microvolt =3D <675000>; regulator-always-on; vin-supply =3D <&vdd>; + bootph-all; }; =20 vref_ddr: regulator-vref-ddr { @@ -111,6 +117,7 @@ vref_ddr: regulator-vref-ddr { regulator-max-microvolt =3D <675000>; regulator-always-on; vin-supply =3D <&vdd>; + bootph-all; }; =20 vdd_sd: regulator-vdd-sd { @@ -119,6 +126,7 @@ vdd_sd: regulator-vdd-sd { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 v3v3: regulator-v3v3 { @@ -127,6 +135,7 @@ v3v3: regulator-v3v3 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 v2v8: regulator-v2v8 { @@ -136,6 +145,7 @@ v2v8: regulator-v2v8 { regulator-max-microvolt =3D <2800000>; regulator-always-on; vin-supply =3D <&v3v3>; + bootph-all; }; =20 v1v8: regulator-v1v8 { @@ -145,13 +155,86 @@ v1v8: regulator-v1v8 { regulator-max-microvolt =3D <1800000>; regulator-always-on; vin-supply =3D <&v3v3>; + bootph-all; }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { i2c-scl-falling-time-ns =3D <20>; i2c-scl-rising-time-ns =3D <185>; @@ -167,6 +250,7 @@ &ipcc { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -180,6 +264,22 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&rcc { + bootph-all; +}; + &rng1 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0= -of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-o= f7.dts index 5116a7785201..7bfd7da4a8db 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -78,6 +78,7 @@ &i2c2 { <dc { pinctrl-names =3D "default"; pinctrl-0 =3D <<dc_pins>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -134,19 +135,45 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&vdd>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + /* J31: RS323 */ &uart8 { pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0= .dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index d949559be020..a1f79659d7c5 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -36,19 +36,46 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&vdd>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; + /* J31: RS323 */ &uart8 { pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi b/arch= /arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi index a75f50cf7123..4f6f4712d634 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi @@ -61,6 +61,7 @@ vin: regulator-vin { regulator-min-microvolt =3D <5000000>; regulator-max-microvolt =3D <5000000>; regulator-always-on; + bootph-all; }; =20 vddcore: regulator-vddcore { @@ -70,6 +71,7 @@ vddcore: regulator-vddcore { regulator-max-microvolt =3D <1200000>; regulator-always-on; vin-supply =3D <&vin>; + bootph-all; }; =20 vdd: regulator-vdd { @@ -79,6 +81,7 @@ vdd: regulator-vdd { regulator-max-microvolt =3D <3300000>; regulator-always-on; vin-supply =3D <&vin>; + bootph-all; }; =20 vddq_ddr: regulator-vddq-ddr { @@ -88,9 +91,34 @@ vddq_ddr: regulator-vddq-ddr { regulator-max-microvolt =3D <1350000>; regulator-always-on; vin-supply =3D <&vin>; + bootph-all; }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status =3D "okay"; }; @@ -113,12 +141,61 @@ nand@0 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -132,6 +209,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&pwr_regulators { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rng1 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-dk2-scmi.dts index 43280289759d..e192d033626e 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -71,6 +71,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -91,3 +92,7 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157c-dk2.dts index 1ec3b8f2faa9..bf9fdf0d611c 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -80,6 +80,7 @@ touchscreen@38 { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ed1-scmi.dts index 6f27d794d270..f053a70cb254 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -70,6 +70,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -90,3 +91,21 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ed1.dts index f6c478dbd041..86919bb642fa 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -132,6 +132,31 @@ channel@6 { }; }; =20 + +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -157,6 +182,54 @@ &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &hash1 { status =3D "okay"; }; @@ -168,7 +241,9 @@ &i2c4 { i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; clock-frequency =3D <400000>; + bootph-all; status =3D "okay"; + /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; @@ -179,6 +254,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; status =3D "okay"; =20 regulators { @@ -314,12 +390,20 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -335,9 +419,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; +}; + +&rcc { + bootph-all; }; =20 &rng1 { @@ -365,9 +466,30 @@ &sdmmc1 { sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-ddr50; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; @@ -381,9 +503,27 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &timers6 { status =3D "okay"; /* spare dmas for other usage */ @@ -399,11 +539,22 @@ &uart4 { pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { vbus-supply =3D <&vbus_otg>; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ev1-scmi.dts index 6ae391bffee5..17295d67ab85 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -75,6 +75,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -95,3 +96,7 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ev1.dts index 8f99c30f1af1..d43bddc42ad9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -231,6 +231,7 @@ &i2c5 { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { @@ -262,6 +263,7 @@ &qspi_bk2_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -271,6 +273,7 @@ flash0: flash@0 { spi-max-frequency =3D <108000000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-pre-ram; }; =20 flash1: flash@1 { @@ -283,6 +286,41 @@ flash1: flash@1 { }; }; =20 +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/d= ts/st/stm32mp157c-lxa-mc1.dts index eada9cf257be..9f513045c559 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts @@ -158,6 +158,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_c>; pinctrl-1 =3D <<dc_sleep_pins_c>; + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp157c-odyssey-som.dtsi index cf7485251490..1c5517f57ecd 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi @@ -75,11 +75,84 @@ led-blue { }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c2_pins_a>; i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; + bootph-all; status =3D "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -91,6 +164,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; =20 regulators { compatible =3D "st,stpmic1-regulators"; @@ -218,12 +292,20 @@ watchdog { }; }; =20 +&i2c2_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -237,6 +319,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&pwr_regulators { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rng1 { status =3D "okay"; }; @@ -258,6 +360,23 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_d { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts b/arch/arm/boot/d= ts/st/stm32mp157c-odyssey.dts index a8b3f7a54703..92bc25b3f563 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts @@ -75,14 +75,35 @@ &sdmmc1 { st,neg-edge; bus-width =3D <4>; vmmc-supply =3D <&v3v3>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &uart4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/b= oot/dts/st/stm32mp157c-osd32mp1-red.dts index 36e6055b5665..b404ea3752d9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -131,6 +131,7 @@ i2s2_endpoint: endpoint { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot= /dts/st/stm32mp157f-dk2-scmi.dtsi index 89de85a2eff3..5d29c2154b46 100644 --- a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi @@ -87,6 +87,7 @@ &mdma1 { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &pwr_regulators { @@ -114,6 +115,10 @@ &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; =20 +&scmi { + bootph-some-ram; +}; + &scmi_reguls { scmi_vddcore: regulator@3 { reg =3D ; diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157f-dk2.dts index 8fa61e54d026..4d857b3575fd 100644 --- a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts @@ -97,6 +97,7 @@ stpmic@33 { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/bo= ot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 5c77202ee196..2e02cd8e7e0d 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -201,6 +201,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_b>; pinctrl-1 =3D <<dc_sleep_pins_b>; + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boo= t/dts/st/stm32mp15xx-dhcom-som.dtsi index 4cc633683c6b..2c40ceaf1f33 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -103,6 +103,10 @@ channel@1 { }; }; =20 +&bsec { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -121,6 +125,26 @@ dac2: dac@2 { }; }; =20 +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status =3D "okay"; }; @@ -190,6 +214,7 @@ &gpioa { "", "", "DHCOM-K", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiob { @@ -197,6 +222,7 @@ &gpiob { "", "", "", "", "DHCOM-Q", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpioc { @@ -204,6 +230,7 @@ &gpioc { "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiod { @@ -211,6 +238,7 @@ &gpiod { "", "", "DHCOM-B", "", "", "", "", "DHCOM-F", "DHCOM-D", "", "", ""; + bootph-all; }; =20 &gpioe { @@ -218,6 +246,7 @@ &gpioe { "", "", "DHCOM-P", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiof { @@ -225,6 +254,7 @@ &gpiof { "", "", "", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiog { @@ -232,6 +262,7 @@ &gpiog { "", "", "", "", "DHCOM-L", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpioh { @@ -239,6 +270,7 @@ &gpioh { "", "", "", "DHCOM-N", "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", "", "DHCOM-S", ""; + bootph-all; }; =20 &gpioi { @@ -246,6 +278,20 @@ &gpioi { "DHCOM-R", "DHCOM-M", "", "", "", "", "", "", "", "", "", ""; + bootph-all; +}; + +&gpioj { + bootph-all; + +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; }; =20 &i2c4 { @@ -253,6 +299,8 @@ &i2c4 { pinctrl-0 =3D <&i2c4_pins_a>; i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; + bootph-all; + bootph-pre-ram; status =3D "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -269,6 +317,8 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; + bootph-pre-ram; =20 regulators { compatible =3D "st,stpmic1-regulators"; @@ -279,6 +329,7 @@ regulators { ldo6-supply =3D <&v3v3>; pwr_sw1-supply =3D <&bst_out>; pwr_sw2-supply =3D <&bst_out>; + bootph-pre-ram; =20 vddcore: buck1 { regulator-name =3D "vddcore"; @@ -409,12 +460,20 @@ eeprom@50 { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -428,9 +487,22 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; }; =20 &qspi { @@ -444,6 +516,7 @@ &qspi_bk1_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -453,6 +526,28 @@ flash0: flash@0 { spi-max-frequency =3D <108000000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-pre-ram; + }; +}; + +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; }; }; =20 @@ -469,6 +564,15 @@ &rcc { assigned-clocks =3D <&rcc CK_MCO2>, <&rcc PLL4_P>; assigned-clock-parents =3D <&rcc PLL4_P>; assigned-clock-rates =3D <50000000>, <100000000>; + bootph-all; +}; + +®11 { + bootph-pre-ram; +}; + +®18 { + bootph-pre-ram; }; =20 &rng1 { @@ -495,6 +599,7 @@ &sdmmc1 { st,ckin-gpios =3D <&gpioe 4 0>; bus-width =3D <4>; vmmc-supply =3D <&vdd_sd>; + bootph-pre-ram; status =3D "okay"; }; =20 @@ -504,11 +609,24 @@ &sdmmc1_b4_pins_a { * - optional on SoMs with SD voltage translator * - mandatory on SoMs without SD voltage translator */ + bootph-pre-ram; pins1 { bias-pull-up; + bootph-pre-ram; }; pins2 { bias-pull-up; + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; }; }; =20 @@ -525,9 +643,24 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&v3v3>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; @@ -545,7 +678,46 @@ &sdmmc3 { &uart4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + +&usb33 { + bootph-pre-ram; +}; + +&usbotg_hs_pins_a { + bootph-pre-ram; +}; + +&usbotg_hs { + bootph-pre-ram; +}; + +&usbphyc { + bootph-pre-ram; +}; + +&usbphyc_port0 { + bootph-pre-ram; +}; + +&usbphyc_port1 { + bootph-pre-ram; +}; + +&vdd_usb { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index aceeff6c38ba..e7e2203ab11a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -355,6 +355,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_d>; pinctrl-1 =3D <<dc_sleep_pins_d>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -402,9 +403,30 @@ &sdmmc1 { bus-width =3D <4>; vmmc-supply =3D <&vdd_sd>; vqmmc-supply =3D <&sd_switch>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -418,9 +440,27 @@ &sdmmc2 { st,neg-edge; vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd_io>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_b>; @@ -455,11 +495,22 @@ &uart4 { label =3D "LS-UART1"; pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_b>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { /* On Low speed expansion header */ label =3D "LS-UART0"; @@ -512,3 +563,7 @@ &usbphyc_port0 { &usbphyc_port1 { phy-supply =3D <&vdd_usb>; }; + +&vdd_io { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi b/arch= /arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi index bc4ddcbdd5cf..9c6a04b4c2e3 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi @@ -231,9 +231,30 @@ &sdmmc1 { /* MicroSD */ bus-width =3D <4>; vmmc-supply =3D <&vdd>; vqmmc-supply =3D <&vdd>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { /* eMMC */ pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -246,9 +267,27 @@ &sdmmc2 { /* eMMC */ st,neg-edge; vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { /* SDIO Wi-Fi */ pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; @@ -276,11 +315,22 @@ &uart4 { label =3D "UART0"; pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_d>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_d { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart5 { /* X11 UART */ label =3D "X11-UART5"; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boo= t/dts/st/stm32mp15xx-dhcor-som.dtsi index 89881a26c614..3d469e29d41a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi @@ -63,6 +63,30 @@ retram: retram@38000000 { }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -71,11 +95,61 @@ &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c4_pins_a>; i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; + bootph-all; + bootph-pre-ram; status =3D "okay"; /delete-property/dmas; /delete-property/dma-names; @@ -86,6 +160,8 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; + bootph-pre-ram; status =3D "okay"; =20 regulators { @@ -98,6 +174,7 @@ regulators { ldo6-supply =3D <&v3v3>; pwr_sw1-supply =3D <&bst_out>; pwr_sw2-supply =3D <&bst_out>; + bootph-pre-ram; =20 vddcore: buck1 { regulator-name =3D "vddcore"; @@ -215,12 +292,20 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -234,9 +319,23 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; + bootph-pre-ram; }; =20 &qspi { @@ -250,6 +349,7 @@ &qspi_bk1_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -262,6 +362,35 @@ flash0: flash@0 { }; }; =20 +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +®11 { + bootph-pre-ram; +}; + +®18 { + bootph-pre-ram; +}; + &rng1 { status =3D "okay"; }; @@ -269,3 +398,31 @@ &rng1 { &rtc { status =3D "okay"; }; + +&usb33 { + bootph-pre-ram; +}; + +&usbotg_hs_pins_a { + bootph-pre-ram; +}; + +&usbotg_hs { + bootph-pre-ram; +}; + +&usbphyc { + bootph-pre-ram; +}; + +&usbphyc_port0 { + bootph-pre-ram; +}; + +&usbphyc_port1 { + bootph-pre-ram; +}; + +&vdd_usb { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi index 6e79c4b6fe32..3b5debd0ffc9 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi @@ -131,9 +131,30 @@ &sdmmc1 { bus-width =3D <4>; vmmc-supply =3D <&vdd_sd>; vqmmc-supply =3D <&sd_switch>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -147,17 +168,46 @@ &sdmmc2 { st,neg-edge; vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&v3v3>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &uart4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_b>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart7_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/= st/stm32mp15xx-dkx.dtsi index 8cea6facd27b..62d6417ed422 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -129,6 +129,10 @@ channel@19 { }; }; =20 +&bsec { + bootph-all; +}; + &cec { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&cec_pins_b>; @@ -136,6 +140,26 @@ &cec { status =3D "okay"; }; =20 +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -144,6 +168,54 @@ &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + ðernet0 { status =3D "okay"; pinctrl-0 =3D <ðernet0_rgmii_pins_a>; @@ -249,6 +321,7 @@ &i2c4 { i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; clock-frequency =3D <400000>; + bootph-all; status =3D "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -284,6 +357,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; status =3D "okay"; =20 regulators { @@ -422,6 +496,13 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &i2c5 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c5_pins_a>; @@ -458,6 +539,7 @@ &ipcc { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -465,6 +547,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_a>; pinctrl-1 =3D <<dc_sleep_pins_a>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -486,9 +569,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; +}; + +&rcc { + bootph-all; }; =20 &rng1 { @@ -553,9 +653,20 @@ &sdmmc1 { st,neg-edge; bus-width =3D <4>; vmmc-supply =3D <&v3v3>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; @@ -676,11 +787,22 @@ &uart4 { pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart7_pins_c>; --=20 2.43.0 From nobody Mon Feb 9 06:19:24 2026 Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazon11013013.outbound.protection.outlook.com [40.107.162.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B4F5346FD2; Fri, 23 Jan 2026 10:14:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.162.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163283; cv=fail; b=kQ9/3yrciBCrJxuN5LTjB/36Pp8nKBMH/8DG+2np0bU3MMM4HRH8Pp7B40gu1UNt19GVxQzzMcRt5Sze6P2dXr3CKimzm2xoYCXqjvTrP4R5nMX6zOpwyQy9/6w7njArCTFix8Q8tq75yJT0dU0Oc8F3Poz86+J0mHtAOnYkAH4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769163283; c=relaxed/simple; bh=dAktAUZnLIB72g6sjKSzfulK9C07lhLHl8dicrLhRQk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=J+/MC/8eAqCN7ujJ6lTJOeJo098im8mSyjD4ouOKFgBfApYhGObcQDyEj/K17gKlqsyOmIm2Go/5mGVMBECM3+Q+gEaHQFZrxK4mnsHDaJbQPRZiORxiqyb19m7vq/q3nDyhcGY99D4LFWUjq0x9uKgRXPBnNceNS1JUumZasN8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=NNsww5Y3; arc=fail smtp.client-ip=40.107.162.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="NNsww5Y3" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YC1NvcwS51nYtEtFDkQa2DUr01cfoFvt73dBklgPVrIaNZzl/D8kcUrUVRy46yNDQ6Pp9I9bQNXewBXR6jPO8dHz48AdYu+ptY1eKylcrb/QfSCkUnis+2CG7uw2+xGQW54OLbG4l7z4lcc7+lwCddTWBHVCYnU+E/T9s6nVSBWJJQ+DJ8nt6pJ0FI/FaeLcIIm4qOzW2C/OpN5zy5Y7yFnVXP/oNVak/yGY1C+GQ5ILqMFvyePUebawNvP0s5KO8f5PMQY+bw/xtlaRuJttKVo3SBbt88UrX3YXTN01GhXrmRMDojhs3+GaIBWUDcjtjrYQHoSY9m95zqdPgoezSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X11aDf6KhJy4X17wue7HKtKGIYM8acS9medwdl080c8=; b=Ke/g4EgoH5W57Ab2wX+v603UIBR6faVezxIkRRcnvFfYzVioC6E8wZ79D4XfemlZ715h4aBRZPM9KFGUEPd2vC34bF0DWToydJeff4LraVA6OQtvfooyFgMeUTkAsW69Bw7SnQ6tCk/5tWVYjQiFVBqxa9gjNFgzY6gRKW24+q9VZBe3ykPvYF3h6BlOLkoYrvNAlfEJrRBGIX6umv164su3UQ8yDULRF8h7GqwG490uShpxpCIpIBjrNoRNevq79ZpET+gKMcjmq6515zQ3cYEq1BOLdW5rl0ALYMD3aLEMsVAiql6dGkgPCHtQywR9WZN5Ge8Oc+sT80917gRQYw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 164.130.1.59) smtp.rcpttodomain=dh-electronics.com smtp.mailfrom=foss.st.com; dmarc=fail (p=none sp=none pct=100) action=none header.from=foss.st.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X11aDf6KhJy4X17wue7HKtKGIYM8acS9medwdl080c8=; b=NNsww5Y34lP5UfRZ2r3z6GjS4q2WFDu9BV++ZStnD7Y5Nd/t349NldhIAlGmiqHfjDrWwFKgzzAcE4ZM0lBbHC1k69ZzIUxXtdW1MlUmeqY+IEDAGB1ReSCA6Kcv1LhKPFreQsFJhtbCK03STmXZk38qqTCb82flkr6PTJJgDpXjRO4bsVQVDwXr+sukRus7vQJkvvDhFgTq1KQ4skOuAbBjN8gX5dWVkmsF9ArG0M7zp9FZe1PH8fMz7IRN0tA/j/X9RyRhSQ5CXRyv0aJ0vd1SSBVaIY5dAOFWrFRhH5c0jQ8EsI3RSahdq4hYoZ3LKtFOH3RIGoWLh3LNxZi9uw== Received: from DUZP191CA0058.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:4fa::18) by VI0PR10MB8354.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:800:21b::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.11; Fri, 23 Jan 2026 10:14:25 +0000 Received: from DB3PEPF0000885D.eurprd02.prod.outlook.com (2603:10a6:10:4fa:cafe::1a) by DUZP191CA0058.outlook.office365.com (2603:10a6:10:4fa::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.11 via Frontend Transport; Fri, 23 Jan 2026 10:14:23 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 164.130.1.59) smtp.mailfrom=foss.st.com; dkim=none (message not signed) header.d=none;dmarc=fail action=none header.from=foss.st.com; Received-SPF: Fail (protection.outlook.com: domain of foss.st.com does not designate 164.130.1.59 as permitted sender) receiver=protection.outlook.com; client-ip=164.130.1.59; helo=smtpO365.st.com; Received: from smtpO365.st.com (164.130.1.59) by DB3PEPF0000885D.mail.protection.outlook.com (10.167.242.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 23 Jan 2026 10:14:25 +0000 Received: from STKDAG1NODE1.st.com (10.75.128.132) by smtpo365.st.com (10.250.44.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:15:40 +0100 Received: from localhost (10.252.18.201) by STKDAG1NODE1.st.com (10.75.128.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 23 Jan 2026 11:14:08 +0100 From: Patrice Chotard Date: Fri, 23 Jan 2026 11:14:08 +0100 Subject: [PATCH v5 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260123-upstream_uboot_properties-v5-6-5167929d5af5@foss.st.com> References: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> In-Reply-To: <20260123-upstream_uboot_properties-v5-0-5167929d5af5@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB3PEPF0000885D:EE_|VI0PR10MB8354:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e35597a-a91f-44d9-9755-08de5a682f76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?b01MM1U2RU1xWlRTMkxhc05tWmJ6VUVEZWg5Qkx6VUxBMWFVMWs5cTE1a0hJ?= =?utf-8?B?TklRZ3dqR0NINGJOQng5Vkx5cElySlRzWk0rRU1sdjlQYVdxRlpXeXBueHRU?= =?utf-8?B?bXprVzdLQ3FoWXJQRVNLTHo5eVpQRUpUaHpmMTZ3SG81TjdNaEpod3NUeUky?= =?utf-8?B?a2N3VVJ4NGVKaVBJODlMSlFoU3Z1Ky9VLzBHWjhTblptNEhmYlJ0NnlXcW1a?= =?utf-8?B?M2VOMWwwTTJZOVJzZE1uNzRMeDZIK1I2czM3R3VrMWxhbExKNGtUMWlDNjlM?= =?utf-8?B?QUp5Um9hVVpvcDFmNERoOXV3S3hBTkxKZ3FERmJyVEt1ckwyVzBtOGdPYWVu?= =?utf-8?B?U25XNWd1V3dQbHBQMmJIaVJDRVlKY0xuV0RTWUZDVDlFeGFYMU1lbkJFbWVL?= =?utf-8?B?R09COW5aNDlZWXpqeEk5U3Y2UVdTYWY0WDYyV1ViWHhrNWNDM2RXZkhkQmhB?= =?utf-8?B?QTJnejg0V1VLL2tIWXV4OEVXL0RLNDVGTVIwdGNrdWtpWHRlVEREekhzc0pS?= =?utf-8?B?YXZtaG9iSzhNUmZVb2ltQkRBeEZJdHZOOVh0N29GMjhZKzB3ZmI5NnFkbEs4?= =?utf-8?B?V2o1SkdDb1pCMElaVFVyeEIrVFVHTzZTZUxMR2lLeVV0di9sNWdCOS9pWTVx?= =?utf-8?B?UXNjTVZXaURSWXE4VVZwR1lnN1NsLzkzd3pqWmFyRUpzQ1hkRzNKc1p1dm4x?= =?utf-8?B?NkxMNk9Rd1BvVGVibGpJSlVJYXV3SGZiaEpGd0tRY29Xa3ZTNmUxK2tleGZZ?= =?utf-8?B?V0FBR2doUFQyMUVCb1BiVklHa1RSdm83NWhFZy9va1B3czhnMWFuNG95eU5j?= =?utf-8?B?OWU3Mm9qTjhZV212N0pEWFRwWmdVY3AyK2JkeUFpbzVSMmxLOFROTmNuYW8v?= =?utf-8?B?U005dGNlWllrUndhRjREbDdFRGtaQTdiMHg3cHZVT2M0ZkpUZldxQWtpUktw?= =?utf-8?B?dFFpaElGQjlQdk5DbkNjK2czSWlNZW9QZlVFWkcrRDhkWlFPOXc1THhXVjY5?= =?utf-8?B?UnpuSnRrM0VYc0RrbnZ6MndqUncrR2hraGRLZWNaWVREc0FjeVVNMXN6UlNz?= =?utf-8?B?MFFYOUphZEZwSEFCdTA1N1NpWW4xWVVyZDVKS051Z2x5WGY3NFVpeml4dmd4?= =?utf-8?B?NTlRRUVqS1V2UnovYU5VaGNLVDhWdnFOZk5sOWFJVjgzOFVOL0JpL2thUkNj?= =?utf-8?B?U0J0eVVnYm1wSmNTUmpkZ3UwVUxkMFM3Y3pLaXZ6Z3JWaGpTKzhXdENucXBn?= =?utf-8?B?aW9RV3V6dSs4azlYcEZnSytuamNPczRPVlJKbkRyNW9mS1BOSGQwQkJsZS9q?= =?utf-8?B?Y2hYdGhwRE1IRGM0czNCcWhUNTFOeGVoWVY4SnlDMkUvdEdDQTRZMnRDZWV4?= =?utf-8?B?M3RLemF2akgvaWg4N0pQQjhnOVJsb2N6amNuZGNaOEh4blNNT3hZL0FFZE5z?= =?utf-8?B?V0xKQ2NFZmFkYnRWT3FCaXVLNlFDSW9zVDZuY2I1S2Iwd3RMYjV1UTJvZFov?= =?utf-8?B?citUNHZiYVZZY3FmZTM1U2ZyNnZZTkUzTlAxWlQrc0FXN0FQdnVEUVREeGhC?= =?utf-8?B?QWtvVzJOa2drTDNnc2tpcFBFY0RYbVphVFlOdm9VTVpjU0EzUTFLclBLWXo5?= =?utf-8?B?QjJid3JQVFVyNVlnQlhkaEpYZ2VUMUdJWW9NazhjUnZ1L1NHTWRtdTZMTTUr?= =?utf-8?B?dkxrWHFSd0V6MEdTWWk1OVBrN3V2b2htSVBqRHN2bGFIRkhiMWdhejdqS2lB?= =?utf-8?B?QzEyK1VMYW85NEluY2VkWXUwK2lIeTRxNHdyRFY5KzlpSHlJNzhJY2k4bitp?= =?utf-8?B?b2ppaWE0RUtpaFhUWVFCQWJVYlZQOVRLMlYzbktTOHZrU2t2Wlk1ZFRMQkJC?= =?utf-8?B?M21zY2prUzloRnFwMWNCY0trSGpPMW8rbWd5SXNwczVveGlhNzJ3RDR0SnBF?= =?utf-8?B?ZHdzSnU3ek5sZ1BIcytxNGtRejFjZlBoYnV0cUE2cTZ1WVh4OE9ORXlzdEg3?= =?utf-8?B?L3g0V1orTXdZNW9WaVFjTG5senFjS3JtSXFRWDRCZjY5VG5NTE5rTFQxSWRN?= =?utf-8?B?NUgyRGtnNmoySkg5T0hodW5ldVd5eXpQMlBrQWRFS2tXUkRaK2xKcFZpdnBZ?= =?utf-8?B?QTNIYTlhWkR1YnNKKzV4WEpsd0lLTW5sZFMvbFZ6T1hXaStCVGpjaVZpVlhK?= =?utf-8?B?MjArc1BpcmppVWNGT3FUYmh6Ymd3ZGhUZm94ZTRzOUxYTktNNmgrdGpFbEt2?= =?utf-8?B?YTFFck8xbmxPRU5VUGtHekYxTXBnPT0=?= X-Forefront-Antispam-Report: CIP:164.130.1.59;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: 6lpkoSBO5oYFK4tE0vIkZTwbAZql8Y/2+4YvAEq/tHXUHsJZX7+45/b6nPf6IgvK91O1Z6QrTC2bfzBCpyWeOQDsksj60+Kh9oawBXaLLjVReT1+q14ie0XfAQGdJhz2QP+dU2PjEx81h6iKRHp1oOqZFzA4V82nfT8LJlPsN5jl0zZ4+KPMhJNacvw5m1vLYUNgcVtRbX2ciQTlPROhQZnxKN7os+NroQG1qC3vnOPpKSaqK5yFNGkTwKVw/83IaKYig6XrI5GWrw8N06wC7N3o49QHkmiMYYkoMdEnwiLL1/jpS089clknYKKha5KzxJNa5hhUzwUKbnDp6+7CBhL40mQ8S2/f/h94mO+UIFpAtp+caN1UfSVnuXhrmlaaDzOfuRFb/k3CJLxu8dGLrZWfeFMOUgSNkxs1Q0FE1g073s37SefUhKB6U8p+f5Vw/j3axvVf3C+b8nFPkHUcQMdklPCV8mrUZ8IuBjkqXjgaEGuxMFpjgxWVcl1EqroG2QquNYbCCdU8ZCPdFtInR7mIA9U4eltSITywSW0zUDqCbslWvYDKXSzIGGqlE/zPN4tXTYE66nrzbzHmmX95OfmNSmcYBFst9pVLFoXnPjbwLQirpblPnsOWfPcKVu621/VYC0hzrZSNl1lKI+qW0hM1E4Wr+wRp75ep4gcZbOOWzvKweeOt7384jcVFPCX6jjSvFhwX56icu8zGKZ5CEg== X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 10:14:25.1467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e35597a-a91f-44d9-9755-08de5a682f76 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB3PEPF0000885D.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR10MB8354 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 25 +++++++ arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 95 ++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp255.dtsi | 2 +- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 103 +++++++++++++++++++++++++= +++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 105 +++++++++++++++++++++++++= ++++ 8 files changed, 335 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/s= t/stm32mp211.dtsi index bf888d60cd4f..9e9f7f6a580f 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -47,7 +47,7 @@ ck_flexgen_51: clock-200000000 { }; =20 firmware { - optee { + optee: optee { compatible =3D "linaro,optee-tz"; method =3D "smc"; }; @@ -70,7 +70,7 @@ scmi_reset: protocol@16 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..2a003a7c3796 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -44,6 +44,31 @@ &arm_wdt { status =3D "okay"; }; =20 +&optee { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&scmi_reset { + bootph-all; +}; + &usart2 { + bootph-all; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 88e214d395ab..a2f93f6ccb84 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -59,7 +59,7 @@ optee: optee { interrupts =3D ; }; =20 - scmi { + scmi: scmi { compatible =3D "linaro,scmi-optee"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -111,7 +111,7 @@ scmi_vdda18adc: regulator@7 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp235f-dk.dts index c3e688068223..a055d8a2ee99 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -78,6 +78,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 =3D <ð1_rgmii_pins_b>; pinctrl-1 =3D <ð1_rgmii_sleep_pins_b>; @@ -100,6 +104,78 @@ phy1_eth1: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -111,6 +187,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -125,12 +205,27 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index a8e6e0f77b83..4eaf1de3d87f 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -68,7 +68,7 @@ optee: optee { interrupts =3D ; }; =20 - scmi { + scmi: scmi { compatible =3D "linaro,scmi-optee"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -139,7 +139,7 @@ v2m0: v2m@48090000 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index 7a598f53a2a0..3ba4e6166586 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -40,4 +40,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; access-controllers =3D <&rifsc 90>; }; -}; \ No newline at end of file +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index e718d888ce21..080358b134ce 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -78,6 +78,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 =3D <ð1_rgmii_pins_b>; pinctrl-1 =3D <ð1_rgmii_sleep_pins_b>; @@ -100,6 +104,86 @@ phy1_eth1: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -111,6 +195,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -125,12 +213,27 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 6e165073f732..61464076b8d5 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -130,6 +130,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + &combophy { clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_cl= k>; clock-names =3D "apb", "ker", "pad"; @@ -216,6 +220,54 @@ phy0_eth2: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c2_pins_a>; @@ -300,6 +352,7 @@ timer { }; =20 <dc { + bootph-all; status =3D "okay"; port { ltdc_ep0_out: endpoint { @@ -309,6 +362,7 @@ ltdc_ep0_out: endpoint { }; =20 &lvds { + bootph-all; status =3D "okay"; ports { #address-cells =3D <1>; @@ -330,6 +384,10 @@ lvds_out0: endpoint { }; }; =20 +&optee { + bootph-all; +}; + &pcie_ep { pinctrl-names =3D "default", "init"; pinctrl-0 =3D <&pcie_pins_a>; @@ -351,10 +409,38 @@ pcie@0,0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status =3D "okay"; }; =20 +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -386,6 +472,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -400,6 +490,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &spi3 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi3_pins_a>; @@ -477,11 +571,22 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart6 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart6_pins_a>; --=20 2.43.0