From nobody Mon Feb 9 13:57:26 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD57236075B; Fri, 23 Jan 2026 09:27:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769160432; cv=none; b=pn7xE/+tmFNTGYV98zeye1wjZvDszigsiih7oHBgiq+nwV2roDuFnklIf3sgbODBOWgELpM++fNaLllVb1np/QPJjo5c1i2NUGaaxVvQNQjjEBYYZPAQl1FyPX2WC0CANHsEBW221r0LJ6NWjSS54etaH6VumQuUtWmA+K/krGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769160432; c=relaxed/simple; bh=OYQyaNUanZ/szVOiycqY145Jb/KVGUWm/mc3+XgZG6w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tXnEM3rDJTb6ghx0eAhH2LbR+hjMluWvVpNZDiCh/PD0kzb6IpCj5+//pD0NmTc9EUWjvf3V7s58Uk748YG0FY2/BDuzFyGl3F0YyZiwsFwQUkPm3t3X4lTldZrqYULq+0oAeFAnIkvg18/y6SzHQMUarNLYHSG4mJ7oi/la0Mc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 23 Jan 2026 17:26:27 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 23 Jan 2026 17:26:27 +0800 From: Billy Tsai Date: Fri, 23 Jan 2026 17:26:30 +0800 Subject: [PATCH v2 5/6] dt-bindings: gpio: aspeed,sgpio: Support ast2700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260123-upstream_sgpio-v2-5-69cfd1631400@aspeedtech.com> References: <20260123-upstream_sgpio-v2-0-69cfd1631400@aspeedtech.com> In-Reply-To: <20260123-upstream_sgpio-v2-0-69cfd1631400@aspeedtech.com> To: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Andrew Jeffery" , , , Billy Tsai , "Krzysztof Kozlowski" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769160386; l=1452; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=OYQyaNUanZ/szVOiycqY145Jb/KVGUWm/mc3+XgZG6w=; b=VR/6NrxX2u5NjM3K8c6vXsi9KCB2tRBkKiyvhKw5FtnZxjYkpWWICR6Q7XiO80MXlaG/NgSGU lNfThdxLSPjAhGQCLHzTpsLj2b2Q7iHdkVl6VaZUEW8DsGoLzKIKlyn X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= The AST2700 is the 7th generation SoC from Aspeed, featuring two SGPIO master controllers: both with 256 serial inputs and outputs. Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Signed-off-by: Billy Tsai --- Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Doc= umentation/devicetree/bindings/gpio/aspeed,sgpio.yaml index 1046f0331c09..974185e3478f 100644 --- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml @@ -10,7 +10,8 @@ maintainers: - Andrew Jeffery =20 description: - This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC, + This SGPIO controller is for ASPEED AST2400, AST2500, AST2600 and AST270= 0 SoC, + AST2700 have two sgpio master both with 256 pins, AST2600 have two sgpio master one with 128 pins another one with 80 pins, AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial GPIO pins can be programmed to support the following options @@ -27,6 +28,7 @@ properties: - aspeed,ast2400-sgpio - aspeed,ast2500-sgpio - aspeed,ast2600-sgpiom + - aspeed,ast2700-sgpiom =20 reg: maxItems: 1 --=20 2.34.1