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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jan 2026 06:56:09.9044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: beb4d8e9-c521-4b55-325d-08de5a4c7d5b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR10MB6008 Update the bindings to allow setting per-line interrupt-types. Some Interrupt Router instances can only work with a specific trigger type (edge or level), while others act as simple passthroughs that preserve the source interrupt type unchanged. Make "ti,intr-trigger-type" property optional, with its absence indicating that the router acts as a passthrough. When absent, "#interrupt-cells" must be 2 to allow each interrupt source to specify its trigger type per-line. Signed-off-by: Aniket Limaye Reviewed-by: Rob Herring (Arm) --- Changes in v4: - Don't repeat property descriptions at multiple places - Use generic name for DT example node and remove the label - Collected R-b - Link to v3: https://lore.kernel.org/r/20260122-ul-driver-i2c-j722s-v3-1-4= ec3478f3866@ti.com Changes in v3: - Avoid new redundant value IRQ_TYPE_DEFAULT for "ti,intr-trigger-type" when "#interrupt-cells"=3D=3D2. Instead, make this property optional and check for its absence to use the per-line interrupt-type setting. - Link to v2: https://lore.kernel.org/r/20260120-ul-driver-i2c-j722s-v2-1-832097c6b64f@ti= .com Changes in v2: - Reword Commit msg to better describe the patch - Link to v1: https://lore.kernel.org/r/20260116-ul-driver-i2c-j722s-v1-1-c28e8ba38a9e@ti= .com --- .../bindings/interrupt-controller/ti,sci-intr.yaml | 38 ++++++++++++++++++= +--- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-= intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-i= ntr.yaml index c99cc7323c71..de45f0c4b1d1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.ya= ml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.ya= ml @@ -15,8 +15,7 @@ allOf: description: | The Interrupt Router (INTR) module provides a mechanism to mux M interrupt inputs to N interrupt outputs, where all M inputs are selectab= le - to be driven per N output. An Interrupt Router can either handle edge - triggered or level triggered interrupts and that is fixed in hardware. + to be driven per N output. =20 Interrupt Router +----------------------+ @@ -64,9 +63,14 @@ properties: interrupt-controller: true =20 '#interrupt-cells': - const: 1 + enum: [1, 2] description: | - The 1st cell should contain interrupt router input hw number. + Number of cells in interrupt specifier. Depends on ti,intr-trigger-t= ype: + - If ti,intr-trigger-type is present: must be 1 + The 1st cell should contain interrupt router input hw number. + - If ti,intr-trigger-type is absent: must be 2 + The 1st cell should contain interrupt router input hw number. + The 2nd cell should contain interrupt trigger type (preserved by r= outer). =20 ti,interrupt-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix @@ -82,9 +86,22 @@ properties: - description: | "limit" specifies the limit for translation =20 +if: + required: + - ti,intr-trigger-type +then: + properties: + '#interrupt-cells': + const: 1 + description: Interrupt ID only. Interrupt type is specified globally +else: + properties: + '#interrupt-cells': + const: 2 + description: Interrupt ID and corresponding interrupt type + required: - compatible - - ti,intr-trigger-type - interrupt-controller - '#interrupt-cells' - ti,sci @@ -105,3 +122,14 @@ examples: ti,sci-dev-id =3D <131>; ti,interrupt-ranges =3D <0 360 32>; }; + + - | + interrupt-controller { + compatible =3D "ti,sci-intr"; + interrupt-controller; + interrupt-parent =3D <&gic500>; + #interrupt-cells =3D <2>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <131>; + ti,interrupt-ranges =3D <0 360 32>; + }; --=20 2.52.0