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Fri, 23 Jan 2026 07:39:27 -0800 (PST) From: Charan Pedumuru Date: Fri, 23 Jan 2026 15:39:02 +0000 Subject: [PATCH v4 1/3] arm: dts: ti: omap: align node patterns with established convention Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-ti-phy-v4-1-b557e2c46e6f@gmail.com> References: <20260123-ti-phy-v4-0-b557e2c46e6f@gmail.com> In-Reply-To: <20260123-ti-phy-v4-0-b557e2c46e6f@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren , Roger Quadros Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Charan Pedumuru X-Mailer: b4 0.14.3 Update OMAP DTS node patterns to match established conventions. Signed-off-by: Charan Pedumuru --- arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 4 ++-- arch/arm/boot/dts/ti/omap/omap4-l4.dtsi | 4 ++-- arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/= omap/dra7-l4.dtsi index c9282f57ffa5..ed206eb84d02 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -328,7 +328,7 @@ ocp2scp@0 { ranges =3D <0 0 0x8000>; reg =3D <0x0 0x20>; =20 - pcie1_phy: pciephy@4000 { + pcie1_phy: pcie-phy@4000 { compatible =3D "ti,phy-pipe3-pcie"; reg =3D <0x4000 0x80>, /* phy_rx */ <0x4400 0x64>; /* phy_tx */ @@ -348,7 +348,7 @@ pcie1_phy: pciephy@4000 { #phy-cells =3D <0>; }; =20 - pcie2_phy: pciephy@5000 { + pcie2_phy: pcie-phy@5000 { compatible =3D "ti,phy-pipe3-pcie"; reg =3D <0x5000 0x80>, /* phy_rx */ <0x5400 0x64>; /* phy_tx */ diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti= /omap/omap4-l4.dtsi index 4ee53dfb71b4..d8b16cbe6c35 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -72,13 +72,13 @@ scm_conf: scm_conf@0 { #size-cells =3D <1>; }; =20 - omap_control_usb2phy: control-phy@300 { + omap_control_usb2phy: phy@300 { compatible =3D "ti,control-phy-usb2"; reg =3D <0x300 0x4>; reg-names =3D "power"; }; =20 - omap_control_usbotg: control-phy@33c { + omap_control_usbotg: phy@33c { compatible =3D "ti,control-phy-otghs"; reg =3D <0x33c 0x4>; reg-names =3D "otghs_control"; diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti= /omap/omap5-l4.dtsi index 9f6100c7c34d..5c94db589dd1 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi @@ -472,7 +472,7 @@ usb2_phy: usb2phy@4000 { #phy-cells =3D <0>; }; =20 - usb3_phy: usb3phy@4400 { + usb3_phy: usb3-phy@4400 { compatible =3D "ti,omap-usb3"; reg =3D <0x4400 0x80>, <0x4800 0x64>, --=20 2.52.0 From nobody Sat Feb 7 08:44:16 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8CD22848A7 for ; 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Fri, 23 Jan 2026 07:39:32 -0800 (PST) Received: from Black-Pearl.localdomain ([115.99.251.203]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2a802f9769esm23732205ad.60.2026.01.23.07.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 07:39:31 -0800 (PST) From: Charan Pedumuru Date: Fri, 23 Jan 2026 15:39:03 +0000 Subject: [PATCH v4 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-ti-phy-v4-2-b557e2c46e6f@gmail.com> References: <20260123-ti-phy-v4-0-b557e2c46e6f@gmail.com> In-Reply-To: <20260123-ti-phy-v4-0-b557e2c46e6f@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren , Roger Quadros Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Charan Pedumuru X-Mailer: b4 0.14.3 Convert TI PIPE3 PHY binding to DT schema. Changes during conversion: - Define a new pattern 'pcie-phy' to match nodes defined in DT. - Drop obsolete "id" property from the schema. Signed-off-by: Charan Pedumuru Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/phy/ti,phy-usb3.yaml | 138 +++++++++++++++++= ++++ 1 file changed, 138 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Docum= entation/devicetree/bindings/phy/ti,phy-usb3.yaml new file mode 100644 index 000000000000..84f538aa587c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI PIPE3 PHY Module + +maintainers: + - Roger Quadros + +description: + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer) + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs. + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3 + interface standard, which defines a common physical layer for + high-speed serial interfaces. + +properties: + $nodename: + pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$" + + compatible: + enum: + - ti,omap-usb3 + - ti,phy-pipe3-pcie + - ti,phy-pipe3-sata + - ti,phy-usb3 + + reg: + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + items: + - const: phy_rx + - const: phy_tx + - const: pll_ctrl + + "#phy-cells": + const: 0 + + clocks: + minItems: 2 + maxItems: 7 + + clock-names: + minItems: 2 + maxItems: 7 + items: + enum: [wkupclk, sysclk, refclk, dpll_ref, + dpll_ref_m2, phy-div, div-clk] + + syscon-phy-power: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + items: + - description: Phandle to the system control module + - description: Register offset controlling PHY power + + syscon-pllreset: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + items: + - description: Phandle to the system control module + - description: Register offset of CTRL_CORE_SMA_SW_0 + + syscon-pcs: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + items: + - description: Phandle to the system control module + - description: Register offset for PCS delay programming + + ctrl-module: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of control module for PHY power on. + deprecated: true + +allOf: + - if: + properties: + compatible: + contains: + const: ti,phy-pipe3-sata + then: + properties: + syscon-pllreset: true + else: + properties: + syscon-pllreset: false + +required: + - reg + - compatible + - reg-names + - "#phy-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + /* TI PIPE3 USB3 PHY */ + usb3-phy@4a084400 { + compatible =3D "ti,phy-usb3"; + reg =3D <0x4a084400 0x80>, + <0x4a084800 0x64>, + <0x4a084c00 0x40>; + reg-names =3D "phy_rx", "phy_tx", "pll_ctrl"; + #phy-cells =3D <0>; + clocks =3D <&usb_phy_cm_clk32k>, + <&sys_clkin>, + <&usb_otg_ss_refclk960m>; + clock-names =3D "wkupclk", "sysclk", "refclk"; + ctrl-module =3D <&omap_control_usb>; + }; + + - | + /* TI PIPE3 SATA PHY */ + phy@4a096000 { + compatible =3D "ti,phy-pipe3-sata"; + reg =3D <0x4a096000 0x80>, /* phy_rx */ + <0x4a096400 0x64>, /* phy_tx */ + <0x4a096800 0x40>; /* pll_ctrl */ + reg-names =3D "phy_rx", "phy_tx", "pll_ctrl"; + clocks =3D <&sys_clkin1>, <&sata_ref_clk>; + clock-names =3D "sysclk", "refclk"; + syscon-pllreset =3D <&scm_conf 0x3fc>; + #phy-cells =3D <0>; + }; +... --=20 2.52.0 From nobody Sat Feb 7 08:44:16 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 900823093C0 for ; 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Fri, 23 Jan 2026 07:39:36 -0800 (PST) Received: from Black-Pearl.localdomain ([115.99.251.203]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2a802f9769esm23732205ad.60.2026.01.23.07.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 07:39:36 -0800 (PST) From: Charan Pedumuru Date: Fri, 23 Jan 2026 15:39:04 +0000 Subject: [PATCH v4 3/3] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-ti-phy-v4-3-b557e2c46e6f@gmail.com> References: <20260123-ti-phy-v4-0-b557e2c46e6f@gmail.com> In-Reply-To: <20260123-ti-phy-v4-0-b557e2c46e6f@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren , Roger Quadros Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Charan Pedumuru X-Mailer: b4 0.14.3 Convert TI OMAP Control PHY binding to DT schema. Reviewed-by: Rob Herring (Arm) Signed-off-by: Charan Pedumuru --- .../bindings/phy/ti,control-phy-otghs.yaml | 99 ++++++++++++++++++= ++++ Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ------------------= --- 2 files changed, 99 insertions(+), 98 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yam= l b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml new file mode 100644 index 000000000000..4ecb1611ee65 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP Control PHY Module + +maintainers: + - Roger Quadros + +description: + The TI OMAP Control PHY module is a hardware block within the system + control module (SCM) of Texas Instruments OMAP SoCs. It provides + centralized control over power, configuration, and auxiliary features + for multiple on-chip PHYs. This module is essential for proper PHY + operation in power-constrained embedded systems. + +properties: + $nodename: + pattern: "^phy@[0-9a-f]+$" + + compatible: + enum: + - ti,control-phy-otghs + - ti,control-phy-pcie + - ti,control-phy-pipe3 + - ti,control-phy-usb2 + - ti,control-phy-usb2-am437 + - ti,control-phy-usb2-dra7 + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + minItems: 1 + maxItems: 3 + items: + enum: [otghs_control, power, pcie_pcs, control_sma] + +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,control-phy-otghs + then: + properties: + reg-names: + const: otghs_control + + - if: + properties: + compatible: + contains: + enum: + - ti,control-phy-pcie + then: + properties: + reg: + minItems: 3 + + reg-names: + items: + - const: power + - const: pcie_pcs + - const: control_sma + + - if: + properties: + compatible: + contains: + enum: + - ti,control-phy-usb2 + - ti,control-phy-usb2-dra7 + - ti,control-phy-usb2-am437 + - ti,control-phy-pipe3 + then: + properties: + reg-names: + const: power + +required: + - reg + - compatible + - reg-names + +unevaluatedProperties: false + +examples: + - | + phy@4a00233c { + compatible =3D "ti,control-phy-otghs"; + reg =3D <0x4a00233c 0x4>; + reg-names =3D "otghs_control"; + }; +... diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentati= on/devicetree/bindings/phy/ti-phy.txt deleted file mode 100644 index 7c7936b89f2c..000000000000 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ /dev/null @@ -1,98 +0,0 @@ -TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs - -OMAP CONTROL PHY - -Required properties: - - compatible: Should be one of - "ti,control-phy-otghs" - if it has otghs_control mailbox register as on O= MAP4. - "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf regi= ster - e.g. USB2_PHY on OMAP5. - "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power cont= rol - e.g. USB3 PHY and SATA PHY on OMAP5. - "ti,control-phy-pcie" - for pcie to support external clock for pcie and to - set PCS delay value. - e.g. PCIE PHY in DRA7x - "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY = on - DRA7 platform. - "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY= on - AM437 platform. - - reg : register ranges as listed in the reg-names property - - reg-names: "otghs_control" for control-phy-otghs - "power", "pcie_pcs" and "control_sma" for control-phy-pcie - "power" for all other types - -omap_control_usb: omap-control-usb@4a002300 { - compatible =3D "ti,control-phy-otghs"; - reg =3D <0x4a00233c 0x4>; - reg-names =3D "otghs_control"; -}; - -TI PIPE3 PHY - -Required properties: - - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or - "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated. - - reg : Address and length of the register set for the device. - - reg-names: The names of the register addresses corresponding to the reg= isters - filled in "reg". - - #phy-cells: determine the number of cells that should be given in the - phandle while referencing this phy. - - clocks: a list of phandles and clock-specifier pairs, one for each entr= y in - clock-names. - - clock-names: should include: - * "wkupclk" - wakeup clock. - * "sysclk" - system clock. - * "refclk" - reference clock. - * "dpll_ref" - external dpll ref clk - * "dpll_ref_m2" - external dpll ref clk - * "phy-div" - divider for apll - * "div-clk" - apll clock - -Optional properties: - - id: If there are multiple instance of the same type, in order to - differentiate between each instance "id" can be used (e.g., multi-lane = PCIe - PHY). If "id" is not provided, it is set to default value of '1'. - - syscon-pllreset: Handle to system control region that contains the - CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW= _0 - register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata= _phy. - - syscon-pcs : phandle/offset pair. Phandle to the system control module = and the - register offset to write the PCS delay value. - -Deprecated properties: - - ctrl-module : phandle of the control module used by PHY driver to power= on - the PHY. - -Recommended properties: - - syscon-phy-power : phandle/offset pair. Phandle to the system control - module and the register offset to power on/off the PHY. - -This is usually a subnode of ocp2scp to which it is connected. - -usb3phy@4a084400 { - compatible =3D "ti,phy-usb3"; - reg =3D <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names =3D "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module =3D <&omap_control_usb>; - #phy-cells =3D <0>; - clocks =3D <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&usb_otg_ss_refclk960m>; - clock-names =3D "wkupclk", - "sysclk", - "refclk"; -}; - -sata_phy: phy@4a096000 { - compatible =3D "ti,phy-pipe3-sata"; - reg =3D <0x4A096000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names =3D "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module =3D <&omap_control_sata>; - clocks =3D <&sys_clkin1>, <&sata_ref_clk>; - clock-names =3D "sysclk", "refclk"; - syscon-pllreset =3D <&scm_conf 0x3fc>; - #phy-cells =3D <0>; -}; --=20 2.52.0