From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oi1-f180.google.com (mail-oi1-f180.google.com [209.85.167.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCCDA2EC080 for ; Fri, 23 Jan 2026 20:38:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200724; cv=none; b=iMoccMnywWIIqzKFn5CyPiWvGmj0bRPFQSWZbYY1XWC+8FFHJeY+m8LOhcm6KyNBg7pnBeAJKQqlreTfwGXlcMD6F4mV4fx0HtqTfTV7CYFLQ3cdVKkOHjrgHkdGFzGRDHcr9VTaUCTglSlzJHz8ECBcet2PfPsi34SsFDUekNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200724; c=relaxed/simple; bh=h+Hpg7mAV/rUr3EzlDZhbxTF2vRK/83Uj6sS1/n0P24=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=srmhVfDO0YI2L57XwNclT/HkYm87Y2gHqYBIOnYboxixcPk+zsD7er8RgFmBBQ1cNrJ15DIBQCeT+iYIZHaiW0Yuc1wN+VcxBEtSFzqsS9pdArsig/sa0JOBqvzYnKn20MevG0Nhu4w7d63ze35Bb2GZ9rmUMRMCuej7/wmOBdc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=QtWTFb7S; arc=none smtp.client-ip=209.85.167.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="QtWTFb7S" Received: by mail-oi1-f180.google.com with SMTP id 5614622812f47-45c8e85deffso835063b6e.1 for ; Fri, 23 Jan 2026 12:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200720; x=1769805520; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=X31guPVFU+0+g2QDbsPtzUxPVvF8hORfxCmewEdgT3I=; b=QtWTFb7Sap5I2lNgkyWwgfbedNfd766WaAJfIgMyW433VuvbmpDJ5xQqGavCX+crc6 lphRAUxu+sBKG7H/26KVz7s11jGcNEmH65SBK94ZcwzsY+i8lLor1hwkPXBYgw8wn2O8 olIEaWt5wU+ylP75s/vFhfRyjPf8FMML04aoHcy639XIlq5P42HCSe643PuWxTWptBA0 CnPb0H2XjMC8N71fWvQj9hmQRFL/WvUmpRe28MIfLJ9Dq5cA5hPaYXfT5QgS1xUXOEB9 PF5AlL+2eSweGWiStJcu08kKsdOlxJ6Y2lHPUV/02JjjvG2CDD0ZBCvmCWYoEKmFiLNm V8Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200720; x=1769805520; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=X31guPVFU+0+g2QDbsPtzUxPVvF8hORfxCmewEdgT3I=; b=vWTEooeuvuZHwe9QPZwjqc6u4mtESu5otQrvM2NfPhVwfpWxAVghkEx0KnWs5nfRDb oqPELOkFlaApW/Z2qn7NjM+hdtMHJ1xI/damBNsQJvilz6n2ZM38Yz9/zq9rHxq9pqW3 npSvlZ7vNNrJwcCBRbR8q4abZ+iCeTXS1gmjsO3ZrMfIizSraefxy7NXW6KnWIPgmk3a T6zH38+2e8CY2VNrJcTkM1maUhSMivBfv1rRsu1ISXBsBoO9x+nu6giuebL0tA55H+Vg i6lxTM6X5RvzfUmAgg4rwiMZofRQLQQN2mugKm3e5Jzhgjq7nPEeKvnljjOrDwhbskk3 i/yQ== X-Forwarded-Encrypted: i=1; AJvYcCU55ZHkZzBvXCWWk6jCqBv2KjP0/attcB5GwCL+0vZ5Sy2czwWDYTjltOEXDbGQMxZrPkdOUuTrNxGPikU=@vger.kernel.org X-Gm-Message-State: AOJu0Yxzah0lW9nRAjLR8C4XmVl46pxbMiEg+XX6xY0T2WmxU9swqQoc dw+WJHimFSzhSigG5K7iJq/jBjMOz/oaVIPVnQUJdPgigs4Uq3EmsJDFD5tkebRKSOw= X-Gm-Gg: AZuq6aKpWZoPoeQk23ArIm2XRKZQKIhgBP1KH6KKrlhv05vhEQX59187Jez3uCQnYqp 62gD5eZ/G4Q0MNsuvv+08I/IdWPFUmIGK90+pkVJUhVvHC+G8MtyT77lIfVgShM2wC90PFc2+Uh tW2ckm5+OCpjxwcBoFLr1ZvgDMvhn3yOppBZMOzrQrEVGPwLUok4+7JB2yHoGXWjwVGL65B2XM8 zsL9z4hxRxeJe7mLG2KuMXCcMlplY53T0F1AF2tHW3qFXp0pqbuUMFZUF54aJcbKK/laAwHiq90 5YSTbn/vEZr4z6KKVF2YdmWeaWRxPuxHxxxnmSFkJn9aaH791WKYIJj1Hylp7KBOLkk7Treh3mc YV+rfxefbspkEzgkf7KOJxGULagGGV2aKZbxyCwVbp00T1EUjsvSWPRN5y50oMOQ58NgOCCkYxn Z0x68sScno7wZJrg== X-Received: by 2002:a05:6808:f92:b0:442:2ce:46cf with SMTP id 5614622812f47-45eb1cbd54dmr1926865b6e.34.1769200720002; Fri, 23 Jan 2026 12:38:40 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:38 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:24 -0600 Subject: [PATCH v6 1/9] spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-1-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9966; i=dlechner@baylibre.com; h=from:subject:message-id; bh=h+Hpg7mAV/rUr3EzlDZhbxTF2vRK/83Uj6sS1/n0P24=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9wQqZDKLcDnrd9zEHZlWK7sz4Ww9Io0Qzt/M zWhNrfZjIiJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcEAAKCRDCzCAB/wGP wLoRB/9XMTjSOrAEY36OQZc/Jvqp2t8wG2+pZqUiEg5iibEFWrwvkqbaCp+PvRWJm9BswMRWqJ+ A8eYOIm6WYbp6WjaowfkT6B38kqVuwdwtIU1WqEmLARZVFzJ4AHe2qYg/U7sY0kRVCemj/2gOqP 7vaTf68UpDe0Tp57aZDLUAygTMMvxeFhjfO718dE8PqrN7DTK8PbcNtEAkTmqOBUj3pgwQVCJkE Vb3vImkqkDzgedxFqA0Zz2pt0wJvuXOJLE8Ab05KnIPfu4U/iaDPysJ6cwxMmzMtxKk66RmfM/x iBXwKAuTIzGV0feHJR28DG+uv2nWjCx3FFvyRmgqn0u7vvmb X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Change spi-rx-bus-width and spi-tx-bus-width properties from single uint32 values to arrays of uint32 values. This allows describing SPI peripherals connected to controllers that have multiple data lanes for receiving or transmitting two or more words in parallel. Each index in the array corresponds to a physical data lane (one or more wires depending on the bus width). Additional mapping properties will be needed in cases where a lane on the controller or peripheral is skipped. Bindings that make use of this property are updated in the same commit to avoid validation errors. The adi,ad4030 binding can now better describe the chips multi-lane capabilities, so that binding is refined and gets a new example. Converting from single uint32 to array of uint32 does not break .dts/ .dtb files since there is no difference between specifying a single uint32 value and an array with a single uint32 value in devicetree. Reviewed-by: Rob Herring (Arm) Reviewed-by: Marcelo Schmitt Reviewed-by: Jonathan Cameron Signed-off-by: David Lechner --- v6 changes: none v5 changes: - Added change for andestech,ae350-spi.yaml (recently new file). v4 changes: - New patch to replace data-lanes property patch. In v3, Rob suggested possibly splitting the spi-controller.yaml file to have a way to make most SPI controllers have maxItems: 1 for these properties. I would like to avoid that because it doesn't seem scalable, e.g. if we need another similar split in the future, the number of combinations would grow exponentially (factorially?). I have an idea to instead do this using $dynamicAnchor and $dynamicRef, but dt-schema doesn't currently support that. So I propose we do the best we can for now with the current dt-schema and make further improvements later. Also, in v3, I suggested that we could have leading 0s in the arrays to indicate unused lanes. But after further consideration, I think it's better to have separate lane-mapping properties for that purpose. It will be easier to explain and parse and be a bit more flexible that way. --- .../bindings/display/panel/sitronix,st7789v.yaml | 5 +-- .../devicetree/bindings/iio/adc/adi,ad4030.yaml | 42 ++++++++++++++++++= +++- .../devicetree/bindings/iio/adc/adi,ad4695.yaml | 5 +-- .../bindings/spi/allwinner,sun4i-a10-spi.yaml | 6 ++-- .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 6 ++-- .../bindings/spi/andestech,ae350-spi.yaml | 6 ++-- .../bindings/spi/nvidia,tegra210-quad.yaml | 6 ++-- .../bindings/spi/spi-peripheral-props.yaml | 26 ++++++++++---- 8 files changed, 83 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st778= 9v.yaml b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.= yaml index 0ce2ea13583d..c35d4f2ab9a4 100644 --- a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml +++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml @@ -34,8 +34,9 @@ properties: spi-cpol: true =20 spi-rx-bus-width: - minimum: 0 - maximum: 1 + items: + minimum: 0 + maximum: 1 =20 dc-gpios: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 54e7349317b7..e22d518135f2 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -37,7 +37,15 @@ properties: maximum: 102040816 =20 spi-rx-bus-width: - enum: [1, 2, 4] + maxItems: 2 + # all lanes must have the same width + oneOf: + - contains: + const: 1 + - contains: + const: 2 + - contains: + const: 4 =20 vdd-5v-supply: true vdd-1v8-supply: true @@ -88,6 +96,18 @@ oneOf: =20 unevaluatedProperties: false =20 +allOf: + - if: + properties: + compatible: + enum: + - adi,ad4030-24 + - adi,ad4032-24 + then: + properties: + spi-rx-bus-width: + maxItems: 1 + examples: - | #include @@ -108,3 +128,23 @@ examples: reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; }; }; + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4630-24"; + reg =3D <0>; + spi-max-frequency =3D <80000000>; + spi-rx-bus-width =3D <4>, <4>; + vdd-5v-supply =3D <&supply_5V>; + vdd-1v8-supply =3D <&supply_1_8V>; + vio-supply =3D <&supply_1_8V>; + ref-supply =3D <&supply_5V>; + cnv-gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4695.yaml index cbde7a0505d2..ae8d0b5f328b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml @@ -38,8 +38,9 @@ properties: spi-cpha: true =20 spi-rx-bus-width: - minimum: 1 - maximum: 4 + items: + minimum: 1 + maximum: 4 =20 avdd-supply: description: Analog power supply. diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml index e1ab3f523ad6..a34e6471dbe8 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml @@ -55,10 +55,12 @@ patternProperties: maximum: 4 =20 spi-rx-bus-width: - const: 1 + items: + - const: 1 =20 spi-tx-bus-width: - const: 1 + items: + - const: 1 =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 1b91d1566c95..a6067030c5ed 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -81,10 +81,12 @@ patternProperties: maximum: 4 =20 spi-rx-bus-width: - const: 1 + items: + - const: 1 =20 spi-tx-bus-width: - const: 1 + items: + - const: 1 =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml= b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml index 78093468dd5e..8e441742cee6 100644 --- a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml +++ b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml @@ -45,10 +45,12 @@ patternProperties: =20 properties: spi-rx-bus-width: - enum: [1, 4] + items: + - enum: [1, 4] =20 spi-tx-bus-width: - enum: [1, 4] + items: + - enum: [1, 4] =20 allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yam= l b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 8b3640280559..909c204b8adf 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -54,10 +54,12 @@ patternProperties: =20 properties: spi-rx-bus-width: - enum: [1, 2, 4] + items: + - enum: [1, 2, 4] =20 spi-tx-bus-width: - enum: [1, 2, 4] + items: + - enum: [1, 2, 4] =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8b6e8fc009db..59ddead7da14 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -64,9 +64,16 @@ properties: description: Bus width to the SPI bus used for read transfers. If 0 is provided, then no RX will be possible on this device. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 4, 8] - default: 1 + + Some SPI peripherals and controllers may have multiple data lanes for + receiving two or more words at the same time. If this is the case, e= ach + index in the array represents the lane on both the SPI peripheral and + controller. Additional mapping properties may be needed if a lane is + skipped on either side. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + enum: [0, 1, 2, 4, 8] + default: [1] =20 spi-rx-delay-us: description: @@ -81,9 +88,16 @@ properties: description: Bus width to the SPI bus used for write transfers. If 0 is provided, then no TX will be possible on this device. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 4, 8] - default: 1 + + Some SPI peripherals and controllers may have multiple data lanes for + transmitting two or more words at the same time. If this is the case= , each + index in the array represents the lane on both the SPI peripheral and + controller. Additional mapping properties may be needed if a lane is + skipped on either side. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + enum: [0, 1, 2, 4, 8] + default: [1] =20 spi-tx-delay-us: description: --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oa1-f48.google.com (mail-oa1-f48.google.com [209.85.160.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79F762EDD7E for ; Fri, 23 Jan 2026 20:38:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200732; cv=none; b=RAQGLK/3GD1Evd77cvRJl0MYn3JGOrsSBtlbC0irKn+g2SkRgAedxGv9Zx/9lEeUrac6Txd11YsmC8go68yG4evx4/Fe3PYyaZ3AMdU+kvzvlObi/fd5WiCDXwqBkG+R29QxXPbaF/Frb6hdwpSfgpw5LWJE4XLercfORtRVsVo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200732; c=relaxed/simple; bh=5HI91WzF40M7BWTtVwSgdEEKhH3jYAKO9/9e2UnBD7E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kzYyXu5jMKPVMRTrlmsKFbhcj3R+v9xoBujfD02oYyv0nYv07j+fF5gtdIQFozGH0i6QhLM1gVQRkjQdVwUDnfkiLvz+AMOURg4xRcD6P0xwGLrR/8g2mr1HKaoEcoLEy0XegprRsaTeZOTmVjq+tzBONbIcFcvKkSv8h1tGUmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=N1vzP6UR; arc=none smtp.client-ip=209.85.160.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="N1vzP6UR" Received: by mail-oa1-f48.google.com with SMTP id 586e51a60fabf-4041c73ab4dso807216fac.2 for ; Fri, 23 Jan 2026 12:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200727; x=1769805527; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AT2w5VHT92aNGbPwdimSOxfLAza15/pSQtaUPTXFgbE=; b=N1vzP6URqyUxf24UhIs9rBrUb5eqnl1oUSXwsDs5gvV8BkXHTWO4/MtzeojU8PWIHs C7UTIMRDrpUgsjdcDN2Texd03sS2V9XBr5ONOLBOFcZQe4HVloe75iJmS3dfBMZdgeuO JCebSyy46de8nvfBFFZNvF5Bcc9IDyR1zhADwXR8idCxEqEXr8orDEjbdVzi7iQr5gl6 ZC9oeAswYXv5SWMRbb9EG0jmDLgru3cEq5lDN3U5C5yzD+536iSGDx/GmD5Wje4/imcT 9jH2Jc35yZBefo+1mJa3RxnzA9WWjuA92USJeihYKRyhkr4zO9svHpnY95vDyy5medho AkAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200727; x=1769805527; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=AT2w5VHT92aNGbPwdimSOxfLAza15/pSQtaUPTXFgbE=; b=qLWiIe55VJogYgDtyKbZckqdWlqTHPCeBapXfped6cO8Sqo9LKs86Z1polWOvnX5Vs psNjt4wLiuucLGoo2rO9uJsVVYYZL4cvV+Vi7VwcISUS9fFBuC/gEMmLZYKmoozN1wfK FzDhldFyA+JXtoxKpcdaMkz1TqtvNWuHl9G4Iq871fFqRktsVyUKs368SfuBp6zu3r8a waMDyjbeeNVp6io/M9zVHTzeTXdU3PUaQwiS73M3WnwZJfQ1BAo/J5Wj8w8BKSyqostO 0QCy8/92tQEOFN9BSpC3HeCUqjK+n+hmzo+X1KKtgMJEWyDgAEzy0NIJkd9b1BpfmhFR EvzA== X-Forwarded-Encrypted: i=1; AJvYcCWNHTL0geHwUovnPNpnk0jHdKqXMpkbSSu5TCs2beeWB5pxCgERzz39PFokbT2Udnw2EyH2VqiF3OCWD7g=@vger.kernel.org X-Gm-Message-State: AOJu0YwVslBGDoxBfiVCZhGuUvSQPqcVh9FINBGDTvc3cQQQoVjMmoGh il3NkFzRyQkrboa7I+KEWdaOWNy+pWdkEIUDxmEhjaN4yGgF7/IyudD8l8AmNcY0FDQ= X-Gm-Gg: AZuq6aLNUgIRRb2fVcwF/FjromeSD8LC7sYoPoiy5oL09bHzOJRRHEudoCHWMMl0tJH w3765szvidZ2YUhIH6lJzrXlT3nFRq9JyJ9SzE5NtqhraT8oZGeV0CyfX9G1Rk6gqQSnQxkr+hI Td6FSH4dIcweYplFTPAdYiPg9S0uPO90qWfJNVCgyMrzspCWxS+w1UFlX+/stNg7kLt+ENSwiSS 33GdHhIGDaNoP/a2T0vktYaYJnkiwJBZYmpM9+B5HBz/TP03AAzZN93yN+YjlXjUzgLUop6IIid K9O2WOfSaH2BWMWXVrl4oLKypZ8/ZvN3zsuxqJoUSf/SQ+qmdajcdOyApNftno0bk6t0xjcGPUm AhEf1gJi2lW6uKqG5HQM6TEi36FGQE4Nv/CLaOlzuTtyNuUjQB0iC4nvrdwRWB4gXicp0mAv/rF zUSynXVo2QRbwLPw== X-Received: by 2002:a05:6870:1696:b0:404:3b73:6804 with SMTP id 586e51a60fabf-408ab84bf07mr1931873fac.58.1769200721878; Fri, 23 Jan 2026 12:38:41 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:40 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:25 -0600 Subject: [PATCH v6 2/9] spi: dt-bindings: add spi-{tx,rx}-lane-map properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-2-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2489; i=dlechner@baylibre.com; h=from:subject:message-id; bh=5HI91WzF40M7BWTtVwSgdEEKhH3jYAKO9/9e2UnBD7E=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9wWLBe1jCZp5s6jymQtTxnQkTipbYZUFXXQb FYZedi+GIWJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcFgAKCRDCzCAB/wGP wBIWCACaHP7H34XUcv7GCi6yQp5HtmIVaHZLDrDsTmvIqFyB0ooSJnmPXvQMWDLKnsaSmkAZgH2 4rNPgNqwf/qLj5KxOmCdmjNesLmhLUIGgaziEEQrI3HY6QF8ullBeLOAgmOMTCzUh2Avn6sxLKF VTEMluS4IRqhDJMrot96t5roQiJNj4P7E9HI+u2nyEzyLhUmyUTEyAdschkH1RzwtXcWxKFkt9q vSxDIcaCY4r6vaI4qX/D6CdbGCXldflboXnz67/YKuBxeA5KfFrLOpbRpwuxpjWZsDAt7BuoQGt KVh5zF1+rMtcgT0IzyeJL+9py6glAMB7nCEouFJYD8olaIFi X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add spi-tx-lane-map and spi-rx-lane-map properties to the SPI peripheral device tree binding. These properties allow specifying the mapping of peripheral data lanes to controller data lanes. This is needed e.g. when some lanes are skipped on the controller side so that the controller can correctly route data to/from the peripheral. Reviewed-by: Rob Herring (Arm) Reviewed-by: Jonathan Cameron Signed-off-by: David Lechner --- v6 changes: none v5 changes: - Use SDI/SDO terminology in descriptions. (Fixes incorrect use of TX/RX when describing the peripheral lanes.) v4 changes: - This replaces the data-lanes property from the previous revision. Now there are separate properties for tx and rx lane maps. And instead of being the primary property for determining the number of lanes, this is only needed in special cases where the mapping is non-trivial. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 59ddead7da14..880a9f624566 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -75,6 +75,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-rx-lane-map: + description: Mapping of peripheral SDO lanes to controller SDI lanes. + Each index in the array represents a peripheral SDO lane, and the va= lue + at that index represents the corresponding controller SDI lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-rx-delay-us: description: Delay, in microseconds, after a read transfer. @@ -99,6 +106,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-tx-lane-map: + description: Mapping of peripheral SDI lanes to controller SDO lanes. + Each index in the array represents a peripheral SDI lane, and the va= lue + at that index represents the corresponding controller SDO lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-tx-delay-us: description: Delay, in microseconds, after a write transfer. --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oa1-f52.google.com (mail-oa1-f52.google.com [209.85.160.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 450E02EC569 for ; Fri, 23 Jan 2026 20:38:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200732; cv=none; b=VLUvATbCZvNejS+HoxMQV5Rddo494xIzSBmQx5/TFvsSy4n/Wj5+VJhlPnp/8Dvaof/4ji7mP6mYomNDIqdsp6axbN6uI7cxunqIQE3oj4vl5/492r/OK3XdjRnzKLoJdUub+XW9aMBhzWcsj4BzuYzb8HOLFPCUI4DG76glEzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200732; c=relaxed/simple; bh=LhhC/BLfQqXEBBBTB1yvmvgOHIE7YTE8dHc8kwu+3IM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VgGNjmka4TRArzKikN5EIDlnhLem3XSivfOYd4ZINulSGpyoETB80yB9AsKfwY6M1Z5lLXNOmSGgqj/s0RpaHeGBcyIig7RYBzIqmuHJhqTVj6Iza2eWQQXNU76LZX1ozIlXRtOWTwff6c3p8PBDRWhAZHCGYenmbC/mOJvZbDk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=LCsBmRcp; arc=none smtp.client-ip=209.85.160.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="LCsBmRcp" Received: by mail-oa1-f52.google.com with SMTP id 586e51a60fabf-404308dd5d6so919862fac.1 for ; Fri, 23 Jan 2026 12:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200726; x=1769805526; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7gap8Ic9mJCJ2EUZ4fRDAE5T4Vxf5aGNigPWsuyzfbU=; b=LCsBmRcpUII5JGSNiqsXYUpTfF8wrYhUsZLKiwrqZj6AVyOaa/E+HVi6x66ilvNGQA Xov/PthRvFi53aNz/zRNh4S2crF8a+R6gLOPvnrdLYDU3e/q58CBW0OC1ghFHfULpQEk 0vSjdypRtEuHtYsBzZ7F2R+3zNu3xZQ9k04/Xd3uAqVfClLBAhOREtvmSA+tH4jZAhFp gVn8MekVQxVQy8RxNirDc67SGLHtVoGq1OVJrRGMlIkZkvc0217vG7PLaVJ21FZK4d4E rvQhAUhXev3RsNgDs/Pb2E+FL2iQuvyepMJ57f5U5ybpVgapjHL/iytjm7yJ4pwGiawk fzqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200726; x=1769805526; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7gap8Ic9mJCJ2EUZ4fRDAE5T4Vxf5aGNigPWsuyzfbU=; b=Dw9QtgYjeHIQ7EBrTge3Md/a9yo2kHOKjctn6bCAnlYY6q2Nwp0Wg3jCsZZVG6y+DW ukZhI03HUTfJZg/EoI5d8oAPm8aFZfvn2h0L8AIie7KGlWyuwBLJs1olmY0Rv1JZkhRw SIc/K62oSdg7RBmiaN9nGDYjrO8RYD8GLDMgSD5gW78uhLaRhjvz+g2eE6GvVNPxbzZ2 6HTgQxXDHXOYurvP9/479kg7+VJRG9G+sGjk6uKCJ4yuFns0WuefOdqFsx4lxJKDBOGS 55aIDs0KUTVE4e0m9h17XOTedlnjhZdL7/CVqRjBkMkZDRe0uhebQp7jOew2ZUWAa8ff h02w== X-Forwarded-Encrypted: i=1; AJvYcCUyi4Z16tWEj2Une/rEp5VPs7M2nd/dA2V4lNQKAOr6NGcSHLX3BuPUCxDw+9Xr9s+PaTl4EOscyIPa2Ik=@vger.kernel.org X-Gm-Message-State: AOJu0YzHU29jv4EACURYBp8027RalYhFgbikwskI/1FX7UkVxJ2kFtlU Qtt8qouVhINcS1RDQJR7nQBCuuEAdrRj6Ht0nJUslqNEwjYStpKtz5Img/265HCyU+E= X-Gm-Gg: AZuq6aJfHCk98vE9NdluLzFOwo8T2rnPUgiV6gjj2Rf5t/Ox+jt6w7cy0d2YRzn+phz mba9g6/mWGfdZRvrBmjRcAdddRLwy3/m+H07ETOqdvJASyCCBRxS5hqKpsdsWhkH3a+Gb6leLOA pTpiqIZau07udpY/ALX54u+HiWvadNKKdR3Enl+wOxLTWyhx748TYiydOI9+xyS3UC5ubhkRnxi 9/kFGBA41DAl9/XoISq9dtKcMR5/UN/R68iybU++ETUurVL4nzxfNJphT5R6Am6vXuwwsU7+8tM DeRAzmsswoiheivASqLmxa1NXJQIybhlOtat4JvAA4+qsr+m0WB0Bv6PdlAp7dfhpFna/H0ECsu IeAGystzGRp7nIZNIJfQ2rmzz7rxTmV/1iFUqy6/jn20e6J9HBI5zY2zl9Bui/Ij/yyXVIUnuPw piKic1GplmEaVrjg== X-Received: by 2002:a05:6871:5225:b0:404:3805:1dde with SMTP id 586e51a60fabf-408ab3b3b5cmr2292518fac.8.1769200724771; Fri, 23 Jan 2026 12:38:44 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:43 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:26 -0600 Subject: [PATCH v6 3/9] spi: support controllers with multiple data lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-3-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=10712; i=dlechner@baylibre.com; h=from:subject:message-id; bh=LhhC/BLfQqXEBBBTB1yvmvgOHIE7YTE8dHc8kwu+3IM=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9wd27hUzKHTrSuRuTHG4+NYWPJ2gy3erffLx 6p9md6dnECJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcHQAKCRDCzCAB/wGP wAodB/0b1Wp207Kf5a/+HihKEQXAvlHY+3opEv0f98N9Cs5JK6gOU0k3pK7YveR2vr9TDMXVpK/ JhQmiwYWIp0NfNFIIQpHexCRN/4lOQqDtfATkLKsJteZN5K8vdNWcmVvAqJ4dSL4BYKyzp/xwAC 9oQ0bNAcFiHoMhauMO73Lx0R9nUh7VfDTdYBf7jS67BRiH4YwnI1xFKfiNr1r+bO7vPDCAmuFig YUko+zSdzBJt8RP3B1HyDvNTnzMjbm6RUI3P98XvvgfcYP5DrZDLL8/ybQzCUI8you/kylMPhHU xpm0Y51DbWemtuTKfQQoWgJTUB0ZPwW3Px1U9KcVzQJBljy1 X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for SPI controllers with multiple physical SPI data lanes. (A data lane in this context means lines connected to a serializer, so a controller with two data lanes would have two serializers in a single controller). This is common in the type of controller that can be used with parallel flash memories, but can be used for general purpose SPI as well. To indicate support, a controller just needs to set ctlr->num_data_lanes to something greater than 1. Peripherals indicate which lane they are connected to via device tree (ACPI support can be added if needed). The spi-{tx,rx}-bus-width DT properties can now be arrays. The length of the array indicates the number of data lanes, and each element indicates the bus width of that lane. For now, we restrict all lanes to have the same bus width to keep things simple. Support for an optional controller lane mapping property is also implemented. Signed-off-by: David Lechner --- v6 changes: - Use u8 instead of u32 for new fields in in struct spi_device to save memory. - Add additional checking to ensure that the data lane map has at least as many entries as there are data lanes. - Don't ignore error return from of_property_read_u32_index() (even though it shouldn't be technically possible to happen - that is why it just returns and doesn't have dev_err()). v5 changes: - Use of_property_read_variable_u32_array() for lane maps. v4 changes: - Update for changes in devicetree bindings. - Don't put new fields in the middle of CS fields. - Dropped acks since this was a significant rework. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. This patch has been seen in a different series [1] by Sean before: [1]: https://lore.kernel.org/linux-spi/20250616220054.3968946-4-sean.anders= on@linux.dev/ Changes: * Use u8 array instead of bitfield so that the order of the mapping is preserved. (Now looks very much like chip select mapping.) * Added doc strings for added fields. * Tweaked the comments. --- drivers/spi/spi.c | 144 ++++++++++++++++++++++++++++++++++++++++++++= ++-- include/linux/spi/spi.h | 22 ++++++++ 2 files changed, 162 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 170b0f3a2156..3887fcf8ec86 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2354,8 +2354,8 @@ static void of_spi_parse_dt_cs_delay(struct device_no= de *nc, static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device = *spi, struct device_node *nc) { - u32 value, cs[SPI_DEVICE_CS_CNT_MAX]; - int rc, idx; + u32 value, cs[SPI_DEVICE_CS_CNT_MAX], map[SPI_DEVICE_DATA_LANE_CNT_MAX]; + int rc, idx, max_num_data_lanes; =20 /* Mode (clock phase/polarity/etc.) */ if (of_property_read_bool(nc, "spi-cpha")) @@ -2370,7 +2370,65 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, spi->mode |=3D SPI_CS_HIGH; =20 /* Device DUAL/QUAD mode */ - if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) { + + rc =3D of_property_read_variable_u32_array(nc, "spi-tx-lane-map", map, 1, + ARRAY_SIZE(map)); + if (rc >=3D 0) { + max_num_data_lanes =3D rc; + for (idx =3D 0; idx < max_num_data_lanes; idx++) + spi->tx_lane_map[idx] =3D map[idx]; + } else if (rc =3D=3D -EINVAL) { + /* Default lane map is identity mapping. */ + max_num_data_lanes =3D ARRAY_SIZE(spi->tx_lane_map); + for (idx =3D 0; idx < max_num_data_lanes; idx++) + spi->tx_lane_map[idx] =3D idx; + } else { + dev_err(&ctlr->dev, + "failed to read spi-tx-lane-map property: %d\n", rc); + return rc; + } + + rc =3D of_property_count_u32_elems(nc, "spi-tx-bus-width"); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, + "failed to read spi-tx-bus-width property: %d\n", rc); + return rc; + } + if (rc > max_num_data_lanes) { + dev_err(&ctlr->dev, + "spi-tx-bus-width has more elements (%d) than spi-tx-lane-map (%d)\n", + rc, max_num_data_lanes); + return -EINVAL; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is not present. */ + spi->num_tx_lanes =3D 1; + } else { + u32 first_value; + + spi->num_tx_lanes =3D rc; + + for (idx =3D 0; idx < spi->num_tx_lanes; idx++) { + rc =3D of_property_read_u32_index(nc, "spi-tx-bus-width", + idx, &value); + if (rc) + return rc; + + /* + * For now, we only support all lanes having the same + * width so we can keep using the existing mode flags. + */ + if (!idx) + first_value =3D value; + else if (first_value !=3D value) { + dev_err(&ctlr->dev, + "spi-tx-bus-width has inconsistent values: first %d vs later %d\n", + first_value, value); + return -EINVAL; + } + } + switch (value) { case 0: spi->mode |=3D SPI_NO_TX; @@ -2394,7 +2452,74 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, } } =20 - if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) { + for (idx =3D 0; idx < spi->num_tx_lanes; idx++) { + if (spi->tx_lane_map[idx] >=3D spi->controller->num_data_lanes) { + dev_err(&ctlr->dev, + "spi-tx-lane-map has invalid value %d (num_data_lanes=3D%d)\n", + spi->tx_lane_map[idx], + spi->controller->num_data_lanes); + return -EINVAL; + } + } + + rc =3D of_property_read_variable_u32_array(nc, "spi-rx-lane-map", map, 1, + ARRAY_SIZE(map)); + if (rc >=3D 0) { + max_num_data_lanes =3D rc; + for (idx =3D 0; idx < max_num_data_lanes; idx++) + spi->rx_lane_map[idx] =3D map[idx]; + } else if (rc =3D=3D -EINVAL) { + /* Default lane map is identity mapping. */ + max_num_data_lanes =3D ARRAY_SIZE(spi->rx_lane_map); + for (idx =3D 0; idx < max_num_data_lanes; idx++) + spi->rx_lane_map[idx] =3D idx; + } else { + dev_err(&ctlr->dev, + "failed to read spi-rx-lane-map property: %d\n", rc); + return rc; + } + + rc =3D of_property_count_u32_elems(nc, "spi-rx-bus-width"); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, + "failed to read spi-rx-bus-width property: %d\n", rc); + return rc; + } + if (rc > max_num_data_lanes) { + dev_err(&ctlr->dev, + "spi-rx-bus-width has more elements (%d) than spi-rx-lane-map (%d)\n", + rc, max_num_data_lanes); + return -EINVAL; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is not present. */ + spi->num_rx_lanes =3D 1; + } else { + u32 first_value; + + spi->num_rx_lanes =3D rc; + + for (idx =3D 0; idx < spi->num_rx_lanes; idx++) { + rc =3D of_property_read_u32_index(nc, "spi-rx-bus-width", + idx, &value); + if (rc) + return rc; + + /* + * For now, we only support all lanes having the same + * width so we can keep using the existing mode flags. + */ + if (!idx) + first_value =3D value; + else if (first_value !=3D value) { + dev_err(&ctlr->dev, + "spi-rx-bus-width has inconsistent values: first %d vs later %d\n", + first_value, value); + return -EINVAL; + } + } + switch (value) { case 0: spi->mode |=3D SPI_NO_RX; @@ -2418,6 +2543,16 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, } } =20 + for (idx =3D 0; idx < spi->num_rx_lanes; idx++) { + if (spi->rx_lane_map[idx] >=3D spi->controller->num_data_lanes) { + dev_err(&ctlr->dev, + "spi-rx-lane-map has invalid value %d (num_data_lanes=3D%d)\n", + spi->rx_lane_map[idx], + spi->controller->num_data_lanes); + return -EINVAL; + } + } + if (spi_controller_is_target(ctlr)) { if (!of_node_name_eq(nc, "slave")) { dev_err(&ctlr->dev, "%pOF is not called 'slave'\n", @@ -3066,6 +3201,7 @@ struct spi_controller *__spi_alloc_controller(struct = device *dev, mutex_init(&ctlr->add_lock); ctlr->bus_num =3D -1; ctlr->num_chipselect =3D 1; + ctlr->num_data_lanes =3D 1; ctlr->target =3D target; if (IS_ENABLED(CONFIG_SPI_SLAVE) && target) ctlr->dev.class =3D &spi_target_class; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 8bc616b00343..ec8a03ee0d4c 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -23,6 +23,9 @@ /* Max no. of CS supported per spi device */ #define SPI_DEVICE_CS_CNT_MAX 4 =20 +/* Max no. of data lanes supported per spi device */ +#define SPI_DEVICE_DATA_LANE_CNT_MAX 8 + struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -174,6 +177,10 @@ extern void spi_transfer_cs_change_delay_exec(struct s= pi_message *msg, * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect = array * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect li= nes * (optional, NULL when not using a GPIO line) + * @tx_lane_map: Map of peripheral lanes (index) to controller lanes (valu= e). + * @num_tx_lanes: Number of transmit lanes wired up. + * @rx_lane_map: Map of peripheral lanes (index) to controller lanes (valu= e). + * @num_rx_lanes: Number of receive lanes wired up. * * A @spi_device is used to interchange data between an SPI target device * (usually a discrete chip) and CPU memory. @@ -242,6 +249,12 @@ struct spi_device { =20 struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio de= sc */ =20 + /* Multi-lane SPI controller support. */ + u8 tx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; + u8 num_tx_lanes; + u8 rx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; + u8 num_rx_lanes; + /* * Likely need more hooks for more protocol options affecting how * the controller talks to each chip, like: @@ -401,6 +414,7 @@ extern struct spi_device *spi_new_ancillary_device(stru= ct spi_device *spi, u8 ch * SPI targets, and are numbered from zero to num_chipselects. * each target has a chipselect signal, but it's common that not * every chipselect is connected to a target. + * @num_data_lanes: Number of data lanes supported by this controller. Def= ault is 1. * @dma_alignment: SPI controller constraint on DMA buffers alignment. * @mode_bits: flags understood by this controller driver * @buswidth_override_bits: flags to override for this controller driver @@ -576,6 +590,14 @@ struct spi_controller { */ u16 num_chipselect; =20 + /* + * Some specialized SPI controllers can have more than one physical + * data lane interface per controller (each having it's own serializer). + * This specifies the number of data lanes in that case. Other + * controllers do not need to set this (defaults to 1). + */ + u16 num_data_lanes; + /* Some SPI controllers pose alignment requirements on DMAable * buffers; let protocol drivers know about these requirements. */ --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oa1-f51.google.com (mail-oa1-f51.google.com [209.85.160.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4999D2ED85F for ; Fri, 23 Jan 2026 20:38:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200731; cv=none; b=fBYtq2PznZkYquEOD9YV15C8VxDZZDSMEii5npjC1pMonMPjlBAHD1IPTG1u2SeIzU8/3Vb8fMOr+qnssyHvrvBkf30XQ9j3J8XV74bDv49eg4tgxWM2UsfWVz13aiAP6Q/Y2Sj6AceIgyBkIbMM3A7eull8wTQCNv1NCL+pkL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200731; c=relaxed/simple; bh=6K+Y2EpItjAFEVDHoZvaznPDbPUDrOkWEh/VhUaPTSM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZhvgnhdnSY4LUngQo0KUdVsx4oIzWyYp92OvjmCVRJGSUQu7P7h53H7cROOCDhqSVgin9BSfY+GNmC9PtdHl0bzR4pI7wnfd4d1CJdm0T2x/NUuH33WamMwUVbWjpxfztBwPeGTi4MlTwGBa7VwzjDMviyp2wY3ipbRvo3nt0oA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=aHuYTRoA; arc=none smtp.client-ip=209.85.160.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="aHuYTRoA" Received: by mail-oa1-f51.google.com with SMTP id 586e51a60fabf-40866616d47so2008600fac.2 for ; Fri, 23 Jan 2026 12:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200726; x=1769805526; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=w6oXy9SAavgg4QtAir0K2/dqpzLAUs+ACA4F9zQ5oKI=; b=aHuYTRoA/YoRQxZBudut92S/EjpBHG+zzZRndDuCaX+T8h/jK4Dolhntf0jaMqGQB7 WNNINYqsPLGKBD/+7TIwh2EdUDo1GdXA4c1cNx5s+6Awr3laRexp03vtOT+zn/DAM6xU 6U3aXYg8VoNLyO2gMbfawha4KAV60BQ9CRvvHSUJe+nCQk6VVBHnjTnqR5V4pThbzepX ZJi9V7vS70MA/oGORPVKp9tQ6b4AAUwZJP5d/+hkXOEI1sCyATaM2Nuet/fY7U3Po/tA GhnK9IAjzzBIkP5LX1vJQ6RqBIaOd7dmx+pFU+KfFQfxOppesVJl+g/FCaZ1yQ8jfcAo 7F7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200727; x=1769805527; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=w6oXy9SAavgg4QtAir0K2/dqpzLAUs+ACA4F9zQ5oKI=; b=hQcQX81PmpeROXB8GvaizwQ9Yrk6WjFV/sWFDgYfcg89K3dcgklpygNC/OkUALECh3 NIi14I4M8Bn5HkNt6ADfic0nhjhet7VOaI6LmQzf0Bpl/kj7azxz6JezysIXuUBlEmD9 9wJonrQd6AIgY3pdHUsBRq2aj6yMjgT11HsW0yS6oDGhRyPLlWPqw+prnTy8d0u1oIWo P+cnq7vx2E3SCbGyRChu6nnT+1bcPM0HQg7tvY9IDWXA6YN3RP1hBmWv/mmc0HLt9sal 2nZVwliRe830UipGt4ls8NUjJdMFqSHO1NyYHlIBbvBbnU4KYrki8Q6hs4lOUYEB8g5s sgtQ== X-Forwarded-Encrypted: i=1; AJvYcCU35Jal4sZCRCLQu8eQicm4HRXmAPsf5HFfwluqKfJlv8sf5GZkvVvnu4pTDaVJ2HcntXhQDkjUKgQhuls=@vger.kernel.org X-Gm-Message-State: AOJu0YxdSm240Cx2IlN5VyVkSNlH2+FDXEtW/37PjkgMcT5rMHQ8cB7C bYEFICWRq2c8i2456MTIRgbdG+mD/W5AIYzAkIz18pPUuaJ/wB6yVVlcdBhfZLt1PFE= X-Gm-Gg: AZuq6aJ1pvebcNLGymFIS/24AQ/ShReUPGjkHJa7JXGca+NvZxZkuLF1YgUzEs9qTVV JBgkzYVMnG1BwzqdeZHx7FkgXWLMjwms+uE1we2ROSFNoaaozRAXQSmFzheTaDCi4eQpagQp9DN XjnWKRpH80xUL2Vl2ueynr+4wGOEm8ljaQ6kMWeohpa7jl+vHk67qc3jBAWeMMzr9p1QzDtWkfC Bg7hurEcyvrQMtM+cdoujzrz1tq8sudnQSFqPSu9W8xyWL2o173Q5CyEX4U+Z/eoyd8HxH5CgOk Pgkc7byOrNUCx99v7ETPoxtFO61Rcb9t3aYYKo4Fjq/UPdR+Zb3W0JTwoizA7LTMI6IaMbf1Q2X nB98BiN036XJ+5LV921QeaifL7LmtGvLfm7ZIRclgXHfeIkIzKgXvW5JdVsLASwGmOsJbol94ew zLf62AMw4yHRwJhw== X-Received: by 2002:a05:6871:2e89:b0:404:43c1:28b5 with SMTP id 586e51a60fabf-408ab4e60f2mr2227571fac.14.1769200726621; Fri, 23 Jan 2026 12:38:46 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:46 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:27 -0600 Subject: [PATCH v6 4/9] spi: add multi_lane_mode field to struct spi_transfer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-4-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2129; i=dlechner@baylibre.com; h=from:subject:message-id; bh=6K+Y2EpItjAFEVDHoZvaznPDbPUDrOkWEh/VhUaPTSM=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9wjnXMHw1tRGqZ6YNmZ5UlrWYkzHUgSrhuv1 MEsWa4upC6JATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcIwAKCRDCzCAB/wGP wJnnCACUe2jk1jNjSGdqZBZ5TKEPO/eu3xkCUafz2SJHfCZ181UY0qHmVMtSnWIf+S3V+/f+bsJ Oj66B//o16b1cSeRpLS652IOro4mwCasABG8beWtnXI/1HrY5nBdzOTcRVdkMEuLfeOfXzLSJwD pn7iOLhz+saxfqw6GRfPfrZ7zNyFjahc+lQ8Zp+7oHG5dkEDUUXaI57zx5/iYuzYQjaEIo8IQD0 lUcVQGnPgkV3RuTKADBgWSZpp4Dv5Bewg8EBSIY/iwgTFBYVK9wz7ahq6dvAo5wMJKia1g1lGwR bKzuUnupvn21goJfbbBqv9+k4al0iIxyJak54Xr3Db74duIP X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add a new multi_lane_mode field to struct spi_transfer to allow peripherals that support multiple SPI lanes to be used with a single SPI controller. This requires both the peripheral and the controller to have multiple serializers connected to separate data lanes. It could also be used with a single controller and multiple peripherals that are functioning as a single logical device (similar to parallel memories). Acked-by: Nuno S=C3=A1 Acked-by: Marcelo Schmitt Reviewed-by: Jonathan Cameron Signed-off-by: David Lechner --- v6 changes: none v5 changes: none v4 changes: * Shortened commit message (useful info will be in docs instead). * Added whitespace to create clear grouping of macros and the field. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. --- include/linux/spi/spi.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index ec8a03ee0d4c..fd8dce4169f7 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -990,6 +990,8 @@ struct spi_res { * (SPI_NBITS_SINGLE) is used. * @rx_nbits: number of bits used for reading. If 0 the default * (SPI_NBITS_SINGLE) is used. + * @multi_lane_mode: How to serialize data on multiple lanes. One of the + * SPI_MULTI_LANE_MODE_* values. * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. If 0 the default (from @spi_device) is used. @@ -1126,6 +1128,12 @@ struct spi_transfer { unsigned cs_change:1; unsigned tx_nbits:4; unsigned rx_nbits:4; + +#define SPI_MULTI_LANE_MODE_SINGLE 0 /* only use single lane */ +#define SPI_MULTI_LANE_MODE_STRIPE 1 /* one data word per lane */ +#define SPI_MULTI_LANE_MODE_MIRROR 2 /* same word sent on all lanes */ + unsigned multi_lane_mode: 2; + unsigned timestamped:1; bool dtr_mode; #define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */ --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oa1-f68.google.com (mail-oa1-f68.google.com [209.85.160.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FB012EF64C for ; Fri, 23 Jan 2026 20:38:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.68 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200733; cv=none; b=YWj/p0j/uOvLuw9MzsliVzCFOemSiMxVeBl61H+ZrlXN6/C6SX8BMuG7tZVsNSpckx3v24eKeMZBiXULnDaHHugA03+MuqVkJmcICYzJohbmWb5ZD0OHyHB3ZMqbGVPf0zNjZe++1VLrPdJd2TbyuVtkbPDUahFY+p1zDzBGG48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200733; c=relaxed/simple; bh=O20ziRwhKmAnSP9ctsHkGnisWSjXJS1ux9ZdETkvqns=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XwZ2Dke6e25YPHvnPNTsi1tztjYMT3+zB2NLxGnuUaWF0otSvF3ITCEvMarjfOYltWfZH/zTVGFg9OU77ExG242ADvDQNRMOOw6q4UhXAFB5iX8/Y7+zHhZ+0L+TmKhDYGieZUfbQY3gEf+exGFRgAnFquyPRqG+IqIddfkluFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=mfRb2TZM; arc=none smtp.client-ip=209.85.160.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="mfRb2TZM" Received: by mail-oa1-f68.google.com with SMTP id 586e51a60fabf-4044d3ff57bso805041fac.0 for ; Fri, 23 Jan 2026 12:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200728; x=1769805528; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dmX79GnzdywzPzH2+K8k/JNfqckElyoOXGWVtE/G7r0=; b=mfRb2TZMcu/lPqzyzfsw5M4yKbBcKWt5gSmVomJoiF7GuGC5xcx5hS4jDdnfj7tytY ihNc22/DHk8G+HfNoj3/UEzlHvZIhUT4qUt2/Dh/1qVhV3q42AveWkgDJeWFerDHmRDA evsS3d0BcZ8LUC3c6qwv1z3fvnzynw45u7hUHIkUwOzkTNBgXUOxvmlZOZqP5TZjgna4 2rLGRHDiqfEFLx84ydMtLk0zczJwYxLhwF6QJS7zZusVkdSSrDMdl2aSIYLj5n+uui4L a6POlTONvKAMdEPqYCqiJPw7lyQSZ14nAvj5H4oObZajjvT/PQ2VbWc9OJwY8lly80nv UFhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200728; x=1769805528; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dmX79GnzdywzPzH2+K8k/JNfqckElyoOXGWVtE/G7r0=; b=dtu/xHUdgP/OFN3ZnitZC/wU1YxS+0F5qadb1N7B56/aV/2v6Q7uqPSww7Om8mVwK1 GtXe7KmO2s7uQ9GJtA4q8KEQYOoSmObo+bYhdKax+Qk8TgCBBuHQ7D3tjN+DCiTTars2 IApbeg+rgUtnoF4Qe7qYvTQ3e2E2d8FPPWNJdfItf5WhBoyge/QtfMN1B56J3p6lqB5p sB8GoruVoycTGXu0YAC4KSGkoqQy2jLKfq0FZfqV0v75nM0BCZ1vqgAymD4zsiTkWOb6 OpJrsculRbbMeBrnFJW+yLat0AWkVytQbODyI3nODCszpbf8A6kJT+vEVDa/0sJ1nwEX 1LHQ== X-Forwarded-Encrypted: i=1; AJvYcCX6eGfJaYtBQyKQf5WQPkizlJjpa5pj3B3dCFuPtmRXhVNGqVikY/VmWcH8eKZCeQMOuXYndsqKguPHIcY=@vger.kernel.org X-Gm-Message-State: AOJu0YxmEpg/FFjKiCzHyPaFkt6ntNAyYanhLXeEUe33IIhmxujSsX/S gqi/q0jwcjDOkNPoeS38jzztkBqVrLdIYMb9mHs9nrJ7viSk7OIx1XYR1oQmqv8VhFquzobcSS7 GOgxkjVY= X-Gm-Gg: AZuq6aKmcUO/Zc0QgxYq/Z5sCxewZRsC9YRnsjk0ThiDv5RVD9jOCgvefz2DEdGVszh 5us9qO/8BQCPsQTtrYbuxlQpZbdR9ZDeS6SvekNP/H7U6RX3piE+CMuuelLFP2ZWgLOYwHZT/fn QmTWoc56PgrkCNzBEgW46MOqVkjMnoVjJc7MGFlp27nQs7tmqXcioJeYtn6uld1zAMTzza2axTf iAnAKN68W0YffCvW16h3bB2M523X07t71HiwkNV1vd3B45Pbl60ktVXdoPWVGugzOnSVP3Cojt7 6QtNs+LdRrc8xy/o+4VP3G+/EEwJRedsTY5faMX23/Df8pafg2hKyjS7wT4SY56S1YUDHW3oAHi YBQT8vxk3s/pw5gKKRoLOs6yhD8SLo2q8qqgO659iYGT0huM+OkRz5yPPh2vh4bQzBmWN0i9R9y i6B89v2TLjimGdPsSRz1Y8t7MU X-Received: by 2002:a05:6870:ac22:b0:3e8:3176:a342 with SMTP id 586e51a60fabf-408ab4fffdemr2009501fac.22.1769200727566; Fri, 23 Jan 2026 12:38:47 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:47 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:28 -0600 Subject: [PATCH v6 5/9] spi: Documentation: add page on multi-lane support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-5-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8955; i=dlechner@baylibre.com; h=from:subject:message-id; bh=O20ziRwhKmAnSP9ctsHkGnisWSjXJS1ux9ZdETkvqns=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9wqO06xg6Gv9V7NIzeqeI+yHWovm7g6//+Km /CjYq8yIb6JATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcKgAKCRDCzCAB/wGP wEX0CACDUlrSXSQQrT8YI6wCrnl/g5281Wzf1uIzVnQiRSpt+2z8h06M/wqpOLVoTMwJCv+Xdo4 Ys9+rw9ELNHoUcTOwWXZT26XZIWOW81wqYAj4DQrJEauin+WvKIaAb0G32MF62OCeHBLPwHDUl7 09luXjPNI2st81Cmxhw2TvHum9LXqcsgJfPsR82+xsI6IFqA/wJCiq8e4eoIdY6q7RRoehSvuMS 5nm3Au3tOA5ODP07aPczyqTd5qNzKvTTlU8u+zYKDW32s1WLqeJm4YAerFrQfd2lEJl1lgOrtZP x303RGtPHWV3XWqETvfGseVAJm9MBxHrCKxzs34w+TJDl7IE X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add a new page to Documentation/spi/ describing how multi-lane SPI support works. This is uncommon functionality so it deserves its own documentation page. Reviewed-by: Marcelo Schmitt Signed-off-by: David Lechner --- v6 changes: * Fix copy/paste typo of wrong property names. v5 changes: * Fix tx/rx typo in stripe mode example. v4 changes: * New patch in v4. --- Documentation/spi/index.rst | 1 + Documentation/spi/multiple-data-lanes.rst | 217 ++++++++++++++++++++++++++= ++++ 2 files changed, 218 insertions(+) diff --git a/Documentation/spi/index.rst b/Documentation/spi/index.rst index 824ce42ed4f0..2c89b1ee39e2 100644 --- a/Documentation/spi/index.rst +++ b/Documentation/spi/index.rst @@ -9,6 +9,7 @@ Serial Peripheral Interface (SPI) =20 spi-summary spidev + multiple-data-lanes butterfly spi-lm70llp spi-sc18is602 diff --git a/Documentation/spi/multiple-data-lanes.rst b/Documentation/spi/= multiple-data-lanes.rst new file mode 100644 index 000000000000..69cb532d052f --- /dev/null +++ b/Documentation/spi/multiple-data-lanes.rst @@ -0,0 +1,217 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SPI devices with multiple data lanes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Some specialized SPI controllers and peripherals support multiple data lan= es +that allow reading more than one word at a time in parallel. This is diffe= rent +from dual/quad/octal SPI where multiple bits of a single word are transfer= red +simultaneously. + +For example, controllers that support parallel flash memories have this fe= ature +as do some simultaneous-sampling ADCs where each channel has its own data = lane. + +--------------------- +Describing the wiring +--------------------- + +The ``spi-tx-bus-width`` and ``spi-rx-bus-width`` properties in the device= tree +are used to describe how many data lanes are connected between the control= ler +and how wide each lane is. The number of items in the array indicates how = many +lanes there are, and the value of each item indicates how many bits wide t= hat +lane is. + +For example, a dual-simultaneous-sampling ADC with two 4-bit lanes might be +wired up like this:: + + +--------------+ +----------+ + | SPI | | AD4630 | + | Controller | | ADC | + | | | | + | CS0 |--->| CS | + | SCK |--->| SCK | + | SDO |--->| SDI | + | | | | + | SDIA0 |<---| SDOA0 | + | SDIA1 |<---| SDOA1 | + | SDIA2 |<---| SDOA2 | + | SDIA3 |<---| SDOA3 | + | | | | + | SDIB0 |<---| SDOB0 | + | SDIB1 |<---| SDOB1 | + | SDIB2 |<---| SDOB2 | + | SDIB3 |<---| SDOB3 | + | | | | + +--------------+ +----------+ + +It is described in a devicetree like this:: + + spi { + compatible =3D "my,spi-controller"; + + ... + + adc@0 { + compatible =3D "adi,ad4630"; + reg =3D <0>; + ... + spi-rx-bus-width =3D <4>, <4>; /* 2 lanes of 4 bits each */ + ... + }; + }; + +In most cases, lanes will be wired up symmetrically (A to A, B to B, etc).= If +this isn't the case, extra ``spi-rx-lane-map`` and ``spi-tx-lane-map`` +properties are needed to provide a mapping between controller lanes and the +physical lane wires. + +Here is an example where a multi-lane SPI controller has each lane wired to +separate single-lane peripherals:: + + +--------------+ +----------+ + | SPI | | Thing 1 | + | Controller | | | + | | | | + | CS0 |--->| CS | + | SDO0 |--->| SDI | + | SDI0 |<---| SDO | + | SCLK0 |--->| SCLK | + | | | | + | | +----------+ + | | + | | +----------+ + | | | Thing 2 | + | | | | + | CS1 |--->| CS | + | SDO1 |--->| SDI | + | SDI1 |<---| SDO | + | SCLK1 |--->| SCLK | + | | | | + +--------------+ +----------+ + +This is described in a devicetree like this:: + + spi { + compatible =3D "my,spi-controller"; + + ... + + thing1@0 { + compatible =3D "my,thing1"; + reg =3D <0>; + ... + }; + + thing2@1 { + compatible =3D "my,thing2"; + reg =3D <1>; + ... + spi-tx-lane-map =3D <1>; /* lane 0 is not used, lane 1 is used= for tx wire */ + spi-rx-lane-map =3D <1>; /* lane 0 is not used, lane 1 is used= for rx wire */ + ... + }; + }; + + +The default values of ``spi-rx-bus-width`` and ``spi-tx-bus-width`` are ``= <1>``, +so these properties can still be omitted even when ``spi-rx-lane-map`` and +``spi-tx-lane-map`` are used. + +---------------------------- +Usage in a peripheral driver +---------------------------- + +These types of SPI controllers generally do not support arbitrary use of t= he +multiple lanes. Instead, they operate in one of a few defined modes. Perip= heral +drivers should set the :c:type:`struct spi_transfer.multi_lane_mode ` +field to indicate which mode they want to use for a given transfer. + +The possible values for this field have the following semantics: + +- :c:macro:`SPI_MULTI_BUS_MODE_SINGLE`: Only use the first lane. Other lan= es are + ignored. This means that it is operating just like a conventional SPI + peripheral. This is the default, so it does not need to be explicitly = set. + + Example:: + + tx_buf[0] =3D 0x88; + + struct spi_transfer xfer =3D { + .tx_buf =3D tx_buf, + .len =3D 1, + }; + + spi_sync_transfer(spi, &xfer, 1); + + Assuming the controller is sending the MSB first, the sequence of bits + sent over the tx wire would be (right-most bit is sent first):: + + controller > data bits > peripheral + ---------- ---------------- ---------- + SDO 0 0-0-0-1-0-0-0-1 SDI 0 + +- :c:macro:`SPI_MULTI_BUS_MODE_MIRROR`: Send a single data word over all o= f the + lanes at the same time. This only makes sense for writes and not + for reads. + + Example:: + + tx_buf[0] =3D 0x88; + + struct spi_transfer xfer =3D { + .tx_buf =3D tx_buf, + .len =3D 1, + .multi_lane_mode =3D SPI_MULTI_BUS_MODE_MIRROR, + }; + + spi_sync_transfer(spi, &xfer, 1); + + The data is mirrored on each tx wire:: + + controller > data bits > peripheral + ---------- ---------------- ---------- + SDO 0 0-0-0-1-0-0-0-1 SDI 0 + SDO 1 0-0-0-1-0-0-0-1 SDI 1 + +- :c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data= words + at the same time, one on each lane. This means that the buffer needs t= o be + sized to hold data for all lanes. Data is interleaved in the buffer, w= ith + the first word corresponding to lane 0, the second to lane 1, and so o= n. + Once the last lane is used, the next word in the buffer corresponds to= lane + 0 again. Accordingly, the buffer size must be a multiple of the number= of + lanes. This mode works for both reads and writes. + + Example:: + + struct spi_transfer xfer =3D { + .rx_buf =3D rx_buf, + .len =3D 2, + .multi_lane_mode =3D SPI_MULTI_BUS_MODE_STRIPE, + }; + + spi_sync_transfer(spi, &xfer, 1); + + Each rx wire has a different data word sent simultaneously:: + + controller < data bits < peripheral + ---------- ---------------- ---------- + SDI 0 0-0-0-1-0-0-0-1 SDO 0 + SDI 1 1-0-0-0-1-0-0-0 SDO 1 + + After the transfer, ``rx_buf[0] =3D=3D 0x11`` (word from SDO 0) and + ``rx_buf[1] =3D=3D 0x88`` (word from SDO 1). + + +----------------------------- +SPI controller driver support +----------------------------- + +To support multiple data lanes, SPI controller drivers need to set +:c:type:`struct spi_controller.num_data_lanes ` to a value +greater than 1. + +Then the part of the driver that handles SPI transfers needs to check the +:c:type:`struct spi_transfer.multi_lane_mode ` field and imp= lement +the appropriate behavior for each supported mode and return an error for +unsupported modes. + +The core SPI code should handle the rest. --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oa1-f43.google.com (mail-oa1-f43.google.com [209.85.160.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CD182EBB8C for ; Fri, 23 Jan 2026 20:38:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200734; cv=none; b=iEG6vX8RjqIyIBxXiJLwDCo+cP3SwLTjZW0/zQsxQrWT7I7bBmgIOF0qM0uPAvSRRsvmv05RR7lYrwIoo92IA0hS2pyj29PyuAZEGHTH9igZjG9AmUdocNlYV7z9EHYyMJRaCQy7O87mcFjyXOjBi2JsOOfMWJzHO7UpNI+Ge3A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200734; c=relaxed/simple; bh=xGdA4shyG2YCvuBGh2md3PDf5DNCGZXwZPSKvqxMkg8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J3fEI9Lk4xQyzWGgZXjC4gbrGlD6eEuoPou66MWetYafAtmKnU6mdcJ+8bRKSBlxQCsyHH3rMAf1uhZTM8L/BPgloAbabvY2r/Kj38nmuuf/JsW957FlKAb40EVYblRPoHQjA3ivyk7zIq9lFKlrQ+1SDwpja25WgDRApyUpckk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Re5pUkn2; arc=none smtp.client-ip=209.85.160.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Re5pUkn2" Received: by mail-oa1-f43.google.com with SMTP id 586e51a60fabf-3f9ebb269c3so1208224fac.3 for ; Fri, 23 Jan 2026 12:38:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200728; x=1769805528; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4D5V2WHoyTIzltxmYXn2Y2Bh1DMbRJSg1M2EQIKXDAk=; b=Re5pUkn2qs5xraFNfWCHwGERp2ObHMdwej+DhjY5fO5QYiO28jZw6qIfA11clvvdOP CWKcAzxeKxJILzkSgw6nbPFNG5trUf16vMhBgk0w4MNEYQ9AGJPbjQuRfQlF7gMutJp6 OvaF7mHq3ppovSX62doZ7lN+BymX1vxYj1+LYzbq3cAJdK9Tw2G1Qjcsd9Z4tfSXI98L pvUFMBo9e26Kwt6RjLARQz5pQVCpJcB3N3H01bKQ9qp1AfYTNO9APhJZ89nx0KBq1XK2 gTXEJXVfjT6yqruCAvX3oOfyq2WDL7Xk4+fwqvsdrzck9E6UrEAGK+gowzzz3Smur0uH 8u5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200728; x=1769805528; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4D5V2WHoyTIzltxmYXn2Y2Bh1DMbRJSg1M2EQIKXDAk=; b=QHPYDZEh/0X/7rVFCMq+LSzQjeMsNWEJjT29t2i1fu1N+1tv5gxTuouRTR8vnFVwzd D1dPI+smmytuGgqa5nS44sjMU4EGipk1N7+5VE0urCUKNq0BxzTYldYD38Vg9TOn1Zev oe6anB05JF5+TqDrHDD+fIfYHdCmv0TuoT0G7nwSG6ZmKnHvgofaFUwql1arBwjrlZg8 a3mWSO5SxldhWK1jZ2KnjRSPpZysyjHhmWVr65kLN4rlOcYg3RYcBo/VZgaVr+9JcqHf ZJYts2K78Nzcznbre16eGOZm3IreTZUe8iMuEkrqEuaqP0O2t0KU0wVRVphx80bO222I OUlg== X-Forwarded-Encrypted: i=1; AJvYcCVOm9EJFEV1EzaEtpLsih5jjN+BBO+mTxPA+qHyE1xcDT4dbXp8P0l0XYTV60U8qDvPAA9mGj22vVpkkCc=@vger.kernel.org X-Gm-Message-State: AOJu0YxZsJcDgCnFLrzA3PMpY9Qi8g8dwi1oJ85WF7b2dU4nmH6+15mW MWDlMEiLlEmToHxaXD/KS9TY843Y4RlwC81cYXvjrXTTjllX6HDzENLITblAtMMUzmA= X-Gm-Gg: AZuq6aIRf9FLizoJOyS9lmMair8M8D3h5HzjLekQK2SMnxW6eIkHWAXs2L9zVPn4Fqd SJfqxyUfGOgKR9FCyIUDTX34XKXK85Irst6bCZ5HrQ6SNFKx+iEuNmqdDs6RiiZSRbArWqzTGQM 0Gmwz7iWLu+NMh6Qii/UhSyFsRzbDroFW4h5zhCO+984vrVoDL5dr5GgKKKEjORogGX6/Kc24jy beqyzL9dWtT3l3jqx0ZrPkZpMGmEA4HQ+yvhzR6oNk78LANXVN0xW6qTZ9UAcqNoEOQ8jWjBza0 8MI4utEjAmlq7h/y150YZE4C0fbPuSGuDh0OQyMIiuL/reQCfxMQ4QnsYSHGA3U35iHv3KqIRJ4 9yayJTOypqFv1+q1kwTbZ4yTl8z+E8w2TQGLvSKmsVPit5Dp6AtXxBgw+wzCknoHnhugLx8eQkP Xpxp3FhpvmlNcvpg== X-Received: by 2002:a05:6820:807:b0:662:c553:f773 with SMTP id 006d021491bc7-662cab0af25mr1991010eaf.25.1769200728584; Fri, 23 Jan 2026 12:38:48 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:48 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:29 -0600 Subject: [PATCH v6 6/9] spi: dt-bindings: adi,axi-spi-engine: add multi-lane support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-6-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1434; i=dlechner@baylibre.com; h=from:subject:message-id; bh=xGdA4shyG2YCvuBGh2md3PDf5DNCGZXwZPSKvqxMkg8=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9wwf/DD6p6dx3xldEec+/4EaAeYpbAs1/F3J ScoCZH53nmJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcMAAKCRDCzCAB/wGP wGrmB/9kc2C/18JRnJIfaukRhqgo7WOfAudo1S4mWl7ghysu38eESv1Ii+24C+i+pZDc5qvjOoe eI5v6HVsrrzLQQ5iAmky2qQZDSz8l7D2PiT+nD0rUiG/hN2XegaUWzToEo7AVFo6Oui6wRV30dS rDTdPbcYlpfCm6G2JYPHutG2zodpGo8OTbIXNh9yAoWIETW7RZv2baOeLrBS64VYV8rEWiVPS81 aKlw9wc51pdMtySPTHQo6ZLDz7n29UXWIRrwNq3SAmZQDGJL/XhBxc8gOT+foVkeCgnueLDDqCy DuiA+Sz80qHv2DFurAScljF2UGTjeFn2Cn0yg125/WMnvhP/ X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI controller has a capability to read multiple data words at the same time (e.g. for use with simultaneous sampling ADCs). The current FPGA implementation can support up to 8 data lanes at a time (depending on a compile-time configuration option). Reviewed-by: Rob Herring (Arm) Reviewed-by: Jonathan Cameron Signed-off-by: David Lechner --- v6 changes: none v5 changes: none v4 changes: - Update to use spi-{tx,rx}-bus-width properties. --- .../devicetree/bindings/spi/adi,axi-spi-engine.yaml | 15 +++++++++++= ++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml = b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index 4b3828eda6cb..0f2448371f17 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -70,6 +70,21 @@ required: =20 unevaluatedProperties: false =20 +patternProperties: + "^.*@[0-9a-f]+": + type: object + + properties: + spi-rx-bus-width: + maxItems: 8 + items: + enum: [0, 1] + + spi-tx-bus-width: + maxItems: 8 + items: + enum: [0, 1] + examples: - | spi@44a00000 { --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oa1-f48.google.com (mail-oa1-f48.google.com [209.85.160.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F5B62F0C63 for ; Fri, 23 Jan 2026 20:38:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200735; cv=none; b=BDVrAGDfIN2gbFT4ECJT8/RnqPi9uw2n1qPo8uttg9pt0sIuw1qzc5a1vOa2J2qcPtPmdwYQMqDTJbrBOXHMW/jEGau5BO1lqYEQfUnT6YbDaJxFr1yTKj7EcYiYmuixuQgjNPJFS4EWBlx1t/T+SR8B8qq0oWxGDNINJ6bm80s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200735; c=relaxed/simple; bh=KnZDb1RT6NWWOFZ3HvXqvyGhNXZq7ggnEolsCRzgZd8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ys2WAg0tZANzunKb1Fu4I8Unjp3EhdMQO0WLi5NMEOI0xMQGrgIKpFb7J15lz8/Mc3hN0ZIhiMRBGIouvk1YNCm0LEp9NIer7bk9H/tYtif31RhUoluKlh/z3zQqaPnCzrzcyEp+6MsG9/K3F1GlUqXsK4bvlrMvgbuTaerwkVA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=iAZsbydM; arc=none smtp.client-ip=209.85.160.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="iAZsbydM" Received: by mail-oa1-f48.google.com with SMTP id 586e51a60fabf-4045ccdd239so783508fac.2 for ; Fri, 23 Jan 2026 12:38:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200730; x=1769805530; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6K91l2e5Ibh1D1gRXzP9yxJZxobSqKsfm22dEUOsBxU=; b=iAZsbydMwqkfc6MVr7/C3ggh9V1GZ1FB/DdoGlhQe/A9+3Ejfz90RW2nM5llPUHtBR 6koFPXj5XghQRnzX8ufXGrD9zx5V/0P6eRwt+aR2eMoJpqsvPUsu4h+YZ668X8NLO7Ms cVAW5Vqd0p9Qh3pmgXF0fEoOWbars/cloJkWfx+o+lgDntUGQ4LytpuDgDyyvNxbqXIH JWOAqkZkq8xaXoTi5FQukAfi78MQ7S10LOntX0U7M7E4xbvagtk4SmWRnD7tvkjTbWW7 cDnQ330OMi8iwMhqmFXggch6I0ljCaMdCA1CpUs72O2ya42KtU8b93vcSJIxgI8UsOu8 878g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200730; x=1769805530; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=6K91l2e5Ibh1D1gRXzP9yxJZxobSqKsfm22dEUOsBxU=; b=NYeeC5t7s3hDPrxZq+vn9g0DZtjxXSy2yYwfx1zM29qX+QZXf9JXXNf56GI6iV0R8f yI7ojAjVAjYILCtQAfITgkKRKt/MzQJ1+VOAPTbrOypYuO6O8liUvKGhjMVtFCoPHn77 sUGeJJYZOdozbDFp2ZlmvQnzSfd0VV/MKXNraE6ZiRx1QrO+BDuuNIYe1a0i6Ij91Uhx flrG67e2Q1V5QMA42nPea1FKJ+5Y/TpcxKXEmnWzrwhYeCq0ZBFvMhsrlZbpq5jvZc0S 5opQZPT645IIswGdx+ApKKNid7i9kIEslyhQ/E+3wIdwRQCaWSPxacjfDj68ConWT793 7c2w== X-Forwarded-Encrypted: i=1; AJvYcCXuybn9zkenPdVDkLCII9rkgzbh2DMpIE6qwJt2wHKuR2cmSwslSPOXvijKp23m4OPGUa8yUdi7jFh15fw=@vger.kernel.org X-Gm-Message-State: AOJu0YyJgLP6kCiZH2tyZqbFSeRPCR3WbnnT1EP3ydjqtt7R6rRSuGSC W/tj52pFn9Z4miavRHxgMGiAorp04JWDJOG8XeI7bN7uNusIpVsar/BdyWetYObUNo0= X-Gm-Gg: AZuq6aLhLxCZ4fDcn4A+cXWSIHn2PeET9sFisDdldcKpvPGjoKABZD3ZH4OhVUxIR9o JXEa+OCJA73eGlDI0fRx422gEpk7eHvFY4clwfpbgLnJbXkX016a3u/IDiBxSUOb2gDLRfHluZu J7AMGQClYmMF8hQObUej7C3PEeSl98abzBJjXediB3Kh235x/xCczOcVAM/ro2lGEgSsqJqdTa7 o1qlaMP1DNmZrszq9GzLEsK9jX+qgwDW7cL3iK8cwhR+Cb0v149Obsg1R5I+AIrd71dvmhIQB5g q/Yierd9GFS4ZpmZId9+M+sTCc5y90a/OAlDtgFXrWmrNvfxrzfrFBPQj7lnuyC8bu8A9LfOOb5 3mPhQRYsMTwOzhHtRnGKnKYKpJoSqhkgHFwiL9UJ0iQ7bwsanW0O5CDxt7Qn0JsR1rXh2tub+iX rYMjsJSTYXr0HCniC0OVNf6zqa X-Received: by 2002:a05:6871:ca:b0:404:36c7:47a8 with SMTP id 586e51a60fabf-408ab884bc3mr1997005fac.59.1769200729510; Fri, 23 Jan 2026 12:38:49 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:49 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:30 -0600 Subject: [PATCH v6 7/9] spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-7-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=12230; i=dlechner@baylibre.com; h=from:subject:message-id; bh=KnZDb1RT6NWWOFZ3HvXqvyGhNXZq7ggnEolsCRzgZd8=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9w3w+rob1cYM3ya/aXzmF6/hqjR5jF5SAisO D0rFB65fUyJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcNwAKCRDCzCAB/wGP wCCfCACQKv+wxM+iVegq9HcWOCvP8OMxcbrXoW/iCNIV3yuDR5/51Xqgjq+Rmw+Em9v2Gc5lvCA R+rjeI+hqt3B3Pq3gi7Db8yLk3vCXofhxlMimAHciEWbmZbsj1Mf2YyBdx4bB3eFgYZQkTeNrdr KlQH2AV0UQynE/5uIHQ0N0pUJn9cpQxaoRhCD24fudUocq5Xd45RZ5t2rqbI8ndPvgyTtqFlEzn nMIE3QN7PdiuRH8h4Tj4/QHLTgaPe3vLuUuw59YIx7fnY/A2+DowUBJqRYlCsYvDfJ5umTDq24b MNXCY+06X1TMG4cBAx34it+NQyP5J0vGrNzzFRsuflhuz1lP X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for SPI_MULTI_LANE_MODE_STRIPE to the AXI SPI engine driver. The v2.0.0 version of the AXI SPI Engine IP core supports multiple lanes. This can be used with SPI_MULTI_LANE_MODE_STRIPE to support reading from simultaneous sampling ADCs that have a separate SDO line for each analog channel. This allows reading all channels at the same time to increase throughput. Reviewed-by: Marcelo Schmitt Reviewed-by: Jonathan Cameron Signed-off-by: David Lechner --- v6 changes: none v5 changes: none v4 changes: * Update for core SPI API changes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. v2 changes: * Fixed off-by-one in SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK --- drivers/spi/spi-axi-spi-engine.c | 145 +++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index 91805eae9263..c75e8da049f7 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -23,6 +23,9 @@ #include #include =20 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(23, 16) +#define SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0) #define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10 #define SPI_ENGINE_REG_RESET 0x40 =20 @@ -75,6 +78,8 @@ #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0 #define SPI_ENGINE_CMD_REG_CONFIG 0x1 #define SPI_ENGINE_CMD_REG_XFER_BITS 0x2 +#define SPI_ENGINE_CMD_REG_SDI_MASK 0x3 +#define SPI_ENGINE_CMD_REG_SDO_MASK 0x4 =20 #define SPI_ENGINE_MISC_SYNC 0x0 #define SPI_ENGINE_MISC_SLEEP 0x1 @@ -105,6 +110,10 @@ #define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16 #define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16 =20 +/* Extending SPI_MULTI_LANE_MODE values for optimizing messages. */ +#define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1 +#define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2 + struct spi_engine_program { unsigned int length; uint16_t instructions[] __counted_by(length); @@ -142,6 +151,11 @@ struct spi_engine_offload { unsigned long flags; unsigned int offload_num; unsigned int spi_mode_config; + unsigned int multi_lane_mode; + u8 rx_primary_lane_mask; + u8 tx_primary_lane_mask; + u8 rx_all_lanes_mask; + u8 tx_all_lanes_mask; u8 bits_per_word; }; =20 @@ -165,6 +179,25 @@ struct spi_engine { bool offload_requires_sync; }; =20 +static void spi_engine_primary_lane_flag(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + *rx_lane_flags =3D BIT(spi->rx_lane_map[0]); + *tx_lane_flags =3D BIT(spi->tx_lane_map[0]); +} + +static void spi_engine_all_lanes_flags(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + int i; + + for (i =3D 0; i < spi->num_rx_lanes; i++) + *rx_lane_flags |=3D BIT(spi->rx_lane_map[i]); + + for (i =3D 0; i < spi->num_tx_lanes; i++) + *tx_lane_flags |=3D BIT(spi->tx_lane_map[i]); +} + static void spi_engine_program_add_cmd(struct spi_engine_program *p, bool dry, uint16_t cmd) { @@ -193,7 +226,7 @@ static unsigned int spi_engine_get_config(struct spi_de= vice *spi) } =20 static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry, - struct spi_transfer *xfer) + struct spi_transfer *xfer, u32 num_lanes) { unsigned int len; =20 @@ -204,6 +237,9 @@ static void spi_engine_gen_xfer(struct spi_engine_progr= am *p, bool dry, else len =3D xfer->len / 4; =20 + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + len /=3D num_lanes; + while (len) { unsigned int n =3D min(len, 256U); unsigned int flags =3D 0; @@ -269,6 +305,7 @@ static int spi_engine_precompile_message(struct spi_mes= sage *msg) { unsigned int clk_div, max_hz =3D msg->spi->controller->max_speed_hz; struct spi_transfer *xfer; + int multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN; u8 min_bits_per_word =3D U8_MAX; u8 max_bits_per_word =3D 0; =20 @@ -284,6 +321,24 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) min_bits_per_word =3D min(min_bits_per_word, xfer->bits_per_word); max_bits_per_word =3D max(max_bits_per_word, xfer->bits_per_word); } + + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + switch (xfer->multi_lane_mode) { + case SPI_MULTI_LANE_MODE_SINGLE: + case SPI_MULTI_LANE_MODE_STRIPE: + break; + default: + /* Other modes, like mirror not supported */ + return -EINVAL; + } + + /* If all xfers have the same multi-lane mode, we can optimize. */ + if (multi_lane_mode =3D=3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN) + multi_lane_mode =3D xfer->multi_lane_mode; + else if (multi_lane_mode !=3D xfer->multi_lane_mode) + multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING; + } } =20 /* @@ -297,6 +352,14 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) priv->bits_per_word =3D min_bits_per_word; else priv->bits_per_word =3D 0; + + priv->multi_lane_mode =3D multi_lane_mode; + spi_engine_primary_lane_flag(msg->spi, + &priv->rx_primary_lane_mask, + &priv->tx_primary_lane_mask); + spi_engine_all_lanes_flags(msg->spi, + &priv->rx_all_lanes_mask, + &priv->tx_all_lanes_mask); } =20 return 0; @@ -310,6 +373,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, struct spi_engine_offload *priv; struct spi_transfer *xfer; int clk_div, new_clk_div, inst_ns; + int prev_multi_lane_mode =3D SPI_MULTI_LANE_MODE_SINGLE; bool keep_cs =3D false; u8 bits_per_word =3D 0; =20 @@ -334,6 +398,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, * in the same way. */ bits_per_word =3D priv->bits_per_word; + prev_multi_lane_mode =3D priv->multi_lane_mode; } else { spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG, @@ -344,6 +409,28 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, spi_engine_gen_cs(p, dry, spi, !xfer->cs_off); =20 list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + if (xfer->multi_lane_mode !=3D prev_multi_lane_mode) { + u8 tx_lane_flags, rx_lane_flags; + + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + spi_engine_all_lanes_flags(spi, &rx_lane_flags, + &tx_lane_flags); + else + spi_engine_primary_lane_flag(spi, &rx_lane_flags, + &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags)); + } + prev_multi_lane_mode =3D xfer->multi_lane_mode; + } + new_clk_div =3D host->max_speed_hz / xfer->effective_speed_hz; if (new_clk_div !=3D clk_div) { clk_div =3D new_clk_div; @@ -360,7 +447,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, bits_per_word)); } =20 - spi_engine_gen_xfer(p, dry, xfer); + spi_engine_gen_xfer(p, dry, xfer, spi->num_rx_lanes); spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer), inst_ns, xfer->effective_speed_hz); =20 @@ -394,6 +481,19 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, if (clk_div !=3D 1) spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0)); + + /* Restore single lane mode unless offload disable will restore it later.= */ + if (prev_multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE && + (!msg->offload || priv->multi_lane_mode !=3D SPI_MULTI_LANE_MODE_STRI= PE)) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(spi, &rx_lane_flags, &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, tx_lane_flags)); + } } =20 static void spi_engine_xfer_next(struct spi_message *msg, @@ -799,6 +899,19 @@ static int spi_engine_setup(struct spi_device *device) writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (host->num_data_lanes > 1) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(device, &rx_lane_flags, &tx_lane_flags); + + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + /* * In addition to setting the flags, we have to do a CS assert command * to make the new setting actually take effect. @@ -902,6 +1015,15 @@ static int spi_engine_trigger_enable(struct spi_offlo= ad *offload) priv->bits_per_word), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + writel_relaxed(SPI_ENGINE_CMD_SYNC(1), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 @@ -929,6 +1051,16 @@ static void spi_engine_trigger_disable(struct spi_off= load *offload) reg &=3D ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE; writel_relaxed(reg, spi_engine->base + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num)); + + /* Restore single-lane mode. */ + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } } =20 static struct dma_chan @@ -973,7 +1105,7 @@ static int spi_engine_probe(struct platform_device *pd= ev) { struct spi_engine *spi_engine; struct spi_controller *host; - unsigned int version; + unsigned int version, data_width_reg_val; int irq, ret; =20 irq =3D platform_get_irq(pdev, 0); @@ -1042,7 +1174,7 @@ static int spi_engine_probe(struct platform_device *p= dev) return PTR_ERR(spi_engine->base); =20 version =3D readl(spi_engine->base + ADI_AXI_REG_VERSION); - if (ADI_AXI_PCORE_VER_MAJOR(version) !=3D 1) { + if (ADI_AXI_PCORE_VER_MAJOR(version) > 2) { dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%u\n", ADI_AXI_PCORE_VER_MAJOR(version), ADI_AXI_PCORE_VER_MINOR(version), @@ -1050,6 +1182,8 @@ static int spi_engine_probe(struct platform_device *p= dev) return -ENODEV; } =20 + data_width_reg_val =3D readl(spi_engine->base + SPI_ENGINE_REG_DATA_WIDTH= ); + if (adi_axi_pcore_ver_gteq(version, 1, 1)) { unsigned int sizes =3D readl(spi_engine->base + SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH); @@ -1096,6 +1230,9 @@ static int spi_engine_probe(struct platform_device *p= dev) } if (adi_axi_pcore_ver_gteq(version, 1, 3)) host->mode_bits |=3D SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; + if (adi_axi_pcore_ver_gteq(version, 2, 0)) + host->num_data_lanes =3D FIELD_GET(SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO= _MASK, + data_width_reg_val); =20 if (host->max_speed_hz =3D=3D 0) return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0"); --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oi1-f171.google.com (mail-oi1-f171.google.com [209.85.167.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4309B2EF65C for ; Fri, 23 Jan 2026 20:38:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200735; cv=none; b=XSpXAwdRsxVwDTYr+tMA51gyCKbK4yzAx4VAfGyMfoVymasEVdfzwFyZJzDFhQOfcDl0FeHhJu/x2dHrGRNNGYE1q7Rc0XFa/4CeZQxY74PybN3TAXEMJXxUWzq7gsg077kh07aoUimeX+L3O08umHFZv+lQ4He+kDu97M2JVHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200735; c=relaxed/simple; bh=0SRGld8wg9ob4xVn5NpAO3HJVSu6bKkd/d9jBcJCtAo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WIkzTH3gLVaKxK439OfKETJnEGae5/h0WCDA+cNWBBwBhDBT079aPwd6KqkzPhCS3Sq9x8BGVq+H6qDXdjGdgzk/FnCOe1houHQLAxQXjfdWpo90fthh4SGvrSIUachR2jesbdcK0maFYfkDTXNJ76ckfjbeT9ynkFRRsA+UzUU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=xzIrvnF7; arc=none smtp.client-ip=209.85.167.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="xzIrvnF7" Received: by mail-oi1-f171.google.com with SMTP id 5614622812f47-45c962424daso806182b6e.2 for ; Fri, 23 Jan 2026 12:38:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200730; x=1769805530; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lRCMa7QMJdZhKtVQUIWaGLlL9RgCPrH55zdDP01EigE=; b=xzIrvnF762GBAObHQ2rZhb5ZgMhMMLbsTSmgBZ4rSwfyBl5qKiAKcKIZAwG3rWLADE aX6QmrcJbAC139Wv6WmpPdtF2rbEJiocvy8xeWgcCVeaTRsRxfgTN9/0MwCKcH4cgkeT clco2n4E1skD+wzXHLf5PhUw4KPuNZKHZRT4ZHSm1DUSzB9exHmHtzEIC9JAjG0OiXWR 76cTVFvFPM87wjRNamza3lW8VMzK938801OiCgoLjv97HNHiCUH7gNpNJ+NsJBhE+5Yr uMLseAFYb+gI9UqZv6OIaTRL41HXlrX0rZ4Co78nl7I0FpHqxpRw5jSv3WUrcSaTohcZ 9Y8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200730; x=1769805530; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=lRCMa7QMJdZhKtVQUIWaGLlL9RgCPrH55zdDP01EigE=; b=d4w9HqCPKLP+oy45kEbC/tCWlKqDYuI9d6LXlTzPyDyoG0bzBRy8nlatBw8KyIWBmK OkgSr9Mg5WLTg+o57Dn52hHTjUr3vwv86QOganDUwTBKLmbb0nECtjC6pA7YRCAQU/Kb hRaO3aK9TwD0l26MleBBAlQIden7Ow7ZwGQ9cxwwc7X+ZubYtyyfAdCH2HX/5W/bCY/F gwzQJuxyzFUc/UDT9H9TVfAjiokGiqRipbC7KpbG20a4Ga7AgylEgc81UEaFQccj8X9Y 3Q2mNPXo7SA5YEfZEmBXoMm7Qk9EShC776lAB1l0HRGJMcDKCu0c3hUE397szPw5A6/E aj8g== X-Forwarded-Encrypted: i=1; AJvYcCV0A1Ko5AyhTBzFrXPts3pDOP1KsMvYuTHk7llNceo2xx9BY23sGwwmZUQZh3Je/FWpocm6atE6Ponen5M=@vger.kernel.org X-Gm-Message-State: AOJu0Yz2/lhpGtoJLBhPhKPQYB8B/qtSa01yM+MlkYTfmE08J1g1d0DQ y4ApxoMKL9l3ZJY1kRoV/M3Pod4dzp4QZ03jJyNBcLlWJcP0VWIyo90cTrivwb2gU/E= X-Gm-Gg: AZuq6aKmDpxXPUBuVQT9S/mnSVPvnYKdnlzjL3bCMHAAn2RjT9uGiC6GPIrxEA1Wyws itN2Ib0gn+v1ayOxyC28pzRPRG1peaISLurjmMoMMMUKdPajcUSpMH765AerLeKNsEVtersDU4k 1hc1dun5Ul5F8BKveThi1dDUZj4m3ZeTPqwbwQyUw4I8vh8RjZ2/PEi9lEIaKMWR9JTlotCep2b SbEHtAfpJ3bZWmqjZn0jUpryoF96DGw+Mt9C5Ep266S8fSaecYW5N8akEk/9bIBc6g/D9ud7ns0 1fU709WJZEckmYKXh5soT7+UDQlqBxYcfUNLh7Fcybi/5caWzsTQTdY4DpBakcbVWY7pXC8s93L DIaH5eRdB4iU8JUh+seUJ3MCYcM/K4iWBwgjPZ634TOCnoxQFhJ7hW01/Fp0uAjwmdWTqu579e3 bvNAhtLiWSt6+EolBQ+kOjLg6P X-Received: by 2002:a05:6808:1306:b0:44d:baaa:c537 with SMTP id 5614622812f47-45eb1ac4ff3mr2135834b6e.11.1769200730536; Fri, 23 Jan 2026 12:38:50 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:50 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:31 -0600 Subject: [PATCH v6 8/9] dt-bindings: iio: adc: adi,ad7380: add spi-rx-bus-width property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-8-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2086; i=dlechner@baylibre.com; h=from:subject:message-id; bh=0SRGld8wg9ob4xVn5NpAO3HJVSu6bKkd/d9jBcJCtAo=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9w9z/Zrr1ZFq1ZeucdXrgMdnDu88JnIRiD1n rYl/9vfUCSJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcPQAKCRDCzCAB/wGP wACVB/94YY1h4opJbziyMfR8A33W8WxV7v7l0Isb56J4ij4epEbYwIO45nuXIaUJfWqyNxDJY9y YFnG5YsmtuiBrrxaW/U4JTM5bKHF76nbLCESS+L3A+6HaWJiJynP5CzbZn/D48gS4Lz09gsznd7 PcHIHkdgAVKrj/9MaZAXFFZhs90hnhrZMHMB0xXb6yQpeQEgmwbV6Hg8g/PD2nBfRmXqSsC96cm HvzVhg5OmCJ9rPlpSJhk4g8a2PL8LdRtuPkYHxsu6Jm8DCyGqqf5rfTnmcjph5FnsCxjyHlnFLd w4MZPIGgU3ayqA6cd2zc9vFDKhWmDeSLKa5IRhDyQ//Wq33K X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add spi-rx-bus-width property to describe how many SDO lines are wired up on the ADC. These chips are simultaneous sampling ADCs and have one SDO line per channel, either 2 or 4 total depending on the part number. Reviewed-by: Rob Herring (Arm) Signed-off-by: David Lechner --- v6 changes: none v5 changes: none v4 changes: * Change to use spi-rx-bus-width property instead of spi-lanes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 23 ++++++++++++++++++= ++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index b91bfb16ed6b..396e1a1aa805 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -62,6 +62,11 @@ properties: spi-cpol: true spi-cpha: true =20 + spi-rx-bus-width: + maxItems: 4 + items: + maximum: 1 + vcc-supply: description: A 3V to 3.6V supply that powers the chip. =20 @@ -160,6 +165,23 @@ patternProperties: unevaluatedProperties: false =20 allOf: + # 2-channel chips only have two SDO lines + - if: + properties: + compatible: + enum: + - adi,ad7380 + - adi,ad7381 + - adi,ad7383 + - adi,ad7384 + - adi,ad7386 + - adi,ad7387 + - adi,ad7388 + then: + properties: + spi-rx-bus-width: + maxItems: 2 + # pseudo-differential chips require common mode voltage supplies, # true differential chips don't use them - if: @@ -284,6 +306,7 @@ examples: spi-cpol; spi-cpha; spi-max-frequency =3D <80000000>; + spi-rx-bus-width =3D <1>, <1>, <1>, <1>; =20 interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; interrupt-parent =3D <&gpio0>; --=20 2.43.0 From nobody Sun Feb 8 15:07:49 2026 Received: from mail-oa1-f45.google.com (mail-oa1-f45.google.com [209.85.160.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 132BD2F5319 for ; Fri, 23 Jan 2026 20:38:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200737; cv=none; b=fhpwZRqCSngINlex4yHkauj+y/8dw8aOnlIhfNT8sO9M6WB34LLx8dkXMzW/SHngFylVFFbctfQqZKy+zwOSbgDB5fCL3GfkKTkIqNvJKa27kAwfVfqRZqFaQgtNcPvUPWW/BEetNXf6igLVcjYEKon5V/3MNvdoHfPfYdh3X28= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769200737; c=relaxed/simple; bh=2C6i3NBXyh26o+VI6Lld/UbaveXiw02diDxZ2kfzhPE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SXeqR+3HCT01zeLKg+PlHLW16KFXA9UVMqxHAg6U9bvWjgu6UVV8Y+Mt16nxvqxWTG9wR/a1kKY0SnjlYMoRG1nqAOwErM7epkedwVqCrkrYpA2IXVbxX4HlNNRc5udA2FqqLMIYQcvy64liQP+A78bsPrsj1XkpLe/WvVA2vLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=GHR802oR; arc=none smtp.client-ip=209.85.160.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="GHR802oR" Received: by mail-oa1-f45.google.com with SMTP id 586e51a60fabf-408778a8ec4so1729907fac.0 for ; Fri, 23 Jan 2026 12:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1769200732; x=1769805532; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CbdZS75AKMVh8QDM0w0436GKbW8GMgnOih9TIeXC38A=; b=GHR802oRGTmGP+m43X+o8HB2AzxUHzwkDazDTfrFrS3vTnksz/JVttuD1a4352kNyL f0vf0rJdN0y1qHe1xIZTqhW07hOPnI+a03eZMMTekTeaYeOUGHF8Ro5m6JJYtSBpEswP zIiVJd/zABTNwIoEQjEVrnuFielorme7Rj0sJmkuom7a3jRnqPRnfGRxXTWuV+X92xph PL/kqxBrY404t8O5vy7lnAkdP8z+UEaQ3KBFZz35Ue/VKA2KcQSevGa3RGk3Y2qBgR3Q iAHF/Y7007/wNHya0U/yh/Gvs/jNaLySDRVI3+V4jT5jis/qRlPdjSaE92jxZ2aMcUWA I0sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769200732; x=1769805532; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=CbdZS75AKMVh8QDM0w0436GKbW8GMgnOih9TIeXC38A=; b=AuHqea1JQ45kb052K/Q/wiu6WWl6WvKZbfUuWNhvrc4dQnJpsaPhawk0Th1YW9a5F0 BgATzO8np+jTYKwqd6ataX43qLCBrSJTNZx9UimIu/OcNr7R2LQTzR3ByjRxppVwjy66 idl/14kwdGKH8c482SGz6Ufqdsmpeajpiy9v3r0f3CZ9InxdgLXdTZ2LQgIgjlI9Qtw1 uBUNOQm81vwcmI5CiaU+QhOLDwQv9qGH+xRirdIaKPbN0VsFe+lqIv0WtAWWm8x5XLy4 4p4pZfEdQ2EForsBxTdVRYOewmLVT2wasCrsZZk42DY2ZjGZ8bkQg4kiqDm/btyuGvHg njUw== X-Forwarded-Encrypted: i=1; AJvYcCVsFug00WaOM/JLdljPuTYkbrTaOgn/LXY5lBiXgbv1FMw01w+W+YpwmkbPKUHIXGBxbkvZEy3pjUFyN+U=@vger.kernel.org X-Gm-Message-State: AOJu0YwAtnfwfpmMZwnKB5kqFEWGJ8HvKrhyGsuHLvkgeIL9s6lJRvSi mQwVlfFpLDxmB8CMtCxPiqoMIcToCt3jVRGG7KoamJsW/urCbVrFZNfnEag+WZSSNl8= X-Gm-Gg: AZuq6aIoWZMq6se+Zu95CJ6AZws6C7S9WIacQSPvfYbUVYkOHMTXLxTRsYzQ/T7bwTH G31vj7gDNqjd7X6xmndrfx9s85NDsFlVaaKukfTmP7EvPlN+hkk4cIK0uzwUoa43fUGt+NW6I8W +WQVDUmgiVpXk19mZqAKkZpiocYWBcXn/5B6UxHwAErwrEWp8coRtPPCPmKsJxDUlF1ew+g60Iv 3VLXBeWSiX/LSxOX1sacS3i60NYyVt5vksAFweVnWQDX0kk1Ba7Vrk2a8LaKyf9y40YfgDrYm2Z JT/mgQuWEBtcoC3LwlNzdLsi3RTXVQZ7ze3zWjc+Lh6GPNjA4IuINuvbzMJB1JfnJXoCQCyJtBB UHw/u3JG58AZuCkpX4iZHuzMeHMI8yK05dA+qMiVCr+VLJkIgnq/znw4JruAohPEUP3BnRm2ukO 4nOpbFo3ldk8XMAQ== X-Received: by 2002:a05:6870:f215:b0:3f5:5d85:80d2 with SMTP id 586e51a60fabf-408ab7e291bmr2111309fac.43.1769200732405; Fri, 23 Jan 2026 12:38:52 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:198f:2b50:c48:1875]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-408af888da1sm2167805fac.6.2026.01.23.12.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 12:38:51 -0800 (PST) From: David Lechner Date: Fri, 23 Jan 2026 14:37:32 -0600 Subject: [PATCH v6 9/9] iio: adc: ad7380: add support for multiple SPI lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-spi-add-multi-bus-support-v6-9-12af183c06eb@baylibre.com> References: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> In-Reply-To: <20260123-spi-add-multi-bus-support-v6-0-12af183c06eb@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6262; i=dlechner@baylibre.com; h=from:subject:message-id; bh=2C6i3NBXyh26o+VI6Lld/UbaveXiw02diDxZ2kfzhPE=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpc9xEN+k0R7Bic+VA3HmpepXcuhZgilXf5ajsv oYVQbn21oeJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaXPcRAAKCRDCzCAB/wGP wNFoB/9VGW1yDYrM8DKEAfnpAkhTWzsoBaVaQHqlbzdkgE3UKW+5yKu2LwOHodIbKhFEot94REK 9+PQGVW2urhNn7geTxRmFFLrHP4x8tLzvJLnspiTwGVqZthwKxQdtyUv2wt9KrEZrbCF9ISQQ13 FxRKgWfYbAvKvwQ07qHvxrOb35V8/8LhL1B8X3PUFYZIz5pjQC6DQQI360SBMeJHavSxgJwzk9J AksPUKILzD6DgmBNzuDK3Y2C1e0xpUSuJ3X39RhtahkzBwPZKRJDRk7+SbvUpwQMKJAGsID1ilO WaglwEThPxE3LipUhfMt7MT8CS85j8SGxxHNwihy9LTExgLS X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for multiple SPI lanes to increase throughput. The AD7380 family of ADCs have multiple SDO lines on the chip that can be used to read each channel on a separate SPI lane. If wired up to a SPI controller that supports it, the driver will now take advantage of this feature. This allows reaching the maximum sample rate advertised in the datasheet when combined with SPI offloading. Reviewed-by: Nuno S=C3=A1 Reviewed-by: Marcelo Schmitt Signed-off-by: David Lechner --- v6 changes: none v5 changes: * Include the number of SDO lines in the error message. v4 changes: * Update for core SPI API changes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. v2 changes: * Move st->seq_xfer[3].multi_lane_mode =3D SPI_MULTI_BUS_MODE_STRIPE; to probe(). --- drivers/iio/adc/ad7380.c | 51 ++++++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index bfd908deefc0..ca411371816f 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -77,8 +77,7 @@ #define AD7380_CONFIG1_REFSEL BIT(1) #define AD7380_CONFIG1_PMODE BIT(0) =20 -#define AD7380_CONFIG2_SDO2 GENMASK(9, 8) -#define AD7380_CONFIG2_SDO BIT(8) +#define AD7380_CONFIG2_SDO GENMASK(9, 8) #define AD7380_CONFIG2_RESET GENMASK(7, 0) =20 #define AD7380_CONFIG2_RESET_SOFT 0x3C @@ -92,11 +91,6 @@ #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ #define T_POWERUP_US 5000 /* Power up */ =20 -/* - * AD738x support several SDO lines to increase throughput, but driver cur= rently - * supports only 1 SDO line (standard SPI transaction) - */ -#define AD7380_NUM_SDO_LINES 1 #define AD7380_DEFAULT_GAIN_MILLI 1000 =20 /* @@ -888,6 +882,8 @@ struct ad7380_state { bool resolution_boost_enabled; unsigned int ch; bool seq; + /* How many SDO lines are wired up. */ + u8 num_sdo_lines; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; unsigned int gain_milli[MAX_NUM_CHANNELS]; @@ -1084,7 +1080,7 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) if (oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->num_sdo_lines; =20 return spi_sync_transfer(st->spi, &xfer, 1); } @@ -1113,7 +1109,7 @@ static int ad7380_update_xfers(struct ad7380_state *s= t, if (oversampling_ratio > 1) t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->num_sdo_lines; =20 if (st->seq) { xfer[0].delay.value =3D xfer[1].delay.value =3D t_convert; @@ -1198,6 +1194,8 @@ static int ad7380_init_offload_msg(struct ad7380_stat= e *st, xfer->bits_per_word =3D scan_type->realbits; xfer->offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; xfer->len =3D AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_cha= nnels; + if (st->num_sdo_lines > 1) + xfer->multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); st->offload_msg.offload =3D st->offload; @@ -1793,6 +1791,7 @@ static const struct iio_info ad7380_info =3D { =20 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) { + u32 sdo; int ret; =20 /* perform hard reset */ @@ -1815,11 +1814,24 @@ static int ad7380_init(struct ad7380_state *st, boo= l external_ref_en) st->ch =3D 0; st->seq =3D false; =20 - /* SPI 1-wire mode */ + /* SDO field has an irregular mapping. */ + switch (st->num_sdo_lines) { + case 1: + sdo =3D 1; + break; + case 2: + sdo =3D 0; + break; + case 4: + sdo =3D 2; + break; + default: + return -EINVAL; + } + return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, AD7380_CONFIG2_SDO, - FIELD_PREP(AD7380_CONFIG2_SDO, - AD7380_NUM_SDO_LINES)); + FIELD_PREP(AD7380_CONFIG2_SDO, sdo)); } =20 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, @@ -1842,7 +1854,7 @@ static int ad7380_probe_spi_offload(struct iio_dev *i= ndio_dev, "failed to get offload trigger\n"); =20 sample_rate =3D st->chip_info->max_conversion_rate_hz * - AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; + st->num_sdo_lines / st->chip_info->num_simult_channels; =20 st->sample_freq_range[0] =3D 1; /* min */ st->sample_freq_range[1] =3D 1; /* step */ @@ -1887,6 +1899,13 @@ static int ad7380_probe(struct spi_device *spi) if (!st->chip_info) return dev_err_probe(dev, -EINVAL, "missing match data\n"); =20 + st->num_sdo_lines =3D spi->num_rx_lanes; + + if (st->num_sdo_lines < 1 || st->num_sdo_lines > st->chip_info->num_simul= t_channels) + return dev_err_probe(dev, -EINVAL, + "invalid number of SDO lines (%d)\n", + st->num_sdo_lines); + ret =3D devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, st->chip_info->supplies); =20 @@ -2010,6 +2029,8 @@ static int ad7380_probe(struct spi_device *spi) st->normal_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs-= >t_csh_ns; st->normal_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; st->normal_xfer[1].rx_buf =3D st->scan_data; + if (st->num_sdo_lines > 1) + st->normal_xfer[1].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, ARRAY_SIZE(st->normal_xfer)); @@ -2031,6 +2052,10 @@ static int ad7380_probe(struct spi_device *spi) st->seq_xfer[2].cs_change =3D 1; st->seq_xfer[2].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; st->seq_xfer[2].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + if (st->num_sdo_lines > 1) { + st->seq_xfer[2].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + st->seq_xfer[3].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + } =20 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, ARRAY_SIZE(st->seq_xfer)); --=20 2.43.0