From nobody Sun Feb 8 06:56:36 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BC80322DD6 for ; Fri, 23 Jan 2026 16:13:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769184825; cv=none; b=Z5E17YyUi3OXFj7MTNFMv4z1/emtsbfYi6EBPIx+OBUB0T8JOWCwcMOL/qh38eC6SLUmrm+3JYn4/uxAw6PtXh0x3FeTO+eyXR6B6MDWpYXnAmWrIPCXlqH7yO7LfO0tanPx92S3879nvdw6PMFABtmbmzsG9FA0swBWO3DJh04= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769184825; c=relaxed/simple; bh=LjruRetuhBkCdZTKnf6+OyPVR1au6V9U/STyFCuxxDg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pskRLU23tg2qWh0q3iJUAYSkCr/J3YW2d8Ekp5A0rIBHL3y+we5OiFM5tkskkoQ3BvMRlRb8tO5HBChuVVZ+KcodLILpfmHBZyMclryhJdOR41tPjVdTW6yTswCGNmU8NQsR0LV6TKGme8iiVW+DHdYLPWyDUV5rzDW5TYb5f+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=NUQiVbpo; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NUQiVbpo" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 97FFFC20308; Fri, 23 Jan 2026 16:13:40 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 478C26070A; Fri, 23 Jan 2026 16:13:40 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BE39E119A87A7; Fri, 23 Jan 2026 17:13:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769184819; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=TxkazZndhpz4hu0l8MUt2pUIjQAK5dSrvRAmWndU+T8=; b=NUQiVbpofkFO0KWVMkV1oxCMOryv/VC4CuxiygddQ4RbGnKazgBt/iWRiWYwqVVT8UWEA7 xRUoWiqUWRipSeWwwEgrZ6DicI4/CYnRqnRpWO5LwQxdXwCKJgBBoYJFLtlMfCX8Cwrh8L EDV+GuJuqGy8pq+GBd/NZxMrV2Vp73vyBcQoJUAC0XuD7oQb/PfAuYJ96i0ZSHaGRc4LU6 JcDLeGwx2guh+aFztSB+GbUfFV16NobqRUrQlH/H24nHZzmOlfWLWKCNP/hwni5KuXn+Vu wvgqp5oVM8mH2jCGUPHtImBXg4VHl0oJHk56hgqmIywH6/y2hrWyfW9lWqf2Lg== From: "Kory Maincent (TI.com)" Date: Fri, 23 Jan 2026 17:12:37 +0100 Subject: [PATCH v5 19/25] drm/tilcdc: Convert to drm_device-based logging helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-feature_tilcdc-v5-19-5a44d2aa3f6f@bootlin.com> References: <20260123-feature_tilcdc-v5-0-5a44d2aa3f6f@bootlin.com> In-Reply-To: <20260123-feature_tilcdc-v5-0-5a44d2aa3f6f@bootlin.com> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Bartosz Golaszewski , Tony Lindgren , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: Markus Schneider-Pargmann , Bajjuri Praneeth , Luca Ceresoli , Louis Chauvet , Thomas Petazzoni , Miguel Gazquez , Herve Codina , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, "Kory Maincent (TI.com)" X-Mailer: b4 0.15-dev-47773 X-Last-TLS-Session-Version: TLSv1.3 Replace dev_* logging calls with their DRM equivalents. This aligns with the DRM subsystem's logging infrastructure and provides better integration with DRM debugging mechanisms. The drm_* helpers automatically include device information and integrate with DRM's debug category filtering. Reviewed-by: Luca Ceresoli Signed-off-by: Kory Maincent (TI.com) --- Change in v4: - New patch. --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 26 +++++++++++++------------- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 16 ++++++++-------- drivers/gpu/drm/tilcdc/tilcdc_encoder.c | 4 ++-- drivers/gpu/drm/tilcdc/tilcdc_plane.c | 8 ++++---- 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/= tilcdc_crtc.c index 2916de3dce91e..4d3b7059cd5b2 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -125,7 +125,7 @@ static void tilcdc_crtc_load_palette(struct drm_crtc *c= rtc) ret =3D wait_for_completion_timeout(&tilcdc_crtc->palette_loaded, msecs_to_jiffies(50)); if (ret =3D=3D 0) - dev_err(dev->dev, "%s: Palette loading timeout", __func__); + drm_err(dev, "%s: Palette loading timeout", __func__); =20 /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */ tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); @@ -223,7 +223,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) */ if (!clk_rate) { /* Nothing more we can do. Just bail out. */ - dev_err(dev->dev, + drm_err(dev, "failed to set the pixel clock - unable to read current lcdc clock rat= e\n"); return; } @@ -240,7 +240,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) real_pclk_rate =3D clk_rate / clkdiv; =20 if (tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) { - dev_warn(dev->dev, + drm_warn(dev, "effective pixel clock rate (%luHz) differs from the requested rate (= %luHz)\n", real_pclk_rate, pclk_rate); } @@ -369,7 +369,7 @@ static void tilcdc_crtc_set_mode(struct drm_crtc *crtc) reg |=3D LCDC_V2_TFT_24BPP_MODE; break; default: - dev_err(dev->dev, "invalid pixel format\n"); + drm_err(dev, "invalid pixel format\n"); return; } } @@ -482,7 +482,7 @@ static void tilcdc_crtc_off(struct drm_crtc *crtc, bool= shutdown) tilcdc_crtc->frame_done, msecs_to_jiffies(500)); if (ret =3D=3D 0) - dev_err(dev->dev, "%s: timeout waiting for framedone\n", + drm_err(dev, "%s: timeout waiting for framedone\n", __func__); =20 drm_crtc_vblank_off(crtc); @@ -543,7 +543,7 @@ static void tilcdc_crtc_recover_work(struct work_struct= *work) container_of(work, struct tilcdc_crtc, recover_work); struct drm_crtc *crtc =3D &tilcdc_crtc->base; =20 - dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__); + drm_info(crtc->dev, "%s: Reset CRTC", __func__); =20 drm_modeset_lock(&crtc->mutex, NULL); =20 @@ -575,7 +575,7 @@ int tilcdc_crtc_update_fb(struct drm_crtc *crtc, struct drm_device *dev =3D crtc->dev; =20 if (tilcdc_crtc->event) { - dev_err(dev->dev, "already pending page flip!\n"); + drm_err(dev, "already pending page flip!\n"); return -EBUSY; } =20 @@ -707,7 +707,7 @@ static void tilcdc_crtc_reset(struct drm_crtc *crtc) tilcdc_crtc->frame_done, msecs_to_jiffies(500)); if (ret =3D=3D 0) - dev_err(dev->dev, "%s: timeout waiting for framedone\n", + drm_err(dev, "%s: timeout waiting for framedone\n", __func__); } pm_runtime_put_sync(dev->dev); @@ -895,7 +895,7 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) } =20 if (stat & LCDC_FIFO_UNDERFLOW) - dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow", + drm_err_ratelimited(dev, "%s(0x%08x): FIFO underflow", __func__, stat); =20 if (stat & LCDC_PL_LOAD_DONE) { @@ -909,7 +909,7 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) } =20 if (stat & LCDC_SYNC_LOST) { - dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", + drm_err_ratelimited(dev, "%s(0x%08x): Sync lost", __func__, stat); tilcdc_crtc->frame_intact =3D false; if (priv->rev =3D=3D 1) { @@ -923,7 +923,7 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) } else { if (tilcdc_crtc->sync_lost_count++ > SYNC_LOST_COUNT_LIMIT) { - dev_err(dev->dev, + drm_err(dev, "%s(0x%08x): Sync lost flood detected, recovering", __func__, stat); queue_work(system_wq, @@ -965,7 +965,7 @@ int tilcdc_crtc_create(struct drm_device *dev) =20 primary =3D tilcdc_plane_init(dev); if (IS_ERR(primary)) { - dev_err(dev->dev, "Failed to initialize plane: %pe\n", primary); + drm_err(dev, "Failed to initialize plane: %pe\n", primary); return PTR_ERR(primary); } =20 @@ -975,7 +975,7 @@ int tilcdc_crtc_create(struct drm_device *dev) &tilcdc_crtc_funcs, "tilcdc crtc"); if (IS_ERR(tilcdc_crtc)) { - dev_err(dev->dev, "Failed to init CRTC: %pe\n", tilcdc_crtc); + drm_err(dev, "Failed to init CRTC: %pe\n", tilcdc_crtc); return PTR_ERR(tilcdc_crtc); } =20 diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/t= ilcdc_drv.c index 3b11d296a7e91..c877b2be9c2ec 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -288,14 +288,14 @@ static int tilcdc_pdev_probe(struct platform_device *= pdev) =20 priv->mmio =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->mmio)) { - dev_err(dev, "failed to request / ioremap\n"); + drm_err(ddev, "failed to request / ioremap\n"); ret =3D PTR_ERR(priv->mmio); goto free_wq; } =20 priv->clk =3D clk_get(dev, "fck"); if (IS_ERR(priv->clk)) { - dev_err(dev, "failed to get functional clock\n"); + drm_err(ddev, "failed to get functional clock\n"); ret =3D -ENODEV; goto free_wq; } @@ -313,7 +313,7 @@ static int tilcdc_pdev_probe(struct platform_device *pd= ev) priv->rev =3D 2; break; default: - dev_warn(dev, "Unknown PID Reg value 0x%08x, " + drm_warn(ddev, "Unknown PID Reg value 0x%08x, " "defaulting to LCD revision 1\n", tilcdc_read(ddev, LCDC_PID_REG)); priv->rev =3D 1; @@ -380,7 +380,7 @@ static int tilcdc_pdev_probe(struct platform_device *pd= ev) =20 ret =3D tilcdc_crtc_create(ddev); if (ret < 0) { - dev_err(dev, "failed to create crtc\n"); + drm_err(ddev, "failed to create crtc\n"); goto disable_pm; } modeset_init(ddev); @@ -390,7 +390,7 @@ static int tilcdc_pdev_probe(struct platform_device *pd= ev) ret =3D cpufreq_register_notifier(&priv->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); if (ret) { - dev_err(dev, "failed to register cpufreq notifier\n"); + drm_err(ddev, "failed to register cpufreq notifier\n"); priv->freq_transition.notifier_call =3D NULL; goto disable_pm; } @@ -401,14 +401,14 @@ static int tilcdc_pdev_probe(struct platform_device *= pdev) goto unregister_cpufreq_notif; =20 if (!priv->connector) { - dev_err(dev, "no encoders/connectors found\n"); + drm_err(ddev, "no encoders/connectors found\n"); ret =3D -EPROBE_DEFER; goto unregister_cpufreq_notif; } =20 ret =3D drm_vblank_init(ddev, 1); if (ret < 0) { - dev_err(dev, "failed to initialize vblank\n"); + drm_err(ddev, "failed to initialize vblank\n"); goto unregister_cpufreq_notif; } =20 @@ -419,7 +419,7 @@ static int tilcdc_pdev_probe(struct platform_device *pd= ev) =20 ret =3D tilcdc_irq_install(ddev, priv->irq); if (ret < 0) { - dev_err(dev, "failed to install IRQ handler\n"); + drm_err(ddev, "failed to install IRQ handler\n"); goto unregister_cpufreq_notif; } =20 diff --git a/drivers/gpu/drm/tilcdc/tilcdc_encoder.c b/drivers/gpu/drm/tilc= dc/tilcdc_encoder.c index 1ee5761757a8c..a34a10337f6a8 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_encoder.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_encoder.c @@ -25,7 +25,7 @@ struct drm_connector *tilcdc_encoder_find_connector(struc= t drm_device *ddev, return connector; } =20 - dev_err(ddev->dev, "No connector found for %s encoder (id %d)\n", + drm_err(ddev, "No connector found for %s encoder (id %d)\n", encoder->name, encoder->base.id); =20 return NULL; @@ -68,7 +68,7 @@ int tilcdc_encoder_create(struct drm_device *ddev) encoder =3D drmm_simple_encoder_alloc(ddev, struct tilcdc_encoder, base, DRM_MODE_ENCODER_NONE); if (IS_ERR(encoder)) { - dev_err(ddev->dev, "drm_encoder_init() failed %pe\n", encoder); + drm_err(ddev, "drm_encoder_init() failed %pe\n", encoder); return PTR_ERR(encoder); } priv->encoder =3D encoder; diff --git a/drivers/gpu/drm/tilcdc/tilcdc_plane.c b/drivers/gpu/drm/tilcdc= /tilcdc_plane.c index d98a1ae0e31f8..a9982a9956903 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_plane.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_plane.c @@ -36,7 +36,7 @@ static int tilcdc_plane_atomic_check(struct drm_plane *pl= ane, return -EINVAL; =20 if (new_state->crtc_x || new_state->crtc_y) { - dev_err(plane->dev->dev, "%s: crtc position must be zero.", + drm_err(plane->dev, "%s: crtc position must be zero.", __func__); return -EINVAL; } @@ -48,7 +48,7 @@ static int tilcdc_plane_atomic_check(struct drm_plane *pl= ane, =20 if (crtc_state->mode.hdisplay !=3D new_state->crtc_w || crtc_state->mode.vdisplay !=3D new_state->crtc_h) { - dev_err(plane->dev->dev, + drm_err(plane->dev, "%s: Size must match mode (%dx%d =3D=3D %dx%d)", __func__, crtc_state->mode.hdisplay, crtc_state->mode.vdisplay, new_state->crtc_w, new_state->crtc_h); @@ -58,13 +58,13 @@ static int tilcdc_plane_atomic_check(struct drm_plane *= plane, pitch =3D crtc_state->mode.hdisplay * new_state->fb->format->cpp[0]; if (new_state->fb->pitches[0] !=3D pitch) { - dev_err(plane->dev->dev, + drm_err(plane->dev, "Invalid pitch: fb and crtc widths must be the same"); return -EINVAL; } =20 if (old_state->fb && new_state->fb->format !=3D old_state->fb->format) { - dev_dbg(plane->dev->dev, + drm_dbg(plane->dev, "%s(): pixel format change requires mode_change\n", __func__); crtc_state->mode_changed =3D true; --=20 2.43.0