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Thu, 22 Jan 2026 23:12:30 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a802f978e0sm11336775ad.62.2026.01.22.23.12.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 23:12:30 -0800 (PST) From: Abhinaba Rakshit Date: Fri, 23 Jan 2026 12:42:12 +0530 Subject: [PATCH v3 1/3] soc: qcom: ice: Add OPP-based clock scaling support for ICE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-enable-ufs-ice-clock-scaling-v3-1-d0d8532abd98@oss.qualcomm.com> References: <20260123-enable-ufs-ice-clock-scaling-v3-0-d0d8532abd98@oss.qualcomm.com> In-Reply-To: <20260123-enable-ufs-ice-clock-scaling-v3-0-d0d8532abd98@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. 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Petersen" , Neeraj Soni Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Proofpoint-GUID: uJueoAmzMHhMta_4TH0gTIsIO0V1d1EN X-Authority-Analysis: v=2.4 cv=I5lohdgg c=1 sm=1 tr=0 ts=69731f60 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=GaBF8cNdLVowMAKyZsMA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: uJueoAmzMHhMta_4TH0gTIsIO0V1d1EN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIzMDA1NCBTYWx0ZWRfX7ymx+q8ofOFJ WNwoHpyid4l6zm8npZdpUaGiPRERmVAaT+mKbKGcxZ9paOG/FUeMSGKrui2jMRIx5TW7Bax5M1n X6HM7XJAsgTwP0yIa2Yg4Mr8zhlmViiFV2PmrNJmpNpybBNnQ7h6VQLCNJxU3ZhD5uW53AWkXd7 xweiwDgg/BRnDWUYyrVyhdBA6Xz/uHU1GHLL7ZCnT84ezXxbbvKSkncvcKDkw0vRdyDvixR5/Ta ORxMndxE+zSfNvsSPCYRcmT8m29WSTk+YlpvmM1c8dN8r7A4blIEOfEea+86s0gX4WBfQQL5yJJ qsaHWFub4kSkcTFcr2oJNyCiJV/sDKyJYEWVsNADKblpaLbJ+ysyK3Rhy95ikzfxOMiP6U1i8hj m53v87YeNDiACSadBAR4QMmacIFhXIHWG9ABKuAWvC6mqY1twEfThjSXk2iyOfodvDVPnoA6EEr R/nCeKKpnqqeIdzTgwA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_06,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601230054 Register optional operation-points-v2 table for ICE device and aquire its minimum and maximum frequency during ICE device probe. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock if valid (non-zero) frequencies are obtained from OPP-table. Disable clock scaling if OPP-table is not registered. When an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/soc/qcom/ice.h | 1 + 2 files changed, 64 insertions(+) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cadd21d6f96eb1799963a13db4b2b72..ca6a7df7a6827378af1f013c7e6= 2a835d1b80cc5 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -111,6 +112,9 @@ struct qcom_ice { bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; + unsigned long max_freq; + unsigned long min_freq; + bool has_opp; }; =20 static bool qcom_ice_check_supported(struct qcom_ice *ice) @@ -549,10 +553,29 @@ int qcom_ice_import_key(struct qcom_ice *ice, } EXPORT_SYMBOL_GPL(qcom_ice_import_key); =20 +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up) +{ + int ret =3D 0; + + if (!ice->has_opp) + return ret; + + if (scale_up && ice->max_freq) + ret =3D dev_pm_opp_set_rate(ice->dev, ice->max_freq); + else if (!scale_up && ice->min_freq) + ret =3D dev_pm_opp_set_rate(ice->dev, ice->min_freq); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk); + static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { struct qcom_ice *engine; + struct dev_pm_opp *opp; + int err; + unsigned long rate; =20 if (!qcom_scm_is_available()) return ERR_PTR(-EPROBE_DEFER); @@ -584,6 +607,46 @@ static struct qcom_ice *qcom_ice_create(struct device = *dev, if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); =20 + /* Register the OPP table only when ICE is described as a standalone + * device node. Older platforms place ICE inside the storage controller + * node, so they don't need an OPP table here, as they are handled in + * storage controller. + */ + if (of_device_is_compatible(dev->of_node, "qcom,inline-crypto-engine")) { + /* OPP table is optional */ + err =3D devm_pm_opp_of_add_table(dev); + if (err && err !=3D -ENODEV) { + dev_err(dev, "Invalid OPP table in Device tree\n"); + return ERR_PTR(err); + } + engine->has_opp =3D (err =3D=3D 0); + + if (!engine->has_opp) + dev_info(dev, "ICE OPP table is not registered\n"); + } + + if (engine->has_opp) { + /* Find the ICE core clock min frequency */ + rate =3D 0; + opp =3D dev_pm_opp_find_freq_ceil_indexed(dev, &rate, 0); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock min freq\n"); + } else { + engine->min_freq =3D rate; + dev_pm_opp_put(opp); + } + + /* Find the ICE core clock max frequency */ + rate =3D ULONG_MAX; + opp =3D dev_pm_opp_find_freq_floor_indexed(dev, &rate, 0); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock max freq\n"); + } else { + engine->max_freq =3D rate; + dev_pm_opp_put(opp); + } + } + if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); =20 diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..b701ec9e062f70152f6dea8bf6c= 4637ab6ef20f1 100644 --- a/include/soc/qcom/ice.h +++ b/include/soc/qcom/ice.h @@ -30,5 +30,6 @@ int qcom_ice_import_key(struct qcom_ice *ice, const u8 *raw_key, size_t raw_key_size, u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]); struct qcom_ice *devm_of_qcom_ice_get(struct device *dev); +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up); =20 #endif /* __QCOM_ICE_H__ */ --=20 2.34.1