From nobody Sat Feb 7 10:14:59 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6501137D122; Fri, 23 Jan 2026 09:55:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769162114; cv=none; b=hjXLzIIEJ63xtwxwVRb0XzgHLTlDKux2+ncjlubSTEu4DstKT6strZvUZb3wQnQq0eDGZ+xdX51did4eLdiVxlm2xzCny70Z6PPxYzj2BO4QEYGZHzUjnQkSskX77UnhoOnWNx4K5khpo9kJqhXR6BrzMjZpQjjWvQiYGZ4iQDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769162114; c=relaxed/simple; bh=+kvLjJ8qVu0U6ba+Of8WjhJZQRzBbZ+ctK3h60Ed+rs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QZl+CMYQhj1YjNmGfWxEM9SzIDejGIOWgw7GsS2mwJM98641UcGKTp0/qzz/K8bTTS+Tgv5bPXz9zRwYkguOH1tfwwIHvyT7NQJQOSeGxA7bZ2IW9YLV2bRHTuba/hWgwlVzmyhskPoUKOKq3po7vm/wwyCwKYzwKC9Fh9bGs6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=YAtPBBM+; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="YAtPBBM+" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 83D9F1A2B19; Fri, 23 Jan 2026 09:54:58 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 591376070A; Fri, 23 Jan 2026 09:54:58 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 221C5119A87A2; Fri, 23 Jan 2026 10:54:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769162097; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=nxNNVm34hEmHicTsZJOHH60jjV020nAjZPyfjiXnMYc=; b=YAtPBBM+QE3wlhWH8hCNUJCO4FexmAUfBd4nnstDgSHCtEzIIG2A1r3MTaIl92PNK2fPBW lYqLcw/i+B8sbLrZllZfmXCeWv4CVZUHZZmZX/U5OfLjYlqOmgj06+HQmedbSatRvjQwdQ oG6ezCyYT/YBQZFbCQU25o4XXZwppsJDJkkcYvNE5GwZfvTUbyFH4f4Z6WtbG5ix1hGOvQ oSu5n1RKPfIJXo/YbeV2Mp3Pk0HQNCvUXQG5i98AtlTNvnb0aX51phv/ZdHpTOuqZJteeb FMt7cb0PBCphvZn16v5dN8hS/V0aMbRcb5cnC6+kVo7oMLVX5kB6gN6NHJb9wA== From: "Thomas Perrot (Schneider Electric)" Date: Fri, 23 Jan 2026 10:54:33 +0100 Subject: [PATCH v2 4/5] gpio: aaeon: Add GPIO driver for SRG-IMX8PL MCU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-dev-b4-aaeon-mcu-driver-v2-4-9f4c00bfb5cb@bootlin.com> References: <20260123-dev-b4-aaeon-mcu-driver-v2-0-9f4c00bfb5cb@bootlin.com> In-Reply-To: <20260123-dev-b4-aaeon-mcu-driver-v2-0-9f4c00bfb5cb@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , "Thomas Perrot (Schneider Electric)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9430; i=thomas.perrot@bootlin.com; h=from:subject:message-id; bh=+kvLjJ8qVu0U6ba+Of8WjhJZQRzBbZ+ctK3h60Ed+rs=; b=owEB7QES/pANAwAKAZ/ACwVx/grtAcsmYgBpc0Vjysw2z0spepJtXCYKgcn9o3qhoufNHSrCn R9IxigqupmJAbMEAAEKAB0WIQSHQHfGpqMKIwOoEiGfwAsFcf4K7QUCaXNFYwAKCRCfwAsFcf4K 7SG8C/9+BwcSA8w08bEDzihO5ah4C4mEa2O+BHA3nCBRKb0G3+Chb42CKHaWeALSjsCTAMahuqf WjKZKG1oRUx0QKKpi3pya02qjdQAE/s9Rv1xMJWs2tbjZsrLXCmL67mdj4R67LK0sCaQHwxf6cb D+Pei3VXALhjj+nSZtwjENStzG7WXthTwbEZ+XJUoFPfAd9gXNz2+IsLi1v+q+NfXh6aekp2VrL 2ARPh7TNjt/dtq9Ip2ppsbWvlt3ANsVwNoreANuvvTZHCY+73MiK90MP3YT19pzhlVn6yZVrAaM 3b8YEg9F7s+w42umkOSQR2f7UMiF7DgxNKxpiyIchK5TBVUAptpmLhJij5KkqPDvFxLYsg0yZax wACsYCydfStU14Q44AxEFhcmCXDqr8mmi3G/xsLm9jo94VJta4Chh/i1nwDDb/mZPoIsTT3cgex VDzj5dmDJzJ8HsjHAmIsXAunsw8g5qWLBIm3YkOQVaUp+HHFXbyO8/acaVXxPsjXHvT9Q= X-Developer-Key: i=thomas.perrot@bootlin.com; a=openpgp; fpr=874077C6A6A30A2303A812219FC00B0571FE0AED X-Last-TLS-Session-Version: TLSv1.3 Add GPIO driver for the Aaeon SRG-IMX8PL embedded controller. This driver supports 7 GPO (General Purpose Output) pins and 12 GPIO pins that can be configured as inputs or outputs. The driver implements proper state management for GPO pins (which are output-only) and full direction control for GPIO pins. During probe, all pins are reset to a known state (GPOs low, GPIOs as inputs) to prevent undefined behavior across system reboots, as the MCU does not reset GPIO states on soft reboot. Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: Thomas Perrot (Schneider Electric) Reviewed-by: Linus Walleij --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-aaeon-mcu.c | 238 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 250 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 175c1e1b28b8151580ed340207d4a6fd59aa8853..28dd964cdf69bdcaec3eb82d6df= 851a2bad47415 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -191,6 +191,7 @@ M: Thomas Perrot R: J=C3=A9r=C3=A9mie Dautheribes S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8pl-mcu.yaml +F: drivers/gpio/gpio-aaeon-mcu.c F: drivers/mfd/aaeon-mcu.c F: include/linux/mfd/aaeon-mcu.h =20 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c74da29253e810b51540684b1186e8f274066b69..6142d50b92b3d8c1fac8b0d8139= 7dc22428fbb51 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -157,6 +157,16 @@ config GPIO_74XX_MMIO 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) =20 +config GPIO_AAEON_MCU + tristate "Aaeon MCU GPIO support" + depends on MFD_AAEON_MCU + select GPIO_GENERIC + help + Select this option to enable GPIO support for the Aaeon SRG-IMX8PL + onboard MCU. This driver provides access to GPIO pins and GPO + (General Purpose Output) pins controlled by the microcontroller. + The driver handles both input and output configuration. + config GPIO_ALTERA tristate "Altera GPIO" select GPIOLIB_IRQCHIP diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 2421a8fd3733e0b06c2581262aaa9cd629f66c7d..1ba6318bc558743fbe5910966c2= c8fc3f792efe9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_104_IDI_48) +=3D gpio-104-idi-48.o obj-$(CONFIG_GPIO_104_IDIO_16) +=3D gpio-104-idio-16.o obj-$(CONFIG_GPIO_74X164) +=3D gpio-74x164.o obj-$(CONFIG_GPIO_74XX_MMIO) +=3D gpio-74xx-mmio.o +obj-$(CONFIG_GPIO_AAEON_MCU) +=3D gpio-aaeon-mcu.o obj-$(CONFIG_GPIO_ADNP) +=3D gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) +=3D gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5585) +=3D gpio-adp5585.o diff --git a/drivers/gpio/gpio-aaeon-mcu.c b/drivers/gpio/gpio-aaeon-mcu.c new file mode 100644 index 0000000000000000000000000000000000000000..533eaf3e7f82f3b9e3f50a1a631= c8e853adc1226 --- /dev/null +++ b/drivers/gpio/gpio-aaeon-mcu.c @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU GPIO driver + * + * Copyright (C) 2025 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AAEON_MCU_CONFIG_GPIO_INPUT 0x69 +#define AAEON_MCU_CONFIG_GPIO_OUTPUT 0x6F +#define AAEON_MCU_READ_GPIO 0x72 +#define AAEON_MCU_WRITE_GPIO 0x77 + +#define AAEON_MCU_CONTROL_GPO 0x6C + +#define MAX_GPIOS 12 +#define MAX_GPOS 7 + +struct aaeon_mcu_gpio { + struct gpio_chip gc; + struct device *dev; + DECLARE_BITMAP(dir_in, MAX_GPOS + MAX_GPIOS); + DECLARE_BITMAP(gpo_state, MAX_GPOS); +}; + +static int aaeon_mcu_gpio_config_input_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset) +{ + u8 cmd[3], rsp; + + cmd[0] =3D AAEON_MCU_CONFIG_GPIO_INPUT; + cmd[1] =3D offset - 7; + cmd[2] =3D 0x00; + + return aaeon_mcu_i2c_xfer(data->dev, cmd, 3, &rsp, 1); +} + +static int aaeon_mcu_gpio_direction_input(struct gpio_chip *gc, unsigned i= nt offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) { + dev_err(gc->parent, "GPIO offset (%d) must be an output GPO\n", offset); + return -EOPNOTSUPP; + } + + ret =3D aaeon_mcu_gpio_config_input_cmd(data, offset); + if (ret < 0) + return ret; + + __set_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_config_output_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset, + int value) +{ + u8 cmd[3], rsp; + int ret; + + cmd[0] =3D AAEON_MCU_CONFIG_GPIO_OUTPUT; + cmd[1] =3D offset - 7; + cmd[2] =3D 0x00; + + ret =3D aaeon_mcu_i2c_xfer(data->dev, cmd, 3, &rsp, 1); + if (ret < 0) + return ret; + + cmd[0] =3D AAEON_MCU_WRITE_GPIO; + /* cmd[1] =3D offset - 7; */ + cmd[2] =3D !!value; + + return aaeon_mcu_i2c_xfer(data->dev, cmd, 3, &rsp, 1); +} + +static int aaeon_mcu_gpio_direction_output(struct gpio_chip *gc, unsigned = int offset, int value) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) + return 0; + + ret =3D aaeon_mcu_gpio_config_output_cmd(data, offset, value); + if (ret < 0) + return ret; + + __clear_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_get_direction(struct gpio_chip *gc, unsigned int= offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + + return test_bit(offset, data->dir_in) ? + GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +static int aaeon_mcu_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + u8 cmd[3], rsp; + int ret; + + if (offset < MAX_GPOS) + return test_bit(offset, data->gpo_state); + + cmd[0] =3D AAEON_MCU_READ_GPIO; + cmd[1] =3D offset - 7; + cmd[2] =3D 0x00; + + ret =3D aaeon_mcu_i2c_xfer(data->dev, cmd, 3, &rsp, 1); + if (ret < 0) + return ret; + + return rsp; +} + +static int aaeon_mcu_gpo_set_cmd(struct aaeon_mcu_gpio *data, unsigned int= offset, int value) +{ + u8 cmd[3], rsp; + + cmd[0] =3D AAEON_MCU_CONTROL_GPO; + cmd[1] =3D offset + 1; + cmd[2] =3D !!value; + + return aaeon_mcu_i2c_xfer(data->dev, cmd, 3, &rsp, 1); +} + +static int aaeon_mcu_gpio_set_cmd(struct aaeon_mcu_gpio *data, unsigned in= t offset, int value) +{ + u8 cmd[3], rsp; + + cmd[0] =3D AAEON_MCU_WRITE_GPIO; + cmd[1] =3D offset - 7; + cmd[2] =3D !!value; + + return aaeon_mcu_i2c_xfer(data->dev, cmd, 3, &rsp, 1); +} + +static int aaeon_mcu_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + + if (offset >=3D MAX_GPOS) + return aaeon_mcu_gpio_set_cmd(data, offset, value); + + if (aaeon_mcu_gpo_set_cmd(data, offset, value) =3D=3D 0) + __assign_bit(offset, data->gpo_state, value); + + return 0; +} + +static const struct gpio_chip aaeon_mcu_chip =3D { + .label =3D "gpio-aaeon-mcu", + .owner =3D THIS_MODULE, + .get_direction =3D aaeon_mcu_gpio_get_direction, + .direction_input =3D aaeon_mcu_gpio_direction_input, + .direction_output =3D aaeon_mcu_gpio_direction_output, + .get =3D aaeon_mcu_gpio_get, + .set =3D aaeon_mcu_gpio_set, + .base =3D -1, + .ngpio =3D MAX_GPOS + MAX_GPIOS, + .can_sleep =3D true, +}; + +static void aaeon_mcu_gpio_reset(struct aaeon_mcu_gpio *data, struct devic= e *dev) +{ + unsigned int i; + int ret; + + /* Reset all GPOs */ + for (i =3D 0; i < MAX_GPOS; i++) { + ret =3D aaeon_mcu_gpo_set_cmd(data, i, 0); + if (ret < 0) + dev_warn(dev, "Failed to reset GPO %u state: %d\n", i, ret); + __clear_bit(i, data->dir_in); + } + + /* Reset all GPIOs */ + for (i =3D MAX_GPOS; i < MAX_GPOS + MAX_GPIOS; i++) { + ret =3D aaeon_mcu_gpio_config_input_cmd(data, i); + if (ret < 0) + dev_warn(dev, "Failed to reset GPIO %u state: %d\n", i, ret); + __set_bit(i, data->dir_in); + } +} + +static int aaeon_mcu_gpio_probe(struct platform_device *pdev) +{ + struct aaeon_mcu_gpio *data; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->dev =3D pdev->dev.parent; + data->gc =3D aaeon_mcu_chip; + data->gc.parent =3D data->dev; + + /* + * Reset all GPIO states to a known configuration. The MCU does not + * reset GPIO state on soft reboot, only on power cycle (hard reboot). + * Without this reset, GPIOs would retain their previous state across + * reboots, which could lead to unexpected behavior. + */ + aaeon_mcu_gpio_reset(data, &pdev->dev); + + return devm_gpiochip_add_data(&pdev->dev, &data->gc, data); +} + +static struct platform_driver aaeon_mcu_gpio_driver =3D { + .driver =3D { + .name =3D "aaeon-mcu-gpio", + }, + .probe =3D aaeon_mcu_gpio_probe, +}; + +module_platform_driver(aaeon_mcu_gpio_driver); + +MODULE_DESCRIPTION("GPIO interface for Aaeon MCU"); +MODULE_AUTHOR("J=C3=A9r=C3=A9mie Dautheribes "); +MODULE_LICENSE("GPL"); --=20 2.52.0