From nobody Mon Feb 9 02:51:06 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1F9025A33F; Fri, 23 Jan 2026 05:55:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; cv=none; b=kH+JnS+5lIBI6dqIe0A8dUcCRJ7n9y1EYIqqB9H8RruSfwOxyIT1WCCp4QVguwloWIbrSuahqZ76asFNISsdfei14p729kqcXSPFEuaUhDh6ycpNwHEaHsyA5ZgM+wmc0V9clk6av4NtOjLD34iq3aZf3nXf9aX603biRXoaEH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; c=relaxed/simple; bh=VSIZZ+c6ZCEkcYCJ5xJcHe3I7DscypgkCjD/RMtrCKk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lykvl0kCJAeLA9jpr/rPwjC8/xWki7v+kjWsT6D7v4C6KKL6BiV571QCjCw7x9tk7Xb29i5Yb+txmVcsZr6nM0scb0PitEUNCPG+PELm8/M+Awp2dXP3Ftph1h5Fe+CNtvzbbX6E4OKh9Sqjjwz8dhcmhnhSwES1T2WnJaDcqZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=syeYLa6r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="syeYLa6r" Received: by smtp.kernel.org (Postfix) with ESMTPS id E9A44C4CEF1; Fri, 23 Jan 2026 05:55:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769147706; bh=VSIZZ+c6ZCEkcYCJ5xJcHe3I7DscypgkCjD/RMtrCKk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=syeYLa6r9DZkbPSdXSH24uK/Oa5R6LR1yTrwU5+IXO3VG/J/P2by44F1eTtu/y3eC xvBl7FrKCVZcHAzMume+zs3UMGmJ3YoHHGQDw/nbFbtDMbZP1yw19HmaC9HKpTEQ+v ZTdVdUVrB5dKi/VxEBHnE6xMo9Ip7Wxc4BCCJO6thVb1yJgpHZtTAO/KCyMg9a/cjN 0EQpwfWm16/kWCbXFTVEFbrmkcHTSSOajBUs6YY1HhHcrtQVYoX6AN3DK2PfgFQ8bi pehNBezS+pzRGUpaL3s5uVhIP6Kh3YDRctMl8R44FPLAJDuunaFB74L55/i1NtW1uv A8mlCoMrpwqsQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2011D6CFD7; Fri, 23 Jan 2026 05:55:05 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 23 Jan 2026 13:54:55 +0800 Subject: [PATCH v6 1/5] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-a5-clk-v6-1-6d3bbf0ec1ea@amlogic.com> References: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> In-Reply-To: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769147703; l=2048; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=4kspprQnq+nsGEHN4lrxioeMwroBsv/rJjwAgDy0myA=; b=PLqruzjeto1unAK+G8UfMAbBeKVb6kYt3WyFxVS/NQLuECtYnkwNyN5n+eXBV8Va6ND2mL9dR lm/2TqlH16DDYljERzZabByDrtq/c+UIxiwmEDpjFZz5C+k0oUXmrFT X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the SCMI clock controller dt-bindings for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-= bindings/clock/amlogic,a5-scmi-clkc.h new file mode 100644 index 000000000000..1bf027d0110a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef __AMLOGIC_A5_SCMI_CLKC_H +#define __AMLOGIC_A5_SCMI_CLKC_H + +#define CLKID_OSC 0 +#define CLKID_SYS_CLK 1 +#define CLKID_AXI_CLK 2 +#define CLKID_CPU_CLK 3 +#define CLKID_DSU_CLK 4 +#define CLKID_GP1_PLL 5 +#define CLKID_FIXED_PLL_DCO 6 +#define CLKID_FIXED_PLL 7 +#define CLKID_ACLKM 8 +#define CLKID_SYS_PLL_DIV16 9 +#define CLKID_CPU_CLK_DIV16 10 +#define CLKID_FCLK_50M_PREDIV 11 +#define CLKID_FCLK_50M_DIV 12 +#define CLKID_FCLK_50M 13 +#define CLKID_FCLK_DIV2_DIV 14 +#define CLKID_FCLK_DIV2 15 +#define CLKID_FCLK_DIV2P5_DIV 16 +#define CLKID_FCLK_DIV2P5 17 +#define CLKID_FCLK_DIV3_DIV 18 +#define CLKID_FCLK_DIV3 19 +#define CLKID_FCLK_DIV4_DIV 20 +#define CLKID_FCLK_DIV4 21 +#define CLKID_FCLK_DIV5_DIV 22 +#define CLKID_FCLK_DIV5 23 +#define CLKID_FCLK_DIV7_DIV 24 +#define CLKID_FCLK_DIV7 25 +#define CLKID_SYS_MMC_PCLK 26 +#define CLKID_SYS_CPU_CTRL 27 +#define CLKID_SYS_IRQ_CTRL 28 +#define CLKID_SYS_GIC 29 +#define CLKID_SYS_BIG_NIC 30 +#define CLKID_AXI_SYS_NIC 31 +#define CLKID_AXI_CPU_DMC 32 + +#endif /* __AMLOGIC_A5_SCMI_CLKC_H */ --=20 2.42.0