From nobody Sun Feb 8 04:33:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1F9025A33F; Fri, 23 Jan 2026 05:55:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; cv=none; b=kH+JnS+5lIBI6dqIe0A8dUcCRJ7n9y1EYIqqB9H8RruSfwOxyIT1WCCp4QVguwloWIbrSuahqZ76asFNISsdfei14p729kqcXSPFEuaUhDh6ycpNwHEaHsyA5ZgM+wmc0V9clk6av4NtOjLD34iq3aZf3nXf9aX603biRXoaEH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; c=relaxed/simple; bh=VSIZZ+c6ZCEkcYCJ5xJcHe3I7DscypgkCjD/RMtrCKk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lykvl0kCJAeLA9jpr/rPwjC8/xWki7v+kjWsT6D7v4C6KKL6BiV571QCjCw7x9tk7Xb29i5Yb+txmVcsZr6nM0scb0PitEUNCPG+PELm8/M+Awp2dXP3Ftph1h5Fe+CNtvzbbX6E4OKh9Sqjjwz8dhcmhnhSwES1T2WnJaDcqZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=syeYLa6r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="syeYLa6r" Received: by smtp.kernel.org (Postfix) with ESMTPS id E9A44C4CEF1; Fri, 23 Jan 2026 05:55:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769147706; bh=VSIZZ+c6ZCEkcYCJ5xJcHe3I7DscypgkCjD/RMtrCKk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=syeYLa6r9DZkbPSdXSH24uK/Oa5R6LR1yTrwU5+IXO3VG/J/P2by44F1eTtu/y3eC xvBl7FrKCVZcHAzMume+zs3UMGmJ3YoHHGQDw/nbFbtDMbZP1yw19HmaC9HKpTEQ+v ZTdVdUVrB5dKi/VxEBHnE6xMo9Ip7Wxc4BCCJO6thVb1yJgpHZtTAO/KCyMg9a/cjN 0EQpwfWm16/kWCbXFTVEFbrmkcHTSSOajBUs6YY1HhHcrtQVYoX6AN3DK2PfgFQ8bi pehNBezS+pzRGUpaL3s5uVhIP6Kh3YDRctMl8R44FPLAJDuunaFB74L55/i1NtW1uv A8mlCoMrpwqsQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2011D6CFD7; Fri, 23 Jan 2026 05:55:05 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 23 Jan 2026 13:54:55 +0800 Subject: [PATCH v6 1/5] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-a5-clk-v6-1-6d3bbf0ec1ea@amlogic.com> References: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> In-Reply-To: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769147703; l=2048; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=4kspprQnq+nsGEHN4lrxioeMwroBsv/rJjwAgDy0myA=; b=PLqruzjeto1unAK+G8UfMAbBeKVb6kYt3WyFxVS/NQLuECtYnkwNyN5n+eXBV8Va6ND2mL9dR lm/2TqlH16DDYljERzZabByDrtq/c+UIxiwmEDpjFZz5C+k0oUXmrFT X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the SCMI clock controller dt-bindings for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-= bindings/clock/amlogic,a5-scmi-clkc.h new file mode 100644 index 000000000000..1bf027d0110a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef __AMLOGIC_A5_SCMI_CLKC_H +#define __AMLOGIC_A5_SCMI_CLKC_H + +#define CLKID_OSC 0 +#define CLKID_SYS_CLK 1 +#define CLKID_AXI_CLK 2 +#define CLKID_CPU_CLK 3 +#define CLKID_DSU_CLK 4 +#define CLKID_GP1_PLL 5 +#define CLKID_FIXED_PLL_DCO 6 +#define CLKID_FIXED_PLL 7 +#define CLKID_ACLKM 8 +#define CLKID_SYS_PLL_DIV16 9 +#define CLKID_CPU_CLK_DIV16 10 +#define CLKID_FCLK_50M_PREDIV 11 +#define CLKID_FCLK_50M_DIV 12 +#define CLKID_FCLK_50M 13 +#define CLKID_FCLK_DIV2_DIV 14 +#define CLKID_FCLK_DIV2 15 +#define CLKID_FCLK_DIV2P5_DIV 16 +#define CLKID_FCLK_DIV2P5 17 +#define CLKID_FCLK_DIV3_DIV 18 +#define CLKID_FCLK_DIV3 19 +#define CLKID_FCLK_DIV4_DIV 20 +#define CLKID_FCLK_DIV4 21 +#define CLKID_FCLK_DIV5_DIV 22 +#define CLKID_FCLK_DIV5 23 +#define CLKID_FCLK_DIV7_DIV 24 +#define CLKID_FCLK_DIV7 25 +#define CLKID_SYS_MMC_PCLK 26 +#define CLKID_SYS_CPU_CTRL 27 +#define CLKID_SYS_IRQ_CTRL 28 +#define CLKID_SYS_GIC 29 +#define CLKID_SYS_BIG_NIC 30 +#define CLKID_AXI_SYS_NIC 31 +#define CLKID_AXI_CPU_DMC 32 + +#endif /* __AMLOGIC_A5_SCMI_CLKC_H */ --=20 2.42.0 From nobody Sun Feb 8 04:33:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F62139A815; Fri, 23 Jan 2026 05:55:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; cv=none; b=XmI3OkO7WSTe721vL9+hu6FrnY3WEp/3y1eaL6DNfCqg9ja3Ixjz4qZIFd3c1Gl+OpZPx5WnpqyxNprst2pPeuHfvHgfxnhjT0QU2r4t6whnQaXIS4bVoRcUx2R/ihP7HBb0F6aQWCih+XuN142F60w2qfpG1FdsF2Fzx4LkhWQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; c=relaxed/simple; bh=GDS2hOEC3ZDMsbfoCk7m1oWy+PAW91PnnU7hk34o6d0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PSbu/c5cDmAKhWzU5nMMBO/yE/eb6TR0E8xqhe4aQuy5tyuklJt9t8pH6VT9SNSuz0DPbOZsnceoNLVHaNY/va7KtY7tfKSUdgk24BnkVBGMe3+pG2KhRrzAKwKRAH7pjKRgKSM6TyPJjISnV6QhJXKph4VmIwdFgdTLry7Eu70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lUPfANag; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lUPfANag" Received: by smtp.kernel.org (Postfix) with ESMTPS id EFF28C2BC86; Fri, 23 Jan 2026 05:55:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769147706; bh=GDS2hOEC3ZDMsbfoCk7m1oWy+PAW91PnnU7hk34o6d0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lUPfANag5v5XJz3BTzz7+i+TFyaMYz0jgg0LQHxL/7jjLEuX/YmVSOQemAAH6ppM2 Pb8m+ub7g5lyBAvc3OocTk/U8L+5nW3nAOdY2Wx7arkrnhJb4H01BOc0uM5T6PH/6B xnekjRA4lCv3Oe/jAzt6c73UjYfC+6tKamgoFxKdjckkZN3YzLS27n98+qp7etQ0Qz w+47H5IutHHXEnkOpYML5Ej9t4q6/b0lqWBhzBuS+PzIfmDpozmKb7iHO0tmS5guCr HIRMMx/jhgKWb8SkEO/e3c5tONOC82GxBtosT9u+GfxIlOKiikZ32pbHiALPB/TL0G BfkJCEyMMSeUQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4C39D6CFD8; Fri, 23 Jan 2026 05:55:05 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 23 Jan 2026 13:54:56 +0800 Subject: [PATCH v6 2/5] dt-bindings: clock: Add Amlogic A5 PLL clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-a5-clk-v6-2-6d3bbf0ec1ea@amlogic.com> References: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> In-Reply-To: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769147703; l=3306; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=L2WtYBPXP83bh/la2DnEiOjTXuQi8+YFfWCWfb93CxI=; b=vuuPPxdyvw3/zMxfvz11tmF9q5N5+rflhGVlRniW+YnGvMOINyZN6wQr5joJJSjZqBj2EOHz5 q1BGC4vd/v5ATT0aYIqeXQn9ZgyUX7bAHqgVBF9X7HVgdpg2YUP62Of X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller dt-bindings for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++++++++++++++++++= ++++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +++++++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml new file mode 100644 index 000000000000..d74570a90926 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series PLL Clock Controller + +maintainers: + - Chuan Liu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a5-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input oscillator + - description: input fix pll dco + - description: input fix pll + + clock-names: + items: + - const: xtal + - const: fix_dco + - const: fix + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8000 { + compatible =3D "amlogic,a5-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_FIXED_PLL_DCO>, + <&scmi_clk CLKID_FIXED_PLL>; + clock-names =3D "xtal", + "fix_dco", + "fix"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-pll-clkc.h b/include/dt-b= indings/clock/amlogic,a5-pll-clkc.h new file mode 100644 index 000000000000..a74c448a8d8a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H + +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 +#define CLKID_GP0_PLL_DCO 9 +#define CLKID_GP0_PLL 10 +#define CLKID_HIFI_PLL_DCO 11 +#define CLKID_HIFI_PLL 12 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H */ --=20 2.42.0 From nobody Sun Feb 8 04:33:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A207839CEE8; Fri, 23 Jan 2026 05:55:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; cv=none; b=W9raG5tGV4yT4jx6jufSsXqpfqSEXHRmyLhP2r0/tUl5AkDrNnt8ATEP+6ass+u0ctEMHikkrP5Ai8zQBObg2u+CzL4h091UDSdVO+6qqpURhdSMHQyGEtF385wXvixxRmZnB2ay7gMm16xKAlOR6KfzheMKMTkuWWqEX/v0BOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147707; c=relaxed/simple; bh=kj2bz78IILEIstewiqZHT9qts3FHFYfsPylDGJjB5eM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f38OY2g6ejieSZsm/7GcAL6xVWoy0DQmWAMx1TGNM1IrDti16AdQPbOg0SLnvRYqvx4vT/XzNpDKn6iKCLsiSryuc8qf+8uKA+tphBUH9xBL3kRPgbvsVpA7sazc1b3oe+9ziQsJT3mt+T6el4lRPf7lW+MkQIJ3tU+msGEL0Wo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NueTdGwU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NueTdGwU" Received: by smtp.kernel.org (Postfix) with ESMTPS id 10C56C19424; Fri, 23 Jan 2026 05:55:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769147706; bh=kj2bz78IILEIstewiqZHT9qts3FHFYfsPylDGJjB5eM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NueTdGwUgDgNvBbI+D6L9aszaqPHSsjvsEzC5TzAflDWrORIB3sHhd/JOIiEQWEwT IGnuL9P/7s6ho2BGgJy6e+N/PJEL9fSf1UJTLGv+iy1E70BZs2U0q+sSxU89gqP/JF nxqoJPWCRyE8IOpXtCyOe1dIhf/+hNHD8U4udLe6X7chBKLxACmzpZRbpyooEeVJJo uEh97qaBTVy6Z0C8GjFmZSaoSMmyEYbAnTeBIJMDVhcPHiMx4/rJNABb4iuacgHaQn jJ6EDCDEW92RaqX8d5uYGTOR2CDkzuTShYHMobLS5tESASWB9bAryQFzq0YQ021q03 +ZF6CRPOVdxDg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0296DD6CFD5; Fri, 23 Jan 2026 05:55:06 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 23 Jan 2026 13:54:57 +0800 Subject: [PATCH v6 3/5] dt-bindings: clock: Add Amlogic A5 peripherals clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-a5-clk-v6-3-6d3bbf0ec1ea@amlogic.com> References: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> In-Reply-To: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769147703; l=9596; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=hHd35yALxxbdvq1KX85En5uKgtIsw1h8WtM1CzHm1rY=; b=DbxUPPY0xG64mCtB7Q3uyoK6YWH4F4kVf8wRZ6YhG9aDYx8luM3smG5q9KchEqkhlLaFr3Lh3 HfoahJd5u0dDhvHsOXQE6anhacS/FB0ttwwjz9jptnOHtoTpjH8uBYo X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller dt-bindings for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- .../clock/amlogic,a5-peripherals-clkc.yaml | 134 +++++++++++++++++= ++++ .../clock/amlogic,a5-peripherals-clkc.h | 132 +++++++++++++++++= +++ 2 files changed, 266 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals= -clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals= -clkc.yaml new file mode 100644 index 000000000000..88d71d9a72ea --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.y= aml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series Peripheral Clock Controller + +maintainers: + - Xianwei Zhao + - Chuan Liu + +properties: + compatible: + const: amlogic,a5-peripherals-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 18 + items: + - description: input oscillator + - description: input oscillators multiplexer + - description: input fix pll + - description: input fclk div 2 + - description: input fclk div 2p5 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input mpll2 + - description: input mpll3 + - description: input gp0 pll + - description: input gp1 pll + - description: input hifi pll + - description: input sys clk + - description: input axi clk + - description: input sys pll div 16 + - description: input cpu clk div 16 + - description: input pad clock for rtc clk (optional) + - description: input ddr pll (optional) + - description: input source from clk-measure (optional) + - description: input rtc pll (optional) + + clock-names: + minItems: 18 + items: + - const: xtal + - const: oscin + - const: fix + - const: fdiv2 + - const: fdiv2p5 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: mpll2 + - const: mpll3 + - const: gp0 + - const: gp1 + - const: hifi + - const: sysclk + - const: axiclk + - const: sysplldiv16 + - const: cpudiv16 + - const: pad_osc + - const: ddr + - const: clkmsr + - const: rtc + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@0 { + compatible =3D "amlogic,a5-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x224>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_OSC>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_GP0_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HIFI_PLL>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_AXI_CLK>, + <&scmi_clk CLKID_SYS_PLL_DIV16>, + <&scmi_clk CLKID_CPU_CLK_DIV16>; + clock-names =3D "xtal", + "oscin", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "mpll2", + "mpll3", + "gp0", + "gp1", + "hifi", + "sysclk", + "axiclk", + "sysplldiv16", + "cpudiv16"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,a5-peripherals-clkc.h new file mode 100644 index 000000000000..b8a68b7f29dc --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H + +#define CLKID_RTC_DUALDIV_CLKIN 0 +#define CLKID_RTC_DUALDIV 1 +#define CLKID_RTC_DUALDIV_SEL 2 +#define CLKID_RTC_DUALDIV_CLKOUT 3 +#define CLKID_RTC_CLK 4 +#define CLKID_SYS_RESET_CTRL 5 +#define CLKID_SYS_PWR_CTRL 6 +#define CLKID_SYS_PAD_CTRL 7 +#define CLKID_SYS_CTRL 8 +#define CLKID_SYS_TS_PLL 9 +#define CLKID_SYS_DEV_ARB 10 +#define CLKID_SYS_MAILBOX 11 +#define CLKID_SYS_JTAG_CTRL 12 +#define CLKID_SYS_IR_CTRL 13 +#define CLKID_SYS_MSR_CLK 14 +#define CLKID_SYS_ROM 15 +#define CLKID_SYS_CPU_ARB 16 +#define CLKID_SYS_RSA 17 +#define CLKID_SYS_SARADC 18 +#define CLKID_SYS_STARTUP 19 +#define CLKID_SYS_SECURE 20 +#define CLKID_SYS_SPIFC 21 +#define CLKID_SYS_DSPA 22 +#define CLKID_SYS_NNA 23 +#define CLKID_SYS_ETH_MAC 24 +#define CLKID_SYS_RAMA 25 +#define CLKID_SYS_RAMB 26 +#define CLKID_SYS_AUDIO_TOP 27 +#define CLKID_SYS_AUDIO_VAD 28 +#define CLKID_SYS_USB 29 +#define CLKID_SYS_SD_EMMC_A 30 +#define CLKID_SYS_SD_EMMC_C 31 +#define CLKID_SYS_PWM_AB 32 +#define CLKID_SYS_PWM_CD 33 +#define CLKID_SYS_PWM_EF 34 +#define CLKID_SYS_PWM_GH 35 +#define CLKID_SYS_SPICC_1 36 +#define CLKID_SYS_SPICC_0 37 +#define CLKID_SYS_UART_A 38 +#define CLKID_SYS_UART_B 39 +#define CLKID_SYS_UART_C 40 +#define CLKID_SYS_UART_D 41 +#define CLKID_SYS_UART_E 42 +#define CLKID_SYS_I2C_M_A 43 +#define CLKID_SYS_I2C_M_B 44 +#define CLKID_SYS_I2C_M_C 45 +#define CLKID_SYS_I2C_M_D 46 +#define CLKID_SYS_RTC 47 +#define CLKID_AXI_AUDIO_VAD 48 +#define CLKID_AXI_AUDIO_TOP 49 +#define CLKID_AXI_RAMB 50 +#define CLKID_AXI_RAMA 51 +#define CLKID_AXI_NNA 52 +#define CLKID_AXI_DEV1_DMC 53 +#define CLKID_AXI_DEV0_DMC 54 +#define CLKID_AXI_DSP_DMC 55 +#define CLKID_12_24M_IN 56 +#define CLKID_12M_24M 57 +#define CLKID_FCLK_25M_DIV 58 +#define CLKID_FCLK_25M 59 +#define CLKID_GEN_SEL 60 +#define CLKID_GEN_DIV 61 +#define CLKID_GEN 62 +#define CLKID_SARADC_SEL 63 +#define CLKID_SARADC_DIV 64 +#define CLKID_SARADC 65 +#define CLKID_PWM_A_SEL 66 +#define CLKID_PWM_A_DIV 67 +#define CLKID_PWM_A 68 +#define CLKID_PWM_B_SEL 69 +#define CLKID_PWM_B_DIV 70 +#define CLKID_PWM_B 71 +#define CLKID_PWM_C_SEL 72 +#define CLKID_PWM_C_DIV 73 +#define CLKID_PWM_C 74 +#define CLKID_PWM_D_SEL 75 +#define CLKID_PWM_D_DIV 76 +#define CLKID_PWM_D 77 +#define CLKID_PWM_E_SEL 78 +#define CLKID_PWM_E_DIV 79 +#define CLKID_PWM_E 80 +#define CLKID_PWM_F_SEL 81 +#define CLKID_PWM_F_DIV 82 +#define CLKID_PWM_F 83 +#define CLKID_PWM_G_SEL 84 +#define CLKID_PWM_G_DIV 85 +#define CLKID_PWM_G 86 +#define CLKID_PWM_H_SEL 87 +#define CLKID_PWM_H_DIV 88 +#define CLKID_PWM_H 89 +#define CLKID_SPICC_0_SEL 90 +#define CLKID_SPICC_0_DIV 91 +#define CLKID_SPICC_0 92 +#define CLKID_SPICC_1_SEL 93 +#define CLKID_SPICC_1_DIV 94 +#define CLKID_SPICC_1 95 +#define CLKID_SD_EMMC_A_SEL 96 +#define CLKID_SD_EMMC_A_DIV 97 +#define CLKID_SD_EMMC_A 98 +#define CLKID_SD_EMMC_C_SEL 99 +#define CLKID_SD_EMMC_C_DIV 100 +#define CLKID_SD_EMMC_C 101 +#define CLKID_TS_DIV 102 +#define CLKID_TS 103 +#define CLKID_ETH_125M_DIV 104 +#define CLKID_ETH_125M 105 +#define CLKID_ETH_RMII_DIV 106 +#define CLKID_ETH_RMII 107 +#define CLKID_DSPA_0_SEL 108 +#define CLKID_DSPA_0_DIV 109 +#define CLKID_DSPA_0 110 +#define CLKID_DSPA_1_SEL 111 +#define CLKID_DSPA_1_DIV 112 +#define CLKID_DSPA_1 113 +#define CLKID_DSPA 114 +#define CLKID_NNA_CORE_SEL 115 +#define CLKID_NNA_CORE_DIV 116 +#define CLKID_NNA_CORE 117 +#define CLKID_NNA_AXI_SEL 118 +#define CLKID_NNA_AXI_DIV 119 +#define CLKID_NNA_AXI 120 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H */ --=20 2.42.0 From nobody Sun Feb 8 04:33:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F53A399A79; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-a5-clk-v6-4-6d3bbf0ec1ea@amlogic.com> References: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> In-Reply-To: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769147703; l=13618; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=6qot9jHTh2G8KC0NAvSqOCQ3iNxhCRriWk4X3hP70qQ=; b=qeuoYFzd+JglH+iKd4LNwf6BNfOjODz8BHxw+b+sf3NIjqVovibxyk3hyt4xIYZ9YjMkM6YHP VI0V3pcF7IsC1o3Xo/17CooIZaYUC9taRnpNcIbQqEBfr1uZUzu2J5U X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller driver for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- drivers/clk/meson/Kconfig | 14 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a5-pll.c | 478 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 493 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 71481607a6d5..b627821da081 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -132,6 +132,20 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_A5_PLL + tristate "Amlogic A5 PLL clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + select COMMON_CLK_MESON_MPLL + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic A113X2 device, AKA A5. + Say Y if you want the board to work, because PLLs are the parent + of most peripherals. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index c6998e752c68..a074aa7e187f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_A5_PLL) +=3D a5-pll.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a5-pll.c b/drivers/clk/meson/a5-pll.c new file mode 100644 index 000000000000..fd9a0e92ba1e --- /dev/null +++ b/drivers/clk/meson/a5-pll.c @@ -0,0 +1,478 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A5 PLL Controller Driver + * + * Copyright (c) 2024-2025 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-mpll.h" +#include "meson-clkc-utils.h" +#include + +#define GP0PLL_CTRL0 0x80 +#define GP0PLL_CTRL1 0x84 +#define GP0PLL_CTRL2 0x88 +#define GP0PLL_CTRL3 0x8c +#define GP0PLL_CTRL4 0x90 +#define GP0PLL_CTRL5 0x94 +#define GP0PLL_CTRL6 0x98 + +#define HIFIPLL_CTRL0 0x100 +#define HIFIPLL_CTRL1 0x104 +#define HIFIPLL_CTRL2 0x108 +#define HIFIPLL_CTRL3 0x10c +#define HIFIPLL_CTRL4 0x110 +#define HIFIPLL_CTRL5 0x114 +#define HIFIPLL_CTRL6 0x118 + +#define MPLL_CTRL0 0x180 +#define MPLL_CTRL1 0x184 +#define MPLL_CTRL2 0x188 +#define MPLL_CTRL3 0x18c +#define MPLL_CTRL4 0x190 +#define MPLL_CTRL5 0x194 +#define MPLL_CTRL6 0x198 +#define MPLL_CTRL7 0x19c +#define MPLL_CTRL8 0x1a0 + +static struct clk_fixed_factor a5_mpll_prediv =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll_prediv", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix_dco" + }, + .num_parents =3D 1, + }, +}; + +static const struct reg_sequence a5_mpll0_init_regs[] =3D { + { .reg =3D MPLL_CTRL2, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll0_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll0_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll0_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL1, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll0_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll1_init_regs[] =3D { + { .reg =3D MPLL_CTRL4, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll1_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll1_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll1_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll1_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL3, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "a5_mpll1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll1_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll2_init_regs[] =3D { + { .reg =3D MPLL_CTRL6, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll2_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll2_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll2_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL5, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll2_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll3_init_regs[] =3D { + { .reg =3D MPLL_CTRL8, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll3_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll3_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll3_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL7, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll3_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_gp0_init_regs[] =3D { + { .reg =3D GP0PLL_CTRL3, .def =3D 0x6a295c00 }, + { .reg =3D GP0PLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D GP0PLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D GP0PLL_CTRL6, .def =3D 0x54540000 } +}; + +static const struct pll_mult_range a5_gp0_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap a5_gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D GP0PLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &a5_gp0_pll_mult_range, + .init_regs =3D a5_gp0_init_regs, + .init_count =3D ARRAY_SIZE(a5_gp0_init_regs), + .frac_max =3D 100000, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +/* The maximum frequency divider supports is 32, not 128(2^7) */ +static const struct clk_div_table a5_gp0_pll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { 5, 32 }, + { /* sentinel */ } +}; + +static struct clk_regmap a5_gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + .table =3D a5_gp0_pll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_hifi_init_regs[] =3D { + { .reg =3D HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, + { .reg =3D HIFIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D HIFIPLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D HIFIPLL_CTRL6, .def =3D 0x56540000 } +}; + +static const struct pll_mult_range a5_hifi_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap a5_hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &a5_hifi_pll_mult_range, + .init_regs =3D a5_hifi_init_regs, + .init_count =3D ARRAY_SIZE(a5_hifi_init_regs), + .frac_max =3D 100000, + .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *a5_pll_hw_clks[] =3D { + [CLKID_MPLL_PREDIV] =3D &a5_mpll_prediv.hw, + [CLKID_MPLL0_DIV] =3D &a5_mpll0_div.hw, + [CLKID_MPLL0] =3D &a5_mpll0.hw, + [CLKID_MPLL1_DIV] =3D &a5_mpll1_div.hw, + [CLKID_MPLL1] =3D &a5_mpll1.hw, + [CLKID_MPLL2_DIV] =3D &a5_mpll2_div.hw, + [CLKID_MPLL2] =3D &a5_mpll2.hw, + [CLKID_MPLL3_DIV] =3D &a5_mpll3_div.hw, + [CLKID_MPLL3] =3D &a5_mpll3.hw, + [CLKID_GP0_PLL_DCO] =3D &a5_gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &a5_gp0_pll.hw, + [CLKID_HIFI_PLL_DCO] =3D &a5_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &a5_hifi_pll.hw +}; + +static const struct meson_clkc_data a5_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D a5_pll_hw_clks, + .num =3D ARRAY_SIZE(a5_pll_hw_clks), + }, +}; + +static const struct of_device_id a5_pll_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a5-pll-clkc", + .data =3D &a5_pll_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a5_pll_clkc_match_table); + +static struct platform_driver a5_pll_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a5-pll-clkc", + .of_match_table =3D a5_pll_clkc_match_table, + }, +}; +module_platform_driver(a5_pll_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A5 PLL Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0 From nobody Sun Feb 8 04:33:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 832EC9443; Fri, 23 Jan 2026 05:55:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147709; cv=none; b=CPDP0OcN4S6/g2hnLf2dx0x8p28DXXq7MNXDVyK8xXzcKvJd/Z++FhHNqb4oEtpisKLt9idA1lGKP6njw5xhARxmctepRgDMemxaSAeblVzLlvFSOAt89tfDuyItP0jTqQk16duNayQHKEXOZSDl7KGbV+x221JmUiPOxtjegwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769147709; c=relaxed/simple; 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Fri, 23 Jan 2026 05:55:06 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 23 Jan 2026 13:54:59 +0800 Subject: [PATCH v6 5/5] clk: amlogic: Add A5 clock peripherals controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260123-a5-clk-v6-5-6d3bbf0ec1ea@amlogic.com> References: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> In-Reply-To: <20260123-a5-clk-v6-0-6d3bbf0ec1ea@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769147703; l=27708; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=btQNZ0SDPLLNtCoY4NEj66pAI4k0z9WH2eRH5ktFKY8=; b=4k/xPIWQ8LfMA5jSOpsrTyePBMI8umYIZ7ew+VDUgWHq7O8KzFgibV84zH5/jvV1Sz7n08l3i eyvgGC+jT1KAvXztU4ICGtsPyYql4mDn7ySAcu4vnfo4ajB6boQOGVJ X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller driver for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a5-peripherals.c | 781 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 795 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index b627821da081..5576f351ef8c 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -146,6 +146,19 @@ config COMMON_CLK_A5_PLL Say Y if you want the board to work, because PLLs are the parent of most peripherals. =20 +config COMMON_CLK_A5_PERIPHERALS + tristate "Amlogic A5 peripherals clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + imply COMMON_CLK_A5_PLL + help + Support for the Peripherals clock controller on Amlogic A113X2 device, + AKA A5. Say Y if you want the peripherals clock to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index a074aa7e187f..0432027d7e2e 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o obj-$(CONFIG_COMMON_CLK_A5_PLL) +=3D a5-pll.o +obj-$(CONFIG_COMMON_CLK_A5_PERIPHERALS) +=3D a5-peripherals.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a5-peripherals.c b/drivers/clk/meson/a5-peri= pherals.c new file mode 100644 index 000000000000..de289a092484 --- /dev/null +++ b/drivers/clk/meson/a5-peripherals.c @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A5 Peripherals Clock Controller Driver + * + * Copyright (c) 2024-2026 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-dualdiv.h" +#include "meson-clkc-utils.h" +#include + +#define RTC_BY_OSCIN_CTRL0 0x8 +#define RTC_BY_OSCIN_CTRL1 0xc +#define RTC_CTRL 0x10 +#define SYS_CLK_EN0_REG0 0x44 +#define SYS_CLK_EN0_REG1 0x48 +#define DSPA_CLK_CTRL0 0x9c +#define CLK12_24_CTRL 0xa8 +#define AXI_CLK_EN0 0xac +#define TS_CLK_CTRL 0x158 +#define ETH_CLK_CTRL 0x164 +#define NAND_CLK_CTRL 0x168 +#define SD_EMMC_CLK_CTRL 0x16c +#define SPICC_CLK_CTRL 0x174 +#define GEN_CLK_CTRL 0x178 +#define SAR_CLK_CTRL0 0x17c +#define PWM_CLK_AB_CTRL 0x180 +#define PWM_CLK_CD_CTRL 0x184 +#define PWM_CLK_EF_CTRL 0x188 +#define PWM_CLK_GH_CTRL 0x18c +#define NNA_CLK_CNTL 0x220 + +static struct clk_regmap a5_rtc_dualdiv_clkin =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkin", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param a5_rtc_dualdiv_table[] =3D { + { 733, 732, 8, 11, 1 }, + { /* sentinel */ } +}; + +static struct clk_regmap a5_rtc_dualdiv =3D { + .data =3D &(struct meson_clk_dualdiv_data) { + .n1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D a5_rtc_dualdiv_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_rtc_dualdiv_clkin.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data a5_rtc_dualdiv_parents[] =3D { + { .hw =3D &a5_rtc_dualdiv.hw }, + { .hw =3D &a5_rtc_dualdiv_clkin.hw } +}; + +static struct clk_regmap a5_rtc_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_rtc_dualdiv_parents, + .num_parents =3D ARRAY_SIZE(a5_rtc_dualdiv_parents), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_rtc_dualdiv_clkout =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_dualdiv_clkout", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_rtc_dualdiv_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data a5_rtc_clk_parents[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_dualdiv_clkout.hw }, + { .fw_name =3D "pad_osc" } +}; + +static struct clk_regmap a5_rtc_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_rtc_clk_parents, + .num_parents =3D ARRAY_SIZE(a5_rtc_clk_parents), + .flags =3D CLK_SET_RATE_NO_REPARENT, + }, +}; + +static const struct clk_parent_data a5_sys_pclk_parents =3D { .fw_name =3D= "sysclk" }; + +#define A5_SYS_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(a5_##_name, _reg, _bit, &a5_sys_pclk_parents, _flags) + +static A5_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); +static A5_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); +static A5_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0); +static A5_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0); +static A5_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0); + +/* + * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that + * access the AXI bus. + */ +static A5_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0); +static A5_SYS_PCLK(sys_mailbox, SYS_CLK_EN0_REG0, 10, 0); +static A5_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0); +static A5_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0); +static A5_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0); +static A5_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0); +static A5_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0); +static A5_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0); +static A5_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG0, 20, 0); +static A5_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0); +static A5_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0); +static A5_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0); +static A5_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG0, 24, 0); +static A5_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 25, 0); +static A5_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0); +static A5_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0); +static A5_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0); +static A5_SYS_PCLK(sys_audio_top, SYS_CLK_EN0_REG1, 0, 0); +static A5_SYS_PCLK(sys_audio_vad, SYS_CLK_EN0_REG1, 1, 0); +static A5_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0); +static A5_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0); +static A5_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0); +static A5_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0); +static A5_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0); +static A5_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0); +static A5_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0); +static A5_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0); +static A5_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0); +static A5_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0); +static A5_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0); +static A5_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0); +static A5_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0); +static A5_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0); +static A5_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0); +static A5_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0); +static A5_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0); +static A5_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0); +static A5_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0); + +static const struct clk_parent_data a5_axi_clk_parents =3D { .fw_name =3D = "axiclk" }; + +#define A5_AXI_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(a5_##_name, _reg, _bit, &a5_axi_clk_parents, _flags) + +static A5_AXI_PCLK(axi_audio_vad, AXI_CLK_EN0, 0, 0); +static A5_AXI_PCLK(axi_audio_top, AXI_CLK_EN0, 1, 0); +static A5_AXI_PCLK(axi_ramb, AXI_CLK_EN0, 5, 0); +static A5_AXI_PCLK(axi_rama, AXI_CLK_EN0, 6, 0); +static A5_AXI_PCLK(axi_nna, AXI_CLK_EN0, 12, 0); + +/* + * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO, + * sec_top, USB, Audio) to access the AXI bus of the DDR. + */ +static A5_AXI_PCLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0); + +/* + * NOTE: axi_dev0_dmc provides the clock for the peripherals(ETH and SPICC) + * to access the AXI bus of the DDR. + */ +static A5_AXI_PCLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0); +static A5_AXI_PCLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0); + +static struct clk_regmap a5_clk_12_24m_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_clk_12_24m =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_clk_12_24m_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_fclk_25m_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_fclk_25m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_fclk_25m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Channel 4 5 8 9 10 11 13 14 15 16 18 are not connected. + * + * gp1 is designed for DSU (DynamIQ Shared Unit) alone. It cannot be chang= ed + * arbitrarily. gp1 is read-only in the kernel and is only open for debug + * purposes. + */ +static u32 a5_gen_parents_val_table[] =3D {0, 1, 2, 3, 6, 7, 12, 17, 19, 2= 0, 21, + 22, 23, 24, 25, 26, 27, 28}; + +static const struct clk_parent_data a5_gen_parents[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_clk.hw }, + { .fw_name =3D "sysplldiv16" }, + { .fw_name =3D "ddr" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "clkmsr" }, + { .fw_name =3D "cpudiv16" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "mpll0" }, + { .fw_name =3D "mpll1" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" } +}; + +static struct clk_regmap a5_gen_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D GEN_CLK_CTRL, + .mask =3D 0x1f, + .shift =3D 12, + .table =3D a5_gen_parents_val_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D a5_gen_parents, + .num_parents =3D ARRAY_SIZE(a5_gen_parents), + }, +}; + +static struct clk_regmap a5_gen_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GEN_CLK_CTRL, + .shift =3D 0, + .width =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gen_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a5_gen =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D GEN_CLK_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gen_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A5_COMP_SEL(_name, _reg, _shift, _mask, _pdata, _table) \ + MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0) + +#define A5_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(a5_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define A5_COMP_GATE(_name, _reg, _bit, _iflags) \ + MESON_COMP_GATE(a5_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags)) + +static const struct clk_parent_data a5_saradc_parents[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" } +}; + +static A5_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x3, a5_saradc_parents, NULL); +static A5_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static A5_COMP_GATE(saradc, SAR_CLK_CTRL0, 8, 0); + +static const struct clk_parent_data a5_pwm_parents[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &a5_rtc_clk.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" } +}; + +static A5_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static A5_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8, 0); + +static A5_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static A5_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24, 0); + +static A5_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static A5_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8, 0); + +static A5_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static A5_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24, 0); + +static A5_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static A5_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8, 0); + +static A5_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static A5_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24, 0); + +static A5_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static A5_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8, 0); + +static A5_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, a5_pwm_parents, NULL); +static A5_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static A5_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24, 0); + +/* + * NOTE: Channel 7 is gp1, because gp1 is designed for DSU, so spicc does = not + * support this source in the driver. + */ +static const struct clk_parent_data a5_spicc_parents[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static A5_COMP_SEL(spicc_0, SPICC_CLK_CTRL, 7, 0x7, a5_spicc_parents, NULL= ); +static A5_COMP_DIV(spicc_0, SPICC_CLK_CTRL, 0, 6); +static A5_COMP_GATE(spicc_0, SPICC_CLK_CTRL, 6, 0); + +static A5_COMP_SEL(spicc_1, SPICC_CLK_CTRL, 23, 0x7, a5_spicc_parents, NUL= L); +static A5_COMP_DIV(spicc_1, SPICC_CLK_CTRL, 16, 6); +static A5_COMP_GATE(spicc_1, SPICC_CLK_CTRL, 22, 0); + +static const struct clk_parent_data a5_sd_emmc_parents[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" }, + { .fw_name =3D "gp0" } +}; + +static A5_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, a5_sd_emmc_parents, + NULL); +static A5_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static A5_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7, 0); + +static A5_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, a5_sd_emmc_parents, + NULL); +static A5_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static A5_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7, 0); + +static struct clk_regmap a5_ts_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_ts =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor a5_eth_125m_div =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_eth_125m_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_eth_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Channel 6 is gp1 dedicated to the DSU. */ +static u32 a5_dspa_parents_val_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data a5_dspa_parents[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "rtc" }, /* rtc_pll */ + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv4" }, + { .hw =3D &a5_rtc_clk.hw } +}; + +static A5_COMP_SEL(dspa_0, DSPA_CLK_CTRL0, 10, 0x7, a5_dspa_parents, + a5_dspa_parents_val_table); +static A5_COMP_DIV(dspa_0, DSPA_CLK_CTRL0, 0, 10); +static A5_COMP_GATE(dspa_0, DSPA_CLK_CTRL0, 13, 0); + +static A5_COMP_SEL(dspa_1, DSPA_CLK_CTRL0, 26, 0x7, a5_dspa_parents, + a5_dspa_parents_val_table); +static A5_COMP_DIV(dspa_1, DSPA_CLK_CTRL0, 16, 10); +static A5_COMP_GATE(dspa_1, DSPA_CLK_CTRL0, 29, 0); + +static struct clk_regmap a5_dspa =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_dspa_0.hw, + &a5_dspa_1.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Channel 6 is gp1 dedicated to the DSU. */ +static u32 a5_nna_parents_val_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data a5_nna_parents[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "hifi" } +}; + +static A5_COMP_SEL(nna_core, NNA_CLK_CNTL, 9, 0x7, a5_nna_parents, + a5_nna_parents_val_table); +static A5_COMP_DIV(nna_core, NNA_CLK_CNTL, 0, 7); +static A5_COMP_GATE(nna_core, NNA_CLK_CNTL, 8, 0); + +static A5_COMP_SEL(nna_axi, NNA_CLK_CNTL, 25, 0x7, a5_nna_parents, + a5_nna_parents_val_table); +static A5_COMP_DIV(nna_axi, NNA_CLK_CNTL, 16, 7); +static A5_COMP_GATE(nna_axi, NNA_CLK_CNTL, 24, 0); + +static struct clk_hw *a5_peripherals_hw_clks[] =3D { + [CLKID_RTC_DUALDIV_CLKIN] =3D &a5_rtc_dualdiv_clkin.hw, + [CLKID_RTC_DUALDIV] =3D &a5_rtc_dualdiv.hw, + [CLKID_RTC_DUALDIV_SEL] =3D &a5_rtc_dualdiv_sel.hw, + [CLKID_RTC_DUALDIV_CLKOUT] =3D &a5_rtc_dualdiv_clkout.hw, + [CLKID_RTC_CLK] =3D &a5_rtc_clk.hw, + [CLKID_SYS_RESET_CTRL] =3D &a5_sys_reset_ctrl.hw, + [CLKID_SYS_PWR_CTRL] =3D &a5_sys_pwr_ctrl.hw, + [CLKID_SYS_PAD_CTRL] =3D &a5_sys_pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &a5_sys_ctrl.hw, + [CLKID_SYS_TS_PLL] =3D &a5_sys_ts_pll.hw, + [CLKID_SYS_DEV_ARB] =3D &a5_sys_dev_arb.hw, + [CLKID_SYS_MAILBOX] =3D &a5_sys_mailbox.hw, + [CLKID_SYS_JTAG_CTRL] =3D &a5_sys_jtag_ctrl.hw, + [CLKID_SYS_IR_CTRL] =3D &a5_sys_ir_ctrl.hw, + [CLKID_SYS_MSR_CLK] =3D &a5_sys_msr_clk.hw, + [CLKID_SYS_ROM] =3D &a5_sys_rom.hw, + [CLKID_SYS_CPU_ARB] =3D &a5_sys_cpu_apb.hw, + [CLKID_SYS_RSA] =3D &a5_sys_rsa.hw, + [CLKID_SYS_SARADC] =3D &a5_sys_saradc.hw, + [CLKID_SYS_STARTUP] =3D &a5_sys_startup.hw, + [CLKID_SYS_SECURE] =3D &a5_sys_secure.hw, + [CLKID_SYS_SPIFC] =3D &a5_sys_spifc.hw, + [CLKID_SYS_DSPA] =3D &a5_sys_dspa.hw, + [CLKID_SYS_NNA] =3D &a5_sys_nna.hw, + [CLKID_SYS_ETH_MAC] =3D &a5_sys_eth_mac.hw, + [CLKID_SYS_RAMA] =3D &a5_sys_rama.hw, + [CLKID_SYS_RAMB] =3D &a5_sys_ramb.hw, + [CLKID_SYS_AUDIO_TOP] =3D &a5_sys_audio_top.hw, + [CLKID_SYS_AUDIO_VAD] =3D &a5_sys_audio_vad.hw, + [CLKID_SYS_USB] =3D &a5_sys_usb.hw, + [CLKID_SYS_SD_EMMC_A] =3D &a5_sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_C] =3D &a5_sys_sd_emmc_c.hw, + [CLKID_SYS_PWM_AB] =3D &a5_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &a5_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &a5_sys_pwm_ef.hw, + [CLKID_SYS_PWM_GH] =3D &a5_sys_pwm_gh.hw, + [CLKID_SYS_SPICC_1] =3D &a5_sys_spicc_1.hw, + [CLKID_SYS_SPICC_0] =3D &a5_sys_spicc_0.hw, + [CLKID_SYS_UART_A] =3D &a5_sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &a5_sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &a5_sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &a5_sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &a5_sys_uart_e.hw, + [CLKID_SYS_I2C_M_A] =3D &a5_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &a5_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &a5_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &a5_sys_i2c_m_d.hw, + [CLKID_SYS_RTC] =3D &a5_sys_rtc.hw, + [CLKID_AXI_AUDIO_VAD] =3D &a5_axi_audio_vad.hw, + [CLKID_AXI_AUDIO_TOP] =3D &a5_axi_audio_top.hw, + [CLKID_AXI_RAMB] =3D &a5_axi_ramb.hw, + [CLKID_AXI_RAMA] =3D &a5_axi_rama.hw, + [CLKID_AXI_NNA] =3D &a5_axi_nna.hw, + [CLKID_AXI_DEV1_DMC] =3D &a5_axi_dev1_dmc.hw, + [CLKID_AXI_DEV0_DMC] =3D &a5_axi_dev0_dmc.hw, + [CLKID_AXI_DSP_DMC] =3D &a5_axi_dsp_dmc.hw, + [CLKID_12_24M_IN] =3D &a5_clk_12_24m_in.hw, + [CLKID_12M_24M] =3D &a5_clk_12_24m.hw, + [CLKID_FCLK_25M_DIV] =3D &a5_fclk_25m_div.hw, + [CLKID_FCLK_25M] =3D &a5_fclk_25m.hw, + [CLKID_GEN_SEL] =3D &a5_gen_sel.hw, + [CLKID_GEN_DIV] =3D &a5_gen_div.hw, + [CLKID_GEN] =3D &a5_gen.hw, + [CLKID_SARADC_SEL] =3D &a5_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &a5_saradc_div.hw, + [CLKID_SARADC] =3D &a5_saradc.hw, + [CLKID_PWM_A_SEL] =3D &a5_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &a5_pwm_a_div.hw, + [CLKID_PWM_A] =3D &a5_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &a5_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &a5_pwm_b_div.hw, + [CLKID_PWM_B] =3D &a5_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &a5_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &a5_pwm_c_div.hw, + [CLKID_PWM_C] =3D &a5_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &a5_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &a5_pwm_d_div.hw, + [CLKID_PWM_D] =3D &a5_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &a5_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &a5_pwm_e_div.hw, + [CLKID_PWM_E] =3D &a5_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &a5_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &a5_pwm_f_div.hw, + [CLKID_PWM_F] =3D &a5_pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &a5_pwm_g_sel.hw, + [CLKID_PWM_G_DIV] =3D &a5_pwm_g_div.hw, + [CLKID_PWM_G] =3D &a5_pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &a5_pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &a5_pwm_h_div.hw, + [CLKID_PWM_H] =3D &a5_pwm_h.hw, + [CLKID_SPICC_0_SEL] =3D &a5_spicc_0_sel.hw, + [CLKID_SPICC_0_DIV] =3D &a5_spicc_0_div.hw, + [CLKID_SPICC_0] =3D &a5_spicc_0.hw, + [CLKID_SPICC_1_SEL] =3D &a5_spicc_1_sel.hw, + [CLKID_SPICC_1_DIV] =3D &a5_spicc_1_div.hw, + [CLKID_SPICC_1] =3D &a5_spicc_1.hw, + [CLKID_SD_EMMC_A_SEL] =3D &a5_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &a5_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &a5_sd_emmc_a.hw, + [CLKID_SD_EMMC_C_SEL] =3D &a5_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &a5_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &a5_sd_emmc_c.hw, + [CLKID_TS_DIV] =3D &a5_ts_div.hw, + [CLKID_TS] =3D &a5_ts.hw, + [CLKID_ETH_125M_DIV] =3D &a5_eth_125m_div.hw, + [CLKID_ETH_125M] =3D &a5_eth_125m.hw, + [CLKID_ETH_RMII_DIV] =3D &a5_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &a5_eth_rmii.hw, + [CLKID_DSPA_0_SEL] =3D &a5_dspa_0_sel.hw, + [CLKID_DSPA_0_DIV] =3D &a5_dspa_0_div.hw, + [CLKID_DSPA_0] =3D &a5_dspa_0.hw, + [CLKID_DSPA_1_SEL] =3D &a5_dspa_1_sel.hw, + [CLKID_DSPA_1_DIV] =3D &a5_dspa_1_div.hw, + [CLKID_DSPA_1] =3D &a5_dspa_1.hw, + [CLKID_DSPA] =3D &a5_dspa.hw, + [CLKID_NNA_CORE_SEL] =3D &a5_nna_core_sel.hw, + [CLKID_NNA_CORE_DIV] =3D &a5_nna_core_div.hw, + [CLKID_NNA_CORE] =3D &a5_nna_core.hw, + [CLKID_NNA_AXI_SEL] =3D &a5_nna_axi_sel.hw, + [CLKID_NNA_AXI_DIV] =3D &a5_nna_axi_div.hw, + [CLKID_NNA_AXI] =3D &a5_nna_axi.hw, +}; + +static const struct meson_clkc_data a5_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D a5_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a5_peripherals_hw_clks), + }, +}; + +static const struct of_device_id a5_peripherals_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a5-peripherals-clkc", + .data =3D &a5_peripherals_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a5_peripherals_clkc_match_table); + +static struct platform_driver a5_peripherals_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a5-peripherals-clkc", + .of_match_table =3D a5_peripherals_clkc_match_table, + }, +}; +module_platform_driver(a5_peripherals_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A5 Peripherals Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0