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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 17:05:08.2559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e2c06d5-dbec-485f-739c-08de59d8657d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE16.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8474 Content-Type: text/plain; charset="utf-8" Instead use amdgpu_gtt_mgr_alloc_entries to avoid hardcoding the number of windows we need. It also allows to simplify amdgpu_gtt_mgr_init because we don't need to reserve some pages anymore and this makes the amdgpu_vce_required_gart_pages function unneeded. --- v5: switch to amdgpu_gtt_mgr_alloc_entries --- Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 66 +++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 18 ------ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 27 ++++++--- 6 files changed, 63 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_gtt_mgr.c index dd9b845d5783..9b0bcf6aca44 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -324,17 +324,13 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, u= int64_t gtt_size) { struct amdgpu_gtt_mgr *mgr =3D &adev->mman.gtt_mgr; struct ttm_resource_manager *man =3D &mgr->manager; - uint64_t start, size; =20 man->use_tt =3D true; man->func =3D &amdgpu_gtt_mgr_func; =20 ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); =20 - start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; - start +=3D amdgpu_vce_required_gart_pages(adev); - size =3D (adev->gmc.gart_size >> PAGE_SHIFT) - start; - drm_mm_init(&mgr->mm, start, size); + drm_mm_init(&mgr->mm, 0, adev->gmc.gart_size >> PAGE_SHIFT); spin_lock_init(&mgr->lock); =20 ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.c index 8b38b5ed9a9c..d23d3046919b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2012,37 +2012,47 @@ static void amdgpu_ttm_free_mmio_remap_bo(struct am= dgpu_device *adev) adev->rmmio_remap.bo =3D NULL; } =20 -static int amdgpu_ttm_buffer_entity_init(struct amdgpu_ttm_buffer_entity *= entity, +static int amdgpu_ttm_buffer_entity_init(struct amdgpu_gtt_mgr *mgr, + struct amdgpu_ttm_buffer_entity *entity, enum drm_sched_priority prio, struct drm_gpu_scheduler **scheds, int num_schedulers, - int starting_gart_window, u32 num_gart_windows) { - int i, r; + int i, r, num_pages; =20 r =3D drm_sched_entity_init(&entity->base, prio, scheds, num_schedulers, = NULL); if (r) return r; =20 - mutex_init(&entity->lock); =20 if (ARRAY_SIZE(entity->gart_window_offs) < num_gart_windows) - return starting_gart_window; + return -EINVAL; + if (num_gart_windows =3D=3D 0) + return 0; + + num_pages =3D num_gart_windows * AMDGPU_GTT_MAX_TRANSFER_SIZE; + r =3D amdgpu_gtt_mgr_alloc_entries(mgr, &entity->node, num_pages, + DRM_MM_INSERT_BEST); + if (r) { + drm_sched_entity_destroy(&entity->base); + return r; + } =20 for (i =3D 0; i < num_gart_windows; i++) { entity->gart_window_offs[i] =3D - (u64)starting_gart_window * AMDGPU_GTT_MAX_TRANSFER_SIZE * - AMDGPU_GPU_PAGE_SIZE; - starting_gart_window++; + (entity->node.start + (u64)i * AMDGPU_GTT_MAX_TRANSFER_SIZE) * + AMDGPU_GPU_PAGE_SIZE; } =20 - return starting_gart_window; + return 0; } =20 -static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_ttm_buffer_entity = *entity) +static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_gtt_mgr *mgr, + struct amdgpu_ttm_buffer_entity *entity) { + amdgpu_gtt_mgr_free_entries(mgr, &entity->node); drm_sched_entity_destroy(&entity->base); } =20 @@ -2343,36 +2353,42 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdg= pu_device *adev, bool enable) =20 ring =3D adev->mman.buffer_funcs_ring; sched =3D &ring->sched; - r =3D amdgpu_ttm_buffer_entity_init(&adev->mman.default_entity, - DRM_SCHED_PRIORITY_KERNEL, &sched, 1, - 0, 0); + r =3D amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.default_entity, + DRM_SCHED_PRIORITY_KERNEL, + &sched, 1, 0); if (r < 0) { dev_err(adev->dev, "Failed setting up TTM entity (%d)\n", r); return; } =20 - r =3D amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, - r, 1); + r =3D amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.clear_entity, + DRM_SCHED_PRIORITY_NORMAL, + &sched, 1, 1); if (r < 0) { dev_err(adev->dev, "Failed setting up TTM BO clear entity (%d)\n", r); goto error_free_default_entity; } =20 - r =3D amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, - r, 2); + r =3D amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.move_entity, + DRM_SCHED_PRIORITY_NORMAL, + &sched, 1, 2); if (r < 0) { dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); goto error_free_clear_entity; } } else { - amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); - amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); - amdgpu_ttm_buffer_entity_fini(&adev->mman.move_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.move_entity); /* Drop all the old fences since re-creating the scheduler entities * will allocate new contexts. */ @@ -2390,9 +2406,11 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgp= u_device *adev, bool enable) return; =20 error_free_clear_entity: - amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entity); error_free_default_entity: - amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); } =20 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ttm.h index 871388b86503..c8284cb2d22c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -40,7 +40,6 @@ #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) =20 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3 =20 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; @@ -56,6 +55,7 @@ struct amdgpu_gtt_mgr { struct amdgpu_ttm_buffer_entity { struct drm_sched_entity base; struct mutex lock; + struct drm_mm_node node; u64 gart_window_offs[2]; }; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vce.c index a7d8f1ce6ac2..eb4a15db2ef2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -450,24 +450,6 @@ void amdgpu_vce_free_handles(struct amdgpu_device *ade= v, struct drm_file *filp) } } =20 -/** - * amdgpu_vce_required_gart_pages() - gets number of GART pages required b= y VCE - * - * @adev: amdgpu_device pointer - * - * Returns how many GART pages we need before GTT for the VCE IP block. - * For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details. - * For VCE2+, this is not needed so return zero. - */ -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev) -{ - /* VCE IP block not added yet, so can't use amdgpu_ip_version */ - if (adev->family =3D=3D AMDGPU_FAMILY_SI) - return 512; - - return 0; -} - /** * amdgpu_vce_get_create_msg - generate a VCE create msg * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_vce.h index 1c3464ce5037..a59d87e09004 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -52,6 +52,7 @@ struct amdgpu_vce { uint32_t srbm_soft_reset; unsigned num_rings; uint32_t keyselect; + struct drm_mm_node node; }; =20 int amdgpu_vce_early_init(struct amdgpu_device *adev); @@ -61,7 +62,6 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev, st= ruct amdgpu_ring *ring) int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *= filp); -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job= *job, struct amdgpu_ib *ib); int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/am= dgpu/vce_v1_0.c index 9ae424618556..bd47fda52e7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -47,11 +47,6 @@ #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 =20 -#define VCE_V1_0_GART_PAGE_START \ - (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) -#define VCE_V1_0_GART_ADDR_START \ - (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) - static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); =20 @@ -541,6 +536,16 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct a= mdgpu_device *adev) u64 num_pages =3D ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_= SIZE; u64 pa =3D amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); u64 flags =3D AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VAL= ID; + u64 vce_gart_start; + int r; + + r =3D amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr, + &adev->vce.node, num_pages, + DRM_MM_INSERT_LOW); + if (r) + return r; + + vce_gart_start =3D adev->vce.node.start * AMDGPU_GPU_PAGE_SIZE; =20 /* * Check if the VCPU BO already has a 32-bit address. @@ -550,12 +555,12 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct = amdgpu_device *adev) return 0; =20 /* Check if we can map the VCPU BO in GART to a 32-bit address. */ - if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) + if (adev->gmc.gart_start + vce_gart_start > max_vcpu_bo_addr) return -EINVAL; =20 - amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START, + amdgpu_gart_map_vram_range(adev, pa, adev->vce.node.start, num_pages, flags, adev->gart.ptr); - adev->vce.gpu_addr =3D adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START; + adev->vce.gpu_addr =3D adev->gmc.gart_start + vce_gart_start; if (adev->vce.gpu_addr > max_vcpu_bo_addr) return -EINVAL; =20 @@ -610,7 +615,11 @@ static int vce_v1_0_sw_fini(struct amdgpu_ip_block *ip= _block) if (r) return r; =20 - return amdgpu_vce_sw_fini(adev); + r =3D amdgpu_vce_sw_fini(adev); + + amdgpu_gtt_mgr_free_entries(&adev->mman.gtt_mgr, &adev->vce.node); + + return r; } =20 /** --=20 2.43.0