From nobody Mon Feb 9 16:51:59 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD7312FD1DB for ; Thu, 22 Jan 2026 15:27:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769095651; cv=none; b=QeurmpbHQmBHkkv1DWe389MDhpMdVMGwMsgyXIXZMdguUb2/t71F2XxWfuruRCJFd0H231VrHtTpL4RajBQjjKdOdICw1TcKN+rKS/TESpfD1KXjCGx/HzfqWyHojCp99n60uz4PYRwrm72HvRksdRfdUrCpf+2x/9+vdn5f/F0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769095651; c=relaxed/simple; bh=eGM/EBqMEDcFmuDjFBM1kZSkKLO4wV+nQKaKtiOH3KM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MJpU6iOaksJG0GZNPqB3vV4Ams1VitM55Pm676qnKYLdmFdCP4BMV3jw1OtJiWn0FyDm/NOMqBDZNQ1Tuo9LF8l14sLCsHNCA0DGANGKcKXqMlZZV0oZX6s0GUqJAaErICJgopS0krPnqtHvS30rJfSAvWroHm10K7jvARrZMaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=h2oTlG5j; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="h2oTlG5j" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-435a11957f6so913552f8f.0 for ; Thu, 22 Jan 2026 07:27:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769095646; x=1769700446; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eSZwviFf1x4T/s2toJik0HTAfoFK/jhdfg8B2E1Bx7s=; b=h2oTlG5jFtxpa5seM6TZUoLqhkBJX4ixn4XmbeQGiKJM/Je/xjBYK36Qhxx6lwPujo /XKxlUouRmoimsO9yudNlX/BI33MO+yQZmwval+yfjibiSA7HABBUBPMGptVvDe/Et+b LmS33MsFNh6NzLTSyR+A6wnv2r4E9xfp9VU0+Yl914IHks8CQIYZ7KLuHUzzbIRym2Rm gMdfW/1W6/yTXfBp9F2aBvaaKXDgIc29lEWQ7Ok47VyEJfBmJhFPjrb3/WNEa/ukkH2R O/aHY2uvT9eb9ELhEM8IaxnEDvMXo4nU/IZ4GLekMtszb9u8ZdBBkDhv2gBq5EctiSN0 mTWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769095646; x=1769700446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eSZwviFf1x4T/s2toJik0HTAfoFK/jhdfg8B2E1Bx7s=; b=BrfX9vBZhOwcd286z3OjKRJKoOK9wukGgRziYgz6jNOgt0+Hq6WnTiNS5KFsISSgfg H7tqRHFlF7CsoHqFS10llUdFeCb7Ov5OL8M0TGJZZACT5nGpIrco9dgut/0zsMGiGc4K ZXLLnu0oVT9pChSJurTtWgP/Cr4REAY3DZkyIHpuYLNljk+THYmt9UOua+DT/1c67h03 QEgNgPs6A1pTYkX2qKbC51ucZBlGIzyXynj1VRCiSAAV2GRpYv9dLjtyeenTeQjdyiJJ BbGWeM4VmZ/6yp3Y+1OqYuSlVBOOb+elwSlm8RLaduP8uxiXdqf3fEdw8P8/5WEH3KIs ybJA== X-Forwarded-Encrypted: i=1; AJvYcCVFWjMCYik2uBpwH2+I9ktMSo6lqki2xrgOZuLtKwSf40fjPQ8L4hVOMq8m+9i9MEHc+ZsWAp76TzTsXQ8=@vger.kernel.org X-Gm-Message-State: AOJu0YzPpZ0KwWQ+SWHOYGJ9gdmpCODENCjbgbevhYjmbmmOp1MUJz7H 0jgdMQQ2y73IxOxIZEwas3u2zVgCB5d2eYERNV3VVKNEwY+NmnfhGJ9j X-Gm-Gg: AZuq6aLEgISX3u4+kGTqtS4S1OSfE5zey7QOERPNVxAsHU3+AIYtBF7Y9fzb9HoNmZe oS3VNLLT0i97wfG4NjDznf04cbJmRQQYHOFohGtU6ybfbJKsKFPVCxLD4uls8gDdy+on46NstqR fTl5V2fcrdmxGXOUpewpIOSY6ZTgJyH4bWyiEhEjfGx6OAqBa/brWGWXJpEatcz0Sm0itYe5HA9 ZdOupDsp184Tq0gngym8iw4TSWK/TJ8J4tEZyoMyP+DzGAnGCAcATUyIbHj1zZ1hmpSsLH/cBJ3 LH/BuzJ0TcdeuPH4H2VhJ5dXT8qQVVHujDjOspOJXWHxtADNDdyUOXFttvAsp0IlVM/Fmk1Cadp hNYHjasfHI1RiOz7Bzz26Vs/E2hpo5g0o/WY116OSg7tMd1KBpe1ZpZPf9yB6SCpFOWXPTknw8a Bc X-Received: by 2002:a05:6000:2386:b0:435:a9ad:d20f with SMTP id ffacd0b85a97d-435a9add46amr4495671f8f.19.1769095645427; Thu, 22 Jan 2026 07:27:25 -0800 (PST) Received: from xeon ([188.163.112.49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4358f138e26sm20762642f8f.17.2026.01.22.07.27.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 07:27:25 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/3] ARM: tegra: lg-x3: add panel and bridge nodes Date: Thu, 22 Jan 2026 17:27:11 +0200 Message-ID: <20260122152713.8311-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260122152713.8311-1-clamor95@gmail.com> References: <20260122152713.8311-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RGB-DSI bridge and panel nodes to LG Optimus 4X and Vu device tees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 23 ++++++ arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 27 +++++++ arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 81 +++++++++++++++++++- 3 files changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p880.dts index c6ef0a20c19f..cc14e6dca770 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -116,6 +116,29 @@ rmi4-f11@11 { }; }; =20 + spi@7000dc00 { + dsi@2 { + /* + * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible =3D "jdi,dx12d100vm0eaa", "renesas,r69328"; + reg =3D <1>; + + reset-gpios =3D <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + vdd-supply =3D <&vcc_3v0_lcd>; + vddio-supply =3D <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&bridge_output>; + }; + }; + }; + }; + }; + memory-controller@7000f000 { emc-timings-0 { /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/d= ts/nvidia/tegra30-lg-p895.dts index e32fafc7f5e0..e300a2c49edf 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -112,6 +112,33 @@ rmi4-f11@11 { }; }; =20 + spi@7000dc00 { + dsi@2 { + /* + * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible =3D "koe,tx13d100vm0eaa", "renesas,r61307"; + reg =3D <1>; + + reset-gpios =3D <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + renesas,gamma =3D <3>; + renesas,inversion; + renesas,contrast; + + vcc-supply =3D <&vcc_3v0_lcd>; + iovcc-supply =3D <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&bridge_output>; + }; + }; + }; + }; + }; + memory-controller@7000f000 { emc-timings-2 { /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dt= s/nvidia/tegra30-lg-x3.dtsi index 909260a5d0fb..d71d1d6694f8 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -20,6 +20,8 @@ aliases { rtc0 =3D &pmic; rtc1 =3D "/rtc@7000e000"; =20 + display0 =3D &lcd; + serial0 =3D &uartd; /* Console */ serial1 =3D &uartc; /* Bluetooth */ serial2 =3D &uartb; /* GPS */ @@ -71,6 +73,21 @@ trustzone@bfe00000 { }; }; =20 + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status =3D "okay"; + + port { + dpi_output: endpoint { + remote-endpoint =3D <&bridge_input>; + bus-width =3D <24>; + }; + }; + }; + }; + }; + vde@6001a000 { assigned-clocks =3D <&tegra_car TEGRA30_CLK_VDE>; assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>; @@ -1357,7 +1374,58 @@ spi@7000dc00 { status =3D "okay"; spi-max-frequency =3D <25000000>; =20 - /* DSI bridge */ + dsi@2 { + compatible =3D "solomon,ssd2825"; + reg =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + spi-max-frequency =3D <1000000>; + + spi-cpha; + spi-cpol; + + reset-gpios =3D <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>; + + dvdd-supply =3D <&vdd_1v2_rgb>; + avdd-supply =3D <&vdd_1v2_rgb>; + vddio-supply =3D <&vdd_1v8_vio>; + + solomon,hs-zero-delay-ns =3D <300>; + solomon,hs-prep-delay-ns =3D <65>; + + clocks =3D <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + + assigned-clocks =3D <&tegra_car TEGRA30_CLK_EXTERN3>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + assigned-clock-rates =3D <24000000>; + + assigned-clock-parents =3D <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_EXTERN3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + bridge_input: endpoint { + remote-endpoint =3D <&dpi_output>; + data-lines =3D <24>; + }; + }; + + port@1 { + reg =3D <1>; + + bridge_output: endpoint { + remote-endpoint =3D <&panel_input>; + }; + }; + }; + }; }; =20 pmc@7000e400 { @@ -1617,6 +1685,17 @@ vdd_1v8_sen: regulator-sen1v8 { vin-supply =3D <&vdd_3v3_vbat>; }; =20 + vdd_1v2_rgb: regulator-rgb1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_1v2_rgb"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + gpio =3D <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vdd_3v3_vbat>; + }; + vcc_3v0_lcd: regulator-lcd3v { compatible =3D "regulator-fixed"; regulator-name =3D "vcc_3v0_lcd"; --=20 2.51.0