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charset="utf-8" Add Enhanced Shared Interrupt (ESI) CPU affinity support to improve UFS performance on Qualcomm platforms. By Default, the IRQ core route interrupts to a limited number of cores while other cores remain idle. This patch enables dynamic interrupt affinity adjustment for better performance tuning by distributing ESI interrupts across all online CPUs in round-robin fashion. This reduces CPU contention and enables better performance optimization on Qualcomm UFS controllers by utilizing all available online CPUs. Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 50 +++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8ebee0cc5313..c43bb75d208c 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -2070,6 +2070,55 @@ static irqreturn_t ufs_qcom_mcq_esi_handler(int irq,= void *data) return IRQ_HANDLED; } +/** + * ufs_qcom_set_esi_affinity - Set CPU affinity hints for ESI interrupts + * @hba: UFS host controller instance + * + * Sets CPU affinity hints for ESI interrupts to distribute them across + * online CPUs for better performance in round-robin fashion. + */ +static void ufs_qcom_set_esi_affinity(struct ufs_hba *hba) +{ + struct msi_desc *desc; + int ret, i =3D 0, nr_irqs =3D 0; + const cpumask_t *mask; + int cpu; + + __msi_lock_descs(hba->dev); + /* Count the number of MSI descriptors */ + msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { + nr_irqs++; + } + __msi_unlock_descs(hba->dev); + + if (nr_irqs =3D=3D 0) + return; + + __msi_lock_descs(hba->dev); + /* Set affinity hints for each interrupt in round-robin fashion */ + msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { + if (i >=3D nr_irqs) + break; + + /* Distribute interrupts across online CPUs in round-robin */ + cpu =3D cpumask_nth(i % num_online_cpus(), cpu_online_mask); + mask =3D get_cpu_mask(cpu); + if (!cpumask_subset(mask, cpu_online_mask)) { + dev_err(hba->dev, "Invalid CPU %d in map, using online CPUs\n", + cpu); + mask =3D cpu_online_mask; + } + + ret =3D irq_set_affinity_hint(desc->irq, mask); + if (ret < 0) + dev_err(hba->dev, "Failed to set affinity hint to CPU %d for ESI IRQ %d= , err =3D %d\n", + cpu, desc->irq, ret); + + i++; + } + __msi_unlock_descs(hba->dev); +} + static int ufs_qcom_config_esi(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -2122,6 +2171,7 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) REG_UFS_CFG3); } ufshcd_mcq_enable_esi(hba); + ufs_qcom_set_esi_affinity(hba); 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charset="utf-8" UFS controller v6.2 requires bit 31 in the spare configuration register to be set for high-speed link startup mode, as per the Hardware Programming Guide (HPG). The spare register value is read during host driver initialization but gets cleared after UFS reset. To align with the UFS v6.2 programming sequence, preserve the spare register value during initialization and restore it during link startup to ensure proper high-speed mode Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 11 ++++++++--- drivers/ufs/host/ufs-qcom.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index c43bb75d208c..ab5aed241913 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -686,6 +686,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, boo= l is_pre_scale_up, unsign static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status) { + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); int err =3D 0; switch (status) { @@ -708,6 +709,10 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba= *hba, */ err =3D ufshcd_disable_host_tx_lcc(hba); + /* Update REG_UFS_DEBUG_SPARE_CFG to set HS-LSS mode in link startup */ + if (host->hw_ver.major =3D=3D 0x6 && host->hw_ver.minor =3D=3D 0x2) + ufshcd_writel(hba, host->spare_cfg, + REG_UFS_DEBUG_SPARE_CFG); break; default: break; @@ -1084,7 +1089,7 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba = *hba) static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) { struct ufs_host_params *host_params =3D &host->host_params; - u32 val, dev_major; + u32 dev_major; /* * Default to powering up the PHY to the max gear possible, which is @@ -1103,8 +1108,8 @@ static void ufs_qcom_set_phy_gear(struct ufs_qcom_hos= t *host) */ host->phy_gear =3D UFS_HS_G2; } else if (host->hw_ver.major >=3D 0x5) { - val =3D ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); - dev_major =3D FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); + host->spare_cfg =3D ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); + dev_major =3D FIELD_GET(UFS_DEV_VER_MAJOR_MASK, host->spare_cfg); /* * Since the UFS device version is populated, let's remove the diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 380d02333d38..d09ef7f44305 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -308,6 +308,7 @@ struct ufs_qcom_host { u32 phy_gear; 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charset="utf-8" The current devfreq downdifferential threshold of 5% causes overly aggressive frequency downscaling, leading to performance degradation sometimes during sequential read workloads. Update the UFS devfreq downdifferential threshold to 65. This widens the hysteresis window and prevents overly aggressive downscaling, ensuring that frequency is maintained for loads above 5% and scaling down occurs only when utilization falls below this level, while scale-up still triggers above the 70% threshold. Signed-off-by: Nitin Rawat Reviewed-by: Konrad Dybcio --- drivers/ufs/host/ufs-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index ab5aed241913..5ef810b95b72 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1962,7 +1962,7 @@ static void ufs_qcom_config_scaling_param(struct ufs_= hba *hba, p->polling_ms =3D 60; p->timer =3D DEVFREQ_TIMER_DELAYED; d->upthreshold =3D 70; - d->downdifferential =3D 5; + d->downdifferential =3D 65; hba->clk_scaling.suspend_on_no_request =3D true; } -- 2.34.1