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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_01,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2601150000 definitions=main-2601220098 X-Authority-Analysis: v=2.4 cv=WbcBqkhX c=1 sm=1 tr=0 ts=697221b1 cx=c_pps a=XiAAW1AwiKB2Y8Wsi+sD2Q==:117 a=XiAAW1AwiKB2Y8Wsi+sD2Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=M51BFTxLslgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yPCof4ZbAAAA:8 a=W2A6FuTIenI3-7UfN4cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDA5NiBTYWx0ZWRfX9Zv0iJEXua69 XsTcmh7/xN2JHZWYukSzDO6a9FeVbC8qiULZqEGTN8z1Um4KUtH6BwbFKc3d1qJchWCxTDOWO34 IS4AVTLs/KhDfNg16zy5BB5bXcMOicUtZemZe0k4p9cb4RAbR4FoD57ABXzcm8HPS6H0VL0jlO9 cnt+E6/6P9DOOu8jxobMQpD6spRJZFRWnmCJmfuNh8YS2JABKS5oaT3qjhqd/urqd/6g1dVK6+U DIVmhNpNZyJub+XrtEWAzFVdK6g7lu+QwXe2EX4IU9pYLZNVMCZqafUCFXK23JejcxN/Dih1J/3 opNwj68pUIEkDOktDUKPKhva9U5W/tOVjavNNP+603l3IcrnXRIgaxgIWdi5UJi2xA7qW6H3INJ PtJH+Iuh+uoTOkTBNfmjhJp/P8fFSVvIzR7jGbVdmyJq3AfwZNmoyxX+qLycf+i8XjFHIoeO8WJ 6oK5I7zRG5HFeSakWjQ== X-Proofpoint-ORIG-GUID: dB5tjO8ckOFC4v1NywuNKUe-CkPlAMXB X-Proofpoint-GUID: dB5tjO8ckOFC4v1NywuNKUe-CkPlAMXB Commit e42010d8207f ("PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX)") fixed a bogus _HPX type 2 record, which instructed program_hpx_type2() to set the RCB in an endpoint, although it's RC did not have the RCB bit set. e42010d8207f fixed that by qualifying the setting of the RCB in the endpoint with the RC supporting an 128 byte RCB. In retrospect, the program_hpx_type2() should only modify the AER bits, and stay away from fiddling with the Link Control Register. Hence, we explicitly program the RCB from pci_configure_device(). According to PCIe r7.0, sec 7.5.3.7, RCB is only valid for Root Ports (where it is Read-Only), Bridges, and Endpoints. The bit is 'RsvdP' for Virtual Functions. Hence, for other cases than Bridges and Physical Endpoints, we bail out early from pci_configure_rcb(). If the Root Port's RCB cannot be determined, we do nothing. If RCB is set in the Root Port and not in the device, we set it. If it is set in the device but not in the Root Port, we print an info message and reset it. Fixes: Commit e42010d8207f ("PCI: Set Read Completion Boundary to 128 iff R= oot Port supports it (_HPX)") Signed-off-by: H=C3=A5kon Bugge Reviewed-by: Niklas Schnelle Tested-by only makes sense for this one. Tested-by: Niklas Schnelle --- Note, that the current duplication of pcie_root_rcb_set() will be removed in the next commit. v2 -> v3: * Qualified the device types more strictly * s/pcie_root_rcb_set/pcie_read_root_rcb/ and changed signature * Do nothing if the RP's RCB cannot be determined * Reset the device's RCB if not set in the RP --- drivers/pci/probe.c | 53 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d9..7165ac4065c97 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2410,6 +2410,58 @@ static void pci_configure_serr(struct pci_dev *dev) } } =20 +static bool pcie_read_root_rcb(struct pci_dev *dev, bool *rcb) +{ + struct pci_dev *rp =3D pcie_find_root_port(dev); + u16 lnkctl; + + if (!rp) + return false; + + pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); + + *rcb =3D !!(lnkctl & PCI_EXP_LNKCTL_RCB); + return true; +} + +static void pci_configure_rcb(struct pci_dev *dev) +{ + u16 lnkctl; + bool rcb; + + /* + * Per PCIe r7.0, sec 7.5.3.7, RCB is only meaningful in Root + * Ports (where it is read-only), Endpoints, and Bridges. It + * may only be set for Endpoints and Bridges if it is set in + * the Root Port. For Endpoints, it is 'RsvdP' for Virtual + * Functions. If the Root Port's RCB cannot be determined, we + * bail out. + */ + if (!pci_is_pcie(dev) || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_UPSTREAM || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC || + dev->is_virtfn || !pcie_read_root_rcb(dev, &rcb)) + return; + + pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnkctl); + if (rcb) { + if (lnkctl & PCI_EXP_LNKCTL_RCB) + return; + + lnkctl |=3D PCI_EXP_LNKCTL_RCB; + } else { + if (!(lnkctl & PCI_EXP_LNKCTL_RCB)) + return; + + pci_info(dev, FW_INFO "clearing RCB (RCB not set in Root Port)\n"); + lnkctl &=3D ~PCI_EXP_LNKCTL_RCB; + } + + pcie_capability_write_word(dev, PCI_EXP_LNKCTL, lnkctl); +} + static void pci_configure_device(struct pci_dev *dev) { pci_configure_mps(dev); @@ -2419,6 +2471,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_aspm_l1ss(dev); pci_configure_eetlp_prefix(dev); pci_configure_serr(dev); + pci_configure_rcb(dev); =20 pci_acpi_program_hp_params(dev); } --=20 2.43.5