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Thu, 22 Jan 2026 13:10:09 +0000 (GMT) Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.18.1.2/8.18.1.2) with ESMTP id 60MCJtgA015534; Thu, 22 Jan 2026 13:10:08 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 4br0vctgsc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 22 Jan 2026 13:10:08 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 60MD5mR1028904; Thu, 22 Jan 2026 13:10:08 GMT Received: from lab61.no.oracle.com (lab61.no.oracle.com [10.172.144.82]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 4br0vctgdy-2; Thu, 22 Jan 2026 13:10:07 +0000 From: =?UTF-8?q?H=C3=A5kon=20Bugge?= To: Bjorn Helgaas , Niklas Schnelle Cc: Alex Williamson , Johannes Thumshirn , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, =?UTF-8?q?H=C3=A5kon=20Bugge?= Subject: [PATCH v3 1/2] PCI: Initialize RCB from pci_configure_device Date: Thu, 22 Jan 2026 14:09:53 +0100 Message-ID: <20260122130957.68757-2-haakon.bugge@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20260122130957.68757-1-haakon.bugge@oracle.com> References: <20260122130957.68757-1-haakon.bugge@oracle.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_01,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2601150000 definitions=main-2601220098 X-Authority-Analysis: v=2.4 cv=WbcBqkhX c=1 sm=1 tr=0 ts=697221b1 cx=c_pps a=XiAAW1AwiKB2Y8Wsi+sD2Q==:117 a=XiAAW1AwiKB2Y8Wsi+sD2Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=M51BFTxLslgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yPCof4ZbAAAA:8 a=W2A6FuTIenI3-7UfN4cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDA5NiBTYWx0ZWRfX9Zv0iJEXua69 XsTcmh7/xN2JHZWYukSzDO6a9FeVbC8qiULZqEGTN8z1Um4KUtH6BwbFKc3d1qJchWCxTDOWO34 IS4AVTLs/KhDfNg16zy5BB5bXcMOicUtZemZe0k4p9cb4RAbR4FoD57ABXzcm8HPS6H0VL0jlO9 cnt+E6/6P9DOOu8jxobMQpD6spRJZFRWnmCJmfuNh8YS2JABKS5oaT3qjhqd/urqd/6g1dVK6+U DIVmhNpNZyJub+XrtEWAzFVdK6g7lu+QwXe2EX4IU9pYLZNVMCZqafUCFXK23JejcxN/Dih1J/3 opNwj68pUIEkDOktDUKPKhva9U5W/tOVjavNNP+603l3IcrnXRIgaxgIWdi5UJi2xA7qW6H3INJ PtJH+Iuh+uoTOkTBNfmjhJp/P8fFSVvIzR7jGbVdmyJq3AfwZNmoyxX+qLycf+i8XjFHIoeO8WJ 6oK5I7zRG5HFeSakWjQ== X-Proofpoint-ORIG-GUID: dB5tjO8ckOFC4v1NywuNKUe-CkPlAMXB X-Proofpoint-GUID: dB5tjO8ckOFC4v1NywuNKUe-CkPlAMXB Commit e42010d8207f ("PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX)") fixed a bogus _HPX type 2 record, which instructed program_hpx_type2() to set the RCB in an endpoint, although it's RC did not have the RCB bit set. e42010d8207f fixed that by qualifying the setting of the RCB in the endpoint with the RC supporting an 128 byte RCB. In retrospect, the program_hpx_type2() should only modify the AER bits, and stay away from fiddling with the Link Control Register. Hence, we explicitly program the RCB from pci_configure_device(). According to PCIe r7.0, sec 7.5.3.7, RCB is only valid for Root Ports (where it is Read-Only), Bridges, and Endpoints. The bit is 'RsvdP' for Virtual Functions. Hence, for other cases than Bridges and Physical Endpoints, we bail out early from pci_configure_rcb(). If the Root Port's RCB cannot be determined, we do nothing. If RCB is set in the Root Port and not in the device, we set it. If it is set in the device but not in the Root Port, we print an info message and reset it. Fixes: Commit e42010d8207f ("PCI: Set Read Completion Boundary to 128 iff R= oot Port supports it (_HPX)") Signed-off-by: H=C3=A5kon Bugge Reviewed-by: Niklas Schnelle Tested-by only makes sense for this one. Tested-by: Niklas Schnelle --- Note, that the current duplication of pcie_root_rcb_set() will be removed in the next commit. v2 -> v3: * Qualified the device types more strictly * s/pcie_root_rcb_set/pcie_read_root_rcb/ and changed signature * Do nothing if the RP's RCB cannot be determined * Reset the device's RCB if not set in the RP --- drivers/pci/probe.c | 53 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d9..7165ac4065c97 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2410,6 +2410,58 @@ static void pci_configure_serr(struct pci_dev *dev) } } =20 +static bool pcie_read_root_rcb(struct pci_dev *dev, bool *rcb) +{ + struct pci_dev *rp =3D pcie_find_root_port(dev); + u16 lnkctl; + + if (!rp) + return false; + + pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); + + *rcb =3D !!(lnkctl & PCI_EXP_LNKCTL_RCB); + return true; +} + +static void pci_configure_rcb(struct pci_dev *dev) +{ + u16 lnkctl; + bool rcb; + + /* + * Per PCIe r7.0, sec 7.5.3.7, RCB is only meaningful in Root + * Ports (where it is read-only), Endpoints, and Bridges. It + * may only be set for Endpoints and Bridges if it is set in + * the Root Port. For Endpoints, it is 'RsvdP' for Virtual + * Functions. If the Root Port's RCB cannot be determined, we + * bail out. + */ + if (!pci_is_pcie(dev) || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_UPSTREAM || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC || + dev->is_virtfn || !pcie_read_root_rcb(dev, &rcb)) + return; + + pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnkctl); + if (rcb) { + if (lnkctl & PCI_EXP_LNKCTL_RCB) + return; + + lnkctl |=3D PCI_EXP_LNKCTL_RCB; + } else { + if (!(lnkctl & PCI_EXP_LNKCTL_RCB)) + return; + + pci_info(dev, FW_INFO "clearing RCB (RCB not set in Root Port)\n"); + lnkctl &=3D ~PCI_EXP_LNKCTL_RCB; + } + + pcie_capability_write_word(dev, PCI_EXP_LNKCTL, lnkctl); +} + static void pci_configure_device(struct pci_dev *dev) { pci_configure_mps(dev); @@ -2419,6 +2471,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_aspm_l1ss(dev); pci_configure_eetlp_prefix(dev); pci_configure_serr(dev); + pci_configure_rcb(dev); =20 pci_acpi_program_hp_params(dev); } --=20 2.43.5 From nobody Sun Feb 8 09:11:12 2026 Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DFA9349AF9; Thu, 22 Jan 2026 13:10:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.165.32 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769087436; cv=none; b=hjL8JPWrEv4KjBY+np2okkhn93kB+1ybpqIT+vn+8d9pbk8IhRpUDWDh2Qer6RQtL01A2gDLucdEm9vmXMS5ST+SxM6YK+iEWhEBIOaHKFGoJ6LQ7+oN7NmNrqea/UDoUIJ8KfQAribxiSUhN1QGb90deaSSlLNm9KWmORRg4IU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769087436; c=relaxed/simple; bh=7cKBl8VA9pIRPJpKxXnBHYyhN6tYa5aTxtvIyhJ0Yh4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jxlVwLkVyHl8S0KzuBTG5SskcYbHUbO0g7NjZBhvjlrMTlPyqMsSqjaH8veGWXdPyGRIhs7gOPeIgbjpQeATQhri1NSPyK72Q5n6RcSVC58BF1e4Lh5cSHb+jI49DK7/9nROt4yY8xVgXx9k6qWXMtoAsQ3S4klOSKdrA9DZ0CU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oracle.com; spf=pass smtp.mailfrom=oracle.com; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b=Ce6CqWDG; arc=none smtp.client-ip=205.220.165.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oracle.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oracle.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b="Ce6CqWDG" Received: from pps.filterd (m0246617.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60M0IDl93032045; Thu, 22 Jan 2026 13:10:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= corp-2025-04-25; bh=nJxYE5tWOaA+nFUgNT+GxlYvfYWT4LvK7kd/62xiFl8=; b= Ce6CqWDGgsthWplFqiSoPjN7iOWmzJ9BcBCaHfGZFvMgeaxDQjJ6G89kowQKMFYA ycRuapFGrc7tR5XwXO3a8P3xhXu1IVdB7MwRssfSa1UT9lLWwACSLq1Tqwq4hSm2 8RUdUfaxSolHy2oV7Cpt7jbOEVxJXdJYiN3ujl2KqO+CaPGhTO3xv0d/wZLsUGz9 qsJCboQ0keWhNZNu9T5HfJXL1zzFePfxdlmL2NyN5VmlzpBVf13//2DxhKW3gFq1 wEqZoObk15CK4sBFFtPsC/TxI4TtOtOCIeJmXareU0P4+v8qlw5ijIOQ16ZtA1r7 Dxz4niWOTKgnieLLdBsMwQ== Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.appoci.oracle.com [138.1.114.2]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 4br2ypyjub-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 22 Jan 2026 13:10:14 +0000 (GMT) Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.18.1.2/8.18.1.2) with ESMTP id 60MD0XQ1015492; Thu, 22 Jan 2026 13:10:13 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 4br0vctgwd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 22 Jan 2026 13:10:13 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 60MD5mR3028904; Thu, 22 Jan 2026 13:10:13 GMT Received: from lab61.no.oracle.com (lab61.no.oracle.com [10.172.144.82]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 4br0vctgdy-3; Thu, 22 Jan 2026 13:10:12 +0000 From: =?UTF-8?q?H=C3=A5kon=20Bugge?= To: Bjorn Helgaas , Niklas Schnelle , "Rafael J. Wysocki" , Len Brown , Mahesh J Salgaonkar , "Oliver O'Halloran" , Greg Kroah-Hartman , Kenji Kaneshige Cc: Alex Williamson , Johannes Thumshirn , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, =?UTF-8?q?H=C3=A5kon=20Bugge?= , linuxppc-dev@lists.ozlabs.org Subject: [PATCH v3 2/2] PCI/ACPI: Confine program_hpx_type2 to the AER bits Date: Thu, 22 Jan 2026 14:09:54 +0100 Message-ID: <20260122130957.68757-3-haakon.bugge@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20260122130957.68757-1-haakon.bugge@oracle.com> References: <20260122130957.68757-1-haakon.bugge@oracle.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_01,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2601150000 definitions=main-2601220098 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDA5NiBTYWx0ZWRfX52jA4HJu4E7K YXMoMji/HCQuhPKrKAIX/mYswMggY9iCnKrmwdIM/6mn+9Lt3YVsB1DNv0NgvfyqqtthgUvGbm/ 57WVWqCXUWdE3pGavY519iKXoAQzJ5boBptsHd+xNVtBhi1k+k3vjMZCywr6jVix+KA495sSPoF l7Dhqn3Jr9uSc3XPQgW2jD/g5vG8jI26FWylNfFMY/qg225wFFNO3ByPJI5azDVqjH9EC2bT8xT e0BrkfVgCslzxwA97ZMDZZ+WPBQK9A/R5/Iw4opFPfqbkkUgLxd40mLACbnV0C+wC6AWY37Bn+j lezvSaI6JStoT0TeCOS/xQHMdl6zj59mWPXRfU9VVNYJuObqI396ieS03eOtgnUgJBQe2SJR1Pk sMlqYZVDWtMtWHirAujY71DqPIz+icPq1EpPqKjOgkelOoBPKaRJ8IRMgQON4OzO5AF7rlMJBki 4SsGD1O19WzV2oehFuQ== X-Authority-Analysis: v=2.4 cv=de6NHHXe c=1 sm=1 tr=0 ts=697221b6 cx=c_pps a=XiAAW1AwiKB2Y8Wsi+sD2Q==:117 a=XiAAW1AwiKB2Y8Wsi+sD2Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=M51BFTxLslgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yPCof4ZbAAAA:8 a=CF6WusRKGoJ8OkfercgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: yXe7wd63ys3MNZY58qSg4iGD59Ki9CQA X-Proofpoint-GUID: yXe7wd63ys3MNZY58qSg4iGD59Ki9CQA program_hpx_type2() is today unconditionally called, despite the fact that when the _HPX was added to the ACPI spec. v3.0, the description stated: OSPM [1] will only evaluate _HPX with Setting Record =E2=80=93 Type 2 if O= SPM is not controlling the PCI Express Advanced Error Reporting capability. Hence, we only call program_hpx_type2() when the OSPM owns the PCIe hotplug capability but not the AER. The Advanced Configuration and Power Interface (ACPI) Specification version 6.6 has a provision that gives the OSPM the ability to control the other PCIe Device Control bits any way. In a note in section 6.2.9, it is stated: "OSPM may override the settings provided by the _HPX object's Type2 record (PCI Express Settings) or Type3 record (PCI Express Descriptor Settings) when OSPM has assumed native control of the corresponding feature." So, in order to preserve the non-AER bits in PCIe Device Control, in particular the performance sensitive ExtTag and RO, we make sure program_hpx_type2() if called, doesn't modify any non-AER bits. Also, when program_hpx_type2() is called, we completely avoid modifying any bits in the Link Control register. However, if the _HPX type 2 records contains bits indicating such modifications, we print an info message. [1] Operating System-directed configuration and Power Management Fixes: 40abb96c51bb ("[PATCH] pciehp: Fix programming hotplug parameters") Signed-off-by: H=C3=A5kon Bugge --- v2 -> v3: * No changes v1 -> v2: * Fixed comment style * Simplified the and/or logic when programming the Device Control register * Fixed the incorrect and brutal warning about Link Control register bits set and changed it to an info message about _HPX attempting to set/reset bits therein. * Removed the RCB programming from program_hpx_type2() * Moved the PCI_EXP_AER_FLAGS definition from drivers/pci/pcie/aer.c to drivers/pci/pci.h --- drivers/pci/pci-acpi.c | 61 +++++++++++++++++++----------------------- drivers/pci/pci.h | 3 +++ drivers/pci/pcie/aer.c | 3 --- 3 files changed, 30 insertions(+), 37 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9369377725fa0..34ea22f65a410 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -271,21 +271,6 @@ static acpi_status decode_type1_hpx_record(union acpi_= object *record, return AE_OK; } =20 -static bool pcie_root_rcb_set(struct pci_dev *dev) -{ - struct pci_dev *rp =3D pcie_find_root_port(dev); - u16 lnkctl; - - if (!rp) - return false; - - pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); - if (lnkctl & PCI_EXP_LNKCTL_RCB) - return true; - - return false; -} - /* _HPX PCI Express Setting Record (Type 2) */ struct hpx_type2 { u32 revision; @@ -311,6 +296,7 @@ static void program_hpx_type2(struct pci_dev *dev, stru= ct hpx_type2 *hpx) { int pos; u32 reg32; + const struct pci_host_bridge *host; =20 if (!hpx) return; @@ -318,6 +304,15 @@ static void program_hpx_type2(struct pci_dev *dev, str= uct hpx_type2 *hpx) if (!pci_is_pcie(dev)) return; =20 + host =3D pci_find_host_bridge(dev->bus); + + /* + * We only do the HP programming if we own the PCIe native + * hotplug and not the AER ownership + */ + if (!host->native_pcie_hotplug || host->native_aer) + return; + if (hpx->revision > 1) { pci_warn(dev, "PCIe settings rev %d not supported\n", hpx->revision); @@ -325,33 +320,31 @@ static void program_hpx_type2(struct pci_dev *dev, st= ruct hpx_type2 *hpx) } =20 /* - * Don't allow _HPX to change MPS or MRRS settings. We manage - * those to make sure they're consistent with the rest of the + * We only allow _HPX to program the AER registers, namely + * PCI_EXP_DEVCTL_CERE, PCI_EXP_DEVCTL_NFERE, + * PCI_EXP_DEVCTL_FERE, and PCI_EXP_DEVCTL_URRE. + * + * The other settings in PCIe DEVCTL are managed by OS in + * order to make sure they're consistent with the rest of the * platform. */ - hpx->pci_exp_devctl_and |=3D PCI_EXP_DEVCTL_PAYLOAD | - PCI_EXP_DEVCTL_READRQ; - hpx->pci_exp_devctl_or &=3D ~(PCI_EXP_DEVCTL_PAYLOAD | - PCI_EXP_DEVCTL_READRQ); + hpx->pci_exp_devctl_and |=3D ~PCI_EXP_AER_FLAGS; + hpx->pci_exp_devctl_or &=3D PCI_EXP_AER_FLAGS; =20 /* Initialize Device Control Register */ pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, ~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or); =20 - /* Initialize Link Control Register */ + /* Log if _HPX attempts to modify PCIe Link Control register */ if (pcie_cap_has_lnkctl(dev)) { - - /* - * If the Root Port supports Read Completion Boundary of - * 128, set RCB to 128. Otherwise, clear it. - */ - hpx->pci_exp_lnkctl_and |=3D PCI_EXP_LNKCTL_RCB; - hpx->pci_exp_lnkctl_or &=3D ~PCI_EXP_LNKCTL_RCB; - if (pcie_root_rcb_set(dev)) - hpx->pci_exp_lnkctl_or |=3D PCI_EXP_LNKCTL_RCB; - - pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, - ~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or); + if (hpx->pci_exp_lnkctl_and) + pci_info(dev, + "_HPX attempts to reset the following bits in PCIe Link Control: 0x%0= 4x\n", + hpx->pci_exp_lnkctl_and); + if (hpx->pci_exp_lnkctl_or) + pci_info(dev, + "_HPX attempts to set the following bits in PCIe Link Control: 0x%04x= \n", + hpx->pci_exp_lnkctl_or); } =20 /* Find Advanced Error Reporting Enhanced Capability */ diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0e67014aa0013..f388d4414dd3a 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -88,6 +88,9 @@ struct pcie_tlp_log; #define PCI_BUS_BRIDGE_MEM_WINDOW 1 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 =20 +#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ + PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; =20 diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index e0bcaa896803c..9472d86cef552 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -239,9 +239,6 @@ void pcie_ecrc_get_policy(char *str) } #endif /* CONFIG_PCIE_ECRC */ =20 -#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ - PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) - int pcie_aer_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); --=20 2.43.5