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Thu, 22 Jan 2026 03:08:08 -0800 From: Kartik Rajput To: , , , , , , CC: Kartik Rajput Subject: [PATCH] soc/tegra: pmc: Add PMC support for Tegra410 Date: Thu, 22 Jan 2026 16:38:05 +0530 Message-ID: <20260122110805.97899-1-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB53:EE_|CH3PR12MB7690:EE_ X-MS-Office365-Filtering-Correlation-Id: ea8214f4-86aa-4032-3666-08de59a69150 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GHHUCNRRabL34GXf0JoRbzJNHQJpsSD7Q1msRbuL5vcH2+k/Bf+wDWK47LTw?= =?us-ascii?Q?3e8onMQoZtJyO1TJbstZs+qYfzdhyrd1Wlf0piJPNKeHDzyLS2Rf/eOzAOhZ?= =?us-ascii?Q?8icAjbVtd5c7I3sJXHqIU6o3a3wD3wFf3jGKc5GPsLLepNZyT8KDJ5XfIPe4?= =?us-ascii?Q?g6eXQv4i2Y2i87CaeCh8lTRST1v9RDYE6LW7ehMAJ4qDa8BLNMYA+ShF7C4i?= =?us-ascii?Q?Pl34ZIPKoYLmq5LCqJ/s/upxd86zgUtVSaIjNWl/Nxdmna11opjKQPYczBhF?= =?us-ascii?Q?dRKvR/XEZCozy/0zHD+gi/ycjy6eoeZtThBLLWuJ6e7DIhFPcGQkyVMCvPhi?= =?us-ascii?Q?5z6KnyOwN3XQHoHwjMVfU2DevGqh/C2S3qkkiKMQQZyVomOjrCn8dbAFUYme?= =?us-ascii?Q?d8sVDw45IBXHyqd/nIsUXB/bkmpm5qE22ggg8e7vJdecj0XoVq/VyXPSJBma?= =?us-ascii?Q?UMbrc9WXMcVT9WHFPyAbN8uE20S+u08DjEFg1A4A1R8hPsOX9pu3qOilXSwR?= =?us-ascii?Q?V2HYGmXvmJ0SVOuYl9opyxKGXLZQ1SMhbRsknvblETTskEnFzpQ3huyuGnqw?= =?us-ascii?Q?AzrHo6OIeKljoZ4d2Opa6V7YA10iGIpddbjQRtjW0/yvYF/m+aecKlAIuFes?= =?us-ascii?Q?FpazlIVNWoF5CfvQ/GOzrXzJ4WxHPg7JW766tKs5UPnPDFuEnHJzkRVZ+ysE?= =?us-ascii?Q?rqVAaNtiwX0BEWspsaIWhrRrwLju/80CidfBENNBKmC2b+UAEm4nXt6ikTo1?= =?us-ascii?Q?MtP1aIHYAjNSdfhfbwcNW2ODlj51s3sdphyON+L2uhfpXx/xvg200UHZRlcc?= =?us-ascii?Q?KqCLiMc2Dvlo5nN6Da6h37gw3Ewf/aH4t0hEs9abul//RLjNI+1kRIqGmSsp?= =?us-ascii?Q?f7ryFFpcAJ2qYiTdKsC6BmgWp//wLmh+7+ECKQdNvQ6OgPpKx9IXCIJlpI3h?= =?us-ascii?Q?zWwLvtJvXm0+EIIffwdqU7RNUtZumH90eQQDuvOSPrHQQHkLLVSArBZb6V9V?= =?us-ascii?Q?ZNZOLAvQj1NsCJ2BI6EvWV7gdEDHnWHaS5g6VbVwFZNbzMx4nhAW0aH+BYp2?= =?us-ascii?Q?tKhbq7MOzg1gkdd7uLi0Z5SN7NyCPxShZsGFGHwt2IXklwh5XzDUamRdBE2n?= =?us-ascii?Q?VZAZoPQo6pdv2tRVnWrEAm6y8i2vUN5TKp42N74+aNAnb8wmC4L/JAs9/bkU?= =?us-ascii?Q?oequdGLNrsN9cubX2uorHYe60KINrdBYm1msv5m4xOvNV/Ep5CAhxhRV69tJ?= =?us-ascii?Q?Woh1KtZiq8voHaLRrroVNuYIFmS5C96Q55ynOeOxY/rKTWVfZvUpqa5Pnhpn?= =?us-ascii?Q?weMZuuIa0eWaBSFHYJICneZ2k8+hHwHLcMhrXR4hwJgGqdm2o9UAXM45uxj2?= =?us-ascii?Q?Tlfs/0qZbkNkJnwqL675oGJ2xMbpishoGh4+/WXV2cVEvQEfrSm66ZGIWfFI?= =?us-ascii?Q?Rp3jd9Yc+vKmDxnUmXyoxlBRNcUwf0q2o17fltOtO+XDZaevk2amqUYIkVcE?= =?us-ascii?Q?v3ck/kQTmqQ6Lp+A40ik9TkpGOFtoDWuOhcoFHI5KraM5XDyuJ36waT9FDFo?= =?us-ascii?Q?Wf377IhByJZ+7QYrhfbmfU0ZmACaHR/rl/J1RDOGPYTjZX4yStK4GLV6jFSf?= =?us-ascii?Q?0HDHkJB24eDjSsFPRQbISOffK4S+5D5Tf/PxiDCY90K+mwGLJkJ+2cWtAwsU?= =?us-ascii?Q?/TRrLw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 11:08:26.8792 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea8214f4-86aa-4032-3666-08de59a69150 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7690 Content-Type: text/plain; charset="utf-8" Tegra410 uses PMC driver only to retrieve system reset reason using PMC sysfs. Tegra410 uses ACPI to probe PMC, unlike device-tree boot it does not use the early initialisation sequence. Add PMC support for Tegra410. Signed-off-by: Kartik Rajput --- drivers/soc/tegra/pmc.c | 128 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 9cdbd8ba94be..2bdcd6d30261 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -11,6 +11,7 @@ =20 #define pr_fmt(fmt) "tegra-pmc: " fmt =20 +#include #include #include #include @@ -3095,12 +3096,30 @@ static void tegra_pmc_reset_suspend_mode(void *data) pmc->suspend_mode =3D TEGRA_SUSPEND_NOT_READY; } =20 +static int tegra_pmc_acpi_probe(struct platform_device *pdev) +{ + pmc->soc =3D device_get_match_data(&pdev->dev); + pmc->dev =3D &pdev->dev; + + pmc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pmc->base)) + return PTR_ERR(pmc->base); + + tegra_pmc_reset_sysfs_init(pmc); + platform_set_drvdata(pdev, pmc); + + return 0; +} + static int tegra_pmc_probe(struct platform_device *pdev) { void __iomem *base; struct resource *res; int err; =20 + if (is_acpi_node(dev_fwnode(&pdev->dev))) + return tegra_pmc_acpi_probe(pdev); + /* * Early initialisation should have configured an initial * register mapping and setup the soc data pointer. If these @@ -4615,6 +4634,108 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = =3D { .max_wake_vectors =3D 4, }; =20 +static const char * const tegra410_reset_sources[] =3D { + "SYS_RESET_N", /* 0x0 */ + "CSDC_RTC_XTAL", + "VREFRO_POWER_BAD", + "FMON_32K", + "FMON_OSC", + "POD_RTC", + "POD_IO", + "POD_PLUS_IO_SPLL", + "POD_PLUS_IO_VMON", /* 0x8 */ + "POD_PLUS_SOC", + "VMON_PLUS_UV", + "VMON_PLUS_OV", + "FUSECRC_FAULT", + "OSC_FAULT", + "BPMP_BOOT_FAULT", + "SCPM_BPMP_CORE_CLK", + "SCPM_PSC_SE_CLK", /* 0x10 */ + "VMON_SOC_MIN", + "VMON_SOC_MAX", + "NVJTAG_SEL_MONITOR", + "L0_RST_REQ_N", + "NV_THERM_FAULT", + "PSC_SW", + "POD_C2C_LPI_0", + "POD_C2C_LPI_1", /* 0x18 */ + "BPMP_FMON", + "FMON_SPLL_OUT", + "L1_RST_REQ_N", + "OCP_RECOVERY", + "AO_WDT_POR", + "BPMP_WDT_POR", + "RAS_WDT_POR", + "TOP_0_WDT_POR", /* 0x20 */ + "TOP_1_WDT_POR", + "TOP_2_WDT_POR", + "PSC_WDT_POR", + "OOBHUB_WDT_POR", + "MSS_SEQ_WDT_POR", + "SW_MAIN", + "L0L1_RST_OUT_N", + "HSM", /* 0x28 */ + "CSITE_SW", + "AO_WDT_DBG", + "BPMP_WDT_DBG", + "RAS_WDT_DBG", + "TOP_0_WDT_DBG", + "TOP_1_WDT_DBG", + "TOP_2_WDT_DBG", + "PSC_WDT_DBG", /* 0x30 */ + "TSC_0_WDT_DBG", + "TSC_1_WDT_DBG", + "OOBHUB_WDT_DBG", + "MSS_SEQ_WDT_DBG", + "L2_RST_REQ_N", + "L2_RST_OUT_N", + "SC7" +}; + +static const struct tegra_pmc_regs tegra410_pmc_regs =3D { + .rst_status =3D 0x8, + .rst_source_shift =3D 0x2, + .rst_source_mask =3D 0xfc, + .rst_level_shift =3D 0x0, + .rst_level_mask =3D 0x3, +}; + +static const struct tegra_pmc_soc tegra410_pmc_soc =3D { + .supports_core_domain =3D false, + .num_powergates =3D 0, + .powergates =3D NULL, + .num_cpu_powergates =3D 0, + .cpu_powergates =3D NULL, + .has_tsense_reset =3D false, + .has_gpu_clamps =3D false, + .needs_mbist_war =3D false, + .has_impl_33v_pwr =3D false, + .maybe_tz_only =3D false, + .num_io_pads =3D 0, + .io_pads =3D NULL, + .num_pin_descs =3D 0, + .pin_descs =3D NULL, + .regs =3D &tegra410_pmc_regs, + .init =3D NULL, + .setup_irq_polarity =3D NULL, + .set_wake_filters =3D NULL, + .irq_set_wake =3D NULL, + .irq_set_type =3D NULL, + .reset_sources =3D tegra410_reset_sources, + .num_reset_sources =3D ARRAY_SIZE(tegra410_reset_sources), + .reset_levels =3D tegra186_reset_levels, + .num_reset_levels =3D ARRAY_SIZE(tegra186_reset_levels), + .num_wake_events =3D 0, + .wake_events =3D NULL, + .max_wake_events =3D 0, + .max_wake_vectors =3D 0, + .pmc_clks_data =3D NULL, + .num_pmc_clks =3D 0, + .has_blink_output =3D false, + .has_single_mmio_aperture =3D false, +}; + static const struct of_device_id tegra_pmc_match[] =3D { { .compatible =3D "nvidia,tegra264-pmc", .data =3D &tegra264_pmc_soc }, { .compatible =3D "nvidia,tegra234-pmc", .data =3D &tegra234_pmc_soc }, @@ -4629,6 +4750,12 @@ static const struct of_device_id tegra_pmc_match[] = =3D { { } }; =20 +static const struct acpi_device_id tegra_pmc_acpi_match[] =3D { + { .id =3D "NVDA2016", .driver_data =3D (kernel_ulong_t)&tegra410_pmc_soc = }, + { } +}; +MODULE_DEVICE_TABLE(acpi, tegra_pmc_acpi_match); + static void tegra_pmc_sync_state(struct device *dev) { struct device_node *np, *child; @@ -4679,6 +4806,7 @@ static struct platform_driver tegra_pmc_driver =3D { .name =3D "tegra-pmc", .suppress_bind_attrs =3D true, .of_match_table =3D tegra_pmc_match, + .acpi_match_table =3D tegra_pmc_acpi_match, #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm =3D &tegra_pmc_pm_ops, #endif --=20 2.43.0