From nobody Mon Feb 9 08:28:32 2026 Received: from out30-118.freemail.mail.aliyun.com (out30-118.freemail.mail.aliyun.com [115.124.30.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E86EE3A9627; Thu, 22 Jan 2026 09:48:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.118 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769075334; cv=none; b=MNGUmMkWJwbNUUTnVjaAK2pKEoopGYbx/qtGtH3Ylo6QuHRl5lZtIQ2bPaz3IPVOS1Xe/CCnV7VbYyRohWJ9h/HCakAYr4cg4hgY+Wih6bFhtPeN15vV4J0HQmheiKq52yW5NUDxibFssTMSBp2yvzmXrDsmk1G6aQgeZYO2Kfk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769075334; c=relaxed/simple; bh=I7VaJtC15QPsbRyJEZs7oEMYTP4IZLTiYkQx5MRzcE8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NvlnpQ/eGKc2tIswKMNur/2OTxYoLl1mTq5ihA7xX0Ejk9NoCz9STEe+fncj28mjoVySggvAGhlZws2PvWQxpcSrdcZenZFXKxfRYwG2A63U4MR5RpReAFYbHoQ6+5MF9ln3y1vDQvpYuyQclkGynoUBfJ/jwjl9KVOgEDXHmfE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=qTu1xlFk; arc=none smtp.client-ip=115.124.30.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="qTu1xlFk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1769075326; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=IB6qe+WiM6Jdm4e2JZteSt/S9JwOmUm8EGeoq5GhI0A=; b=qTu1xlFk0GuZWZqOOhcRDRPH2m1KeplmUBGLA1g9/4IfcVTAeB3QKUqd7GhfQ9WwjyaQ7mbwDN6Mf6BnL1m4rucwqdLsr04gmrebHOK1AciD4HQpuQ5M3TQUFK8/1VU7zBaZrQh08NiAbY33oQpPxnjm7e/Md/L67XB/IMcL5Jk= Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0WxbwhFR_1769075322 cluster:ay36) by smtp.aliyun-inc.com; Thu, 22 Jan 2026 17:48:45 +0800 From: Ruidong Tian To: catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org, guohanjun@huawei.com, sudeep.holla@arm.com, rafael@kernel.org, robin.murphy@arm.com, mark.rutland@arm.com, tony.luck@intel.com, bp@alien8.de, tglx@linutronix.de, peterz@infradead.org Cc: lenb@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, mchehab@kernel.org, xueshuai@linux.alibaba.com, zhuo.song@linux.alibaba.com, oliver.yang@linux.alibaba.com, Ruidong Tian Subject: [PATCH v6 16/16] trace, ras: add ARM RAS extension trace event Date: Thu, 22 Jan 2026 17:46:56 +0800 Message-Id: <20260122094656.73399-17-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20260122094656.73399-1-tianruidong@linux.alibaba.com> References: <20260122094656.73399-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a trace event for hardware errors reported by the ARMv8 RAS extension registers. userspace app can monitor this trace event and decode error information. Signed-off-by: Ruidong Tian --- drivers/ras/aest/aest-core.c | 6 +++ drivers/ras/ras.c | 3 ++ include/ras/ras_event.h | 71 ++++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c index bbf8b1142be7..6a2d84b47721 100644 --- a/drivers/ras/aest/aest-core.c +++ b/drivers/ras/aest/aest-core.c @@ -13,6 +13,8 @@ #include #include =20 +#include + #include "aest.h" =20 DEFINE_PER_CPU(struct aest_device, percpu_adev); @@ -90,6 +92,10 @@ static void aest_print(struct aest_event *event) pr_err("%s ERR%dMISC3: 0x%llx\n", pfx_seq, index, regs->err_misc[3]); } + + trace_arm_ras_ext_event(event->type, event->id0, event->id1, + event->index, event->hid, &event->regs, + event->vendor_data, event->vendor_data_size); } =20 static void aest_handle_memory_failure(u64 addr) diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index 2a5b5a9fdcb3..28ef30ddfeaf 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -111,6 +111,9 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(extlog_mem_event); EXPORT_TRACEPOINT_SYMBOL_GPL(mc_event); EXPORT_TRACEPOINT_SYMBOL_GPL(non_standard_event); EXPORT_TRACEPOINT_SYMBOL_GPL(arm_event); +#ifdef CONFIG_ARM64_RAS_EXTN +EXPORT_TRACEPOINT_SYMBOL_GPL(arm_ras_ext_event); +#endif =20 static int __init parse_ras_param(char *str) { diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index eaecc3c5f772..3a4a0c0e4dbe 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -377,6 +377,77 @@ TRACE_EVENT(aer_event, "Not available") ); #endif /* CONFIG_PCIEAER */ + +/* + * ARM RAS Extension Events Report + * + * This event is generated when an error reported by the ARM RAS extension + * hardware is detected. + */ + +#ifdef CONFIG_ARM64_RAS_EXTN +#include +TRACE_EVENT(arm_ras_ext_event, + + TP_PROTO(const u8 type, + const u32 id0, + const u32 id1, + const u32 index, + char *hid, + struct ras_ext_regs *regs, + const u8 *data, + const u32 len), + + TP_ARGS(type, id0, id1, index, hid, regs, data, len), + + TP_STRUCT__entry( + __field(u8, type) + __field(u32, id0) + __field(u32, id1) + __field(u32, index) + __field(char *, hid) + __field(u64, err_fr) + __field(u64, err_ctlr) + __field(u64, err_status) + __field(u64, err_addr) + __field(u64, err_misc0) + __field(u64, err_misc1) + __field(u64, err_misc2) + __field(u64, err_misc3) + __field(u32, len) + __dynamic_array(u8, buf, len) + ), + + TP_fast_assign( + __entry->type =3D type; + __entry->id0 =3D id0; + __entry->id1 =3D id1; + __entry->index =3D index; + __entry->hid =3D hid; + __entry->err_fr =3D regs->err_fr; + __entry->err_ctlr =3D regs->err_ctlr; + __entry->err_status =3D regs->err_status; + __entry->err_addr =3D regs->err_addr; + __entry->err_misc0 =3D regs->err_misc[0]; + __entry->err_misc1 =3D regs->err_misc[1]; + __entry->err_misc2 =3D regs->err_misc[2]; + __entry->err_misc3 =3D regs->err_misc[3]; + __entry->len =3D len; + memcpy(__get_dynamic_array(buf), data, len); + ), + + TP_printk("type: %d; id0: %d; id1: %d; index: %d; hid: %s; " + "ERR_FR: %llx; ERR_CTLR: %llx; ERR_STATUS: %llx; " + "ERR_ADDR: %llx; ERR_MISC0: %llx; ERR_MISC1: %llx; " + "ERR_MISC2: %llx; ERR_MISC3: %llx; data len:%d; raw data:%s", + __entry->type, __entry->id0, __entry->id1, __entry->index, + __entry->hid, __entry->err_fr, __entry->err_ctlr, + __entry->err_status, __entry->err_addr, __entry->err_misc0, + __entry->err_misc1, __entry->err_misc2, __entry->err_misc3, + __entry->len, + __print_hex(__get_dynamic_array(buf), __entry->len)) +); +#endif /* CONFIG_ARM64_RAS_EXTN */ #endif /* _TRACE_HW_EVENT_MC_H */ =20 /* This part must be outside protection */ --=20 2.51.2.612.gdc70283dfc