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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 08:26:01.2617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc01d4ca-b112-48c8-ec91-08de598fe06b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB6326 Content-Type: text/plain; charset="utf-8" PCIe r6.0, section 7.9.15 requires PTM capability in exactly one function to control all PTM-capable functions. This makes PTM registers controller-level rather than per-function. As suggested by Niklas Cassel, add a comment explaining why PTM capability registers are accessed using the standard DBI accessors instead of func_no indexed per-function accessors. Suggested-by: Niklas Cassel Signed-off-by: Aksh Garg Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-designware-ep.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 12625a1059a4..0a9d5402f23a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -995,6 +995,17 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) if (ep->ops->init) ep->ops->init(ep); =20 + /* + * PCIe r6.0, section 7.9.15 states that for endpoints that support PTM, + * this capability structure is required in exactly one function, which + * controls the PTM behavior of all PTM capable functions. This indicates + * the PTM capability structure represents controller-level registers + * rather than per-function registers. + * + * Therefore, PTM capability registers are configured using the standard = DBI + * accessors, instead of func_no indexed per-function accessors. + */ + ptm_cap_base =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); =20 /* --=20 2.34.1