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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 08:25:53.3759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c62f5c0-fa3a-43e6-4274-08de598fdbbc X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR10MB4691 Content-Type: text/plain; charset="utf-8" The resizable BAR support added by the commit 3a3d4cabe681 ("PCI: dwc: ep: Allow EPF drivers to configure the size of Resizable BARs") incorrectly configures the resizable BARs only for the first Physical Function (PF0) in EP mode. The resizable BAR configuration functions use generic dw_pcie_*_dbi operations instead of physical function specific dw_pcie_ep_*_dbi operations. This causes resizable BAR configuration to always target PF0 regardless of the requested function number. Additionally, dw_pcie_ep_init_non_sticky_registers() only initializes resizable BAR registers for PF0, leaving other PFs unconfigured during the execution of this function. Fix this by using physical function specific configuration space access operations throughout the resizable BAR code path and initializing registers for all the physical functions that support resizable BARs. Fixes: 3a3d4cabe681 ("PCI: dwc: ep: Allow EPF drivers to configure the size= of Resizable BARs") Signed-off-by: Aksh Garg Reviewed-by: Niklas Cassel --- Link to v1: https://lore.kernel.org/all/20260121054214.274429-2-a-garg7@ti.com/ Changes from v1 to v2: - Fixed the suggested nit .../pci/controller/dwc/pcie-designware-ep.c | 48 ++++++++++++------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 19571ac2b961..1458477a6ba9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -75,6 +75,13 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *= ep, u8 func_no, u8 cap) cap, ep, func_no); } =20 +static u16 dw_pcie_ep_find_ext_capability(struct dw_pcie_ep *ep, + u8 func_no, u8 cap) +{ + return PCI_FIND_NEXT_EXT_CAP(dw_pcie_ep_read_cfg, 0, + cap, ep, func_no); +} + /** * dw_pcie_ep_hide_ext_capability - Hide a capability from the linked list * @pci: DWC PCI device @@ -217,22 +224,22 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc,= u8 func_no, u8 vfunc_no, ep->bar_to_atu[bar] =3D 0; } =20 -static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci, +static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie_ep *ep, u8 = func_no, enum pci_barno bar) { u32 reg, bar_index; unsigned int offset, nbars; int i; =20 - offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + offset =3D dw_pcie_ep_find_ext_capability(ep, func_no, PCI_EXT_CAP_ID_REB= AR); if (!offset) return offset; =20 - reg =3D dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + reg =3D dw_pcie_ep_readl_dbi(ep, func_no, offset + PCI_REBAR_CTRL); nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, reg); =20 for (i =3D 0; i < nbars; i++, offset +=3D PCI_REBAR_CTRL) { - reg =3D dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + reg =3D dw_pcie_ep_readl_dbi(ep, func_no, offset + PCI_REBAR_CTRL); bar_index =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, reg); if (bar_index =3D=3D bar) return offset; @@ -253,7 +260,7 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_= ep *ep, u8 func_no, u32 rebar_cap, rebar_ctrl; int ret; =20 - rebar_offset =3D dw_pcie_ep_get_rebar_offset(pci, bar); + rebar_offset =3D dw_pcie_ep_get_rebar_offset(ep, func_no, bar); if (!rebar_offset) return -EINVAL; =20 @@ -283,16 +290,16 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pci= e_ep *ep, u8 func_no, * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. */ - rebar_ctrl =3D dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); + rebar_ctrl =3D dw_pcie_ep_readl_dbi(ep, func_no, rebar_offset + PCI_REBAR= _CTRL); rebar_ctrl &=3D ~GENMASK(31, 16); - dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + dw_pcie_ep_writel_dbi(ep, func_no, rebar_offset + PCI_REBAR_CTRL, rebar_c= trl); =20 /* * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically * updated when writing PCI_REBAR_CAP, see "Figure 3-26 Resizable BAR * Example for 32-bit Memory BAR0" in DWC EP databook 5.96a. */ - dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CAP, rebar_cap); + dw_pcie_ep_writel_dbi(ep, func_no, rebar_offset + PCI_REBAR_CAP, rebar_ca= p); =20 dw_pcie_dbi_ro_wr_dis(pci); =20 @@ -836,20 +843,17 @@ void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); =20 -static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) +static void __dw_pcie_ep_init_non_sticky_registers(struct dw_pcie_ep *ep, = u8 func_no) { - struct dw_pcie_ep *ep =3D &pci->ep; unsigned int offset; unsigned int nbars; enum pci_barno bar; u32 reg, i, val; =20 - offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); - - dw_pcie_dbi_ro_wr_en(pci); + offset =3D dw_pcie_ep_find_ext_capability(ep, func_no, PCI_EXT_CAP_ID_REB= AR); =20 if (offset) { - reg =3D dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + reg =3D dw_pcie_ep_readl_dbi(ep, func_no, offset + PCI_REBAR_CTRL); nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, reg); =20 /* @@ -870,16 +874,28 @@ static void dw_pcie_ep_init_non_sticky_registers(stru= ct dw_pcie *pci) * the controller when RESBAR_CAP_REG is written, which * is why RESBAR_CAP_REG is written here. */ - val =3D dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + val =3D dw_pcie_ep_readl_dbi(ep, func_no, offset + PCI_REBAR_CTRL); bar =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, val); if (ep->epf_bar[bar]) pci_epc_bar_size_to_rebar_cap(ep->epf_bar[bar]->size, &val); else val =3D BIT(4); =20 - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, val); 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 08:25:56.8151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0347939a-3946-43ba-7adf-08de598fddcb X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR10MB4737 Content-Type: text/plain; charset="utf-8" The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support for DWC") added support for multiple PFs in the DWC driver, but the implementation was incomplete. It did not properly support MSI/MSI-X, as well as BAR and inbound ATU mapping for multiple PFs. The MSI/MSI-X issue was later fixed by commit 47a062609a30 ("PCI: designware-ep: Modify MSI and MSIX CAP way of finding") by introducing a per-PF struct dw_pcie_ep_func. However, even with both commits, the multiple PF support in the driver remains broken because BAR configuration and ATU mappings are managed globally in struct dw_pcie_ep, meaning all PFs share the same BAR-to-ATU mapping table. This causes one PF's EPF to overwrite the address translation of another PF's EPF in the internal ATU region, creating conflicts when multiple physical functions attempt to configure their BARs independently. Fix this by moving bar_to_atu and epf_bar from struct dw_pcie_ep to struct dw_pcie_ep_func, similar to what commit 47a062609a30 ("PCI: designware-ep: Modify MSI and MSIX CAP way of finding") did for MSI/MSI-X capability support, to allow proper multi-function endpoint operation, where each PF can configure its BARs and corresponding internal ATU region without interfering with other PFs. Fixes: 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support for DWC") Signed-off-by: Aksh Garg Reviewed-by: Niklas Cassel --- Link to v1: https://lore.kernel.org/all/20260121054214.274429-3-a-garg7@ti.com/ Changes from v1 to v2: - Fixed the suggested nits - Rephrased the commit message with a proper Fixes tag .../pci/controller/dwc/pcie-designware-ep.c | 46 ++++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 4 +- 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 1458477a6ba9..12625a1059a4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -153,11 +153,15 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *= ep, u8 func_no, int type, int ret; u32 free_win; struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + struct dw_pcie_ep_func *ep_func =3D dw_pcie_ep_get_func_from_ep(ep, func_= no); =20 - if (!ep->bar_to_atu[bar]) + if (!ep_func) + return -EINVAL; + + if (!ep_func->bar_to_atu[bar]) free_win =3D find_first_zero_bit(ep->ib_window_map, pci->num_ib_windows); else - free_win =3D ep->bar_to_atu[bar] - 1; + free_win =3D ep_func->bar_to_atu[bar] - 1; =20 if (free_win >=3D pci->num_ib_windows) { dev_err(pci->dev, "No free inbound window\n"); @@ -175,7 +179,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep= , u8 func_no, int type, * Always increment free_win before assignment, since value 0 is used to = identify * unallocated mapping. */ - ep->bar_to_atu[bar] =3D free_win + 1; + ep_func->bar_to_atu[bar] =3D free_win + 1; set_bit(free_win, ep->ib_window_map); =20 return 0; @@ -211,17 +215,18 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc,= u8 func_no, u8 vfunc_no, struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); enum pci_barno bar =3D epf_bar->barno; - u32 atu_index =3D ep->bar_to_atu[bar] - 1; + struct dw_pcie_ep_func *ep_func =3D dw_pcie_ep_get_func_from_ep(ep, func_= no); + u32 atu_index =3D ep_func->bar_to_atu[bar] - 1; =20 - if (!ep->bar_to_atu[bar]) + if (!ep_func || !ep_func->bar_to_atu[bar]) return; =20 __dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags); =20 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index); clear_bit(atu_index, ep->ib_window_map); - ep->epf_bar[bar] =3D NULL; - ep->bar_to_atu[bar] =3D 0; + ep_func->epf_bar[bar] =3D NULL; + ep_func->bar_to_atu[bar] =3D 0; } =20 static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie_ep *ep, u8 = func_no, @@ -348,12 +353,16 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8= func_no, u8 vfunc_no, { struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + struct dw_pcie_ep_func *ep_func =3D dw_pcie_ep_get_func_from_ep(ep, func_= no); enum pci_barno bar =3D epf_bar->barno; size_t size =3D epf_bar->size; enum pci_epc_bar_type bar_type; int flags =3D epf_bar->flags; int ret, type; =20 + if (!ep_func) + return -EINVAL; + /* * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs * 1 and 2 to form a 64-bit BAR. @@ -367,14 +376,14 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8= func_no, u8 vfunc_no, * calling clear_bar() would clear the BAR's PCI address assigned by the * host). */ - if (ep->epf_bar[bar]) { + if (ep_func->epf_bar[bar]) { /* * We can only dynamically change a BAR if the new BAR size and * BAR flags do not differ from the existing configuration. */ - if (ep->epf_bar[bar]->barno !=3D bar || - ep->epf_bar[bar]->size !=3D size || - ep->epf_bar[bar]->flags !=3D flags) + if (ep_func->epf_bar[bar]->barno !=3D bar || + ep_func->epf_bar[bar]->size !=3D size || + ep_func->epf_bar[bar]->flags !=3D flags) return -EINVAL; =20 /* @@ -420,7 +429,7 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 f= unc_no, u8 vfunc_no, if (ret) return ret; =20 - ep->epf_bar[bar] =3D epf_bar; + ep_func->epf_bar[bar] =3D epf_bar; =20 return 0; } @@ -782,7 +791,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8= func_no, bir =3D FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); tbl_offset &=3D PCI_MSIX_TABLE_OFFSET; =20 - msix_tbl =3D ep->epf_bar[bir]->addr + tbl_offset; + msix_tbl =3D ep_func->epf_bar[bir]->addr + tbl_offset; msg_addr =3D msix_tbl[(interrupt_num - 1)].msg_addr; msg_data =3D msix_tbl[(interrupt_num - 1)].msg_data; vec_ctrl =3D msix_tbl[(interrupt_num - 1)].vector_ctrl; @@ -845,11 +854,14 @@ EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); =20 static void __dw_pcie_ep_init_non_sticky_registers(struct dw_pcie_ep *ep, = u8 func_no) { - unsigned int offset; - unsigned int nbars; + struct dw_pcie_ep_func *ep_func =3D dw_pcie_ep_get_func_from_ep(ep, func_= no); + unsigned int offset, nbars; enum pci_barno bar; u32 reg, i, val; =20 + if (!ep_func) + return; + offset =3D dw_pcie_ep_find_ext_capability(ep, func_no, PCI_EXT_CAP_ID_REB= AR); =20 if (offset) { @@ -876,8 +888,8 @@ static void __dw_pcie_ep_init_non_sticky_registers(stru= ct dw_pcie_ep *ep, u8 fun */ val =3D dw_pcie_ep_readl_dbi(ep, func_no, offset + PCI_REBAR_CTRL); bar =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, val); - if (ep->epf_bar[bar]) - pci_epc_bar_size_to_rebar_cap(ep->epf_bar[bar]->size, &val); + if (ep_func->epf_bar[bar]) + pci_epc_bar_size_to_rebar_cap(ep_func->epf_bar[bar]->size, &val); else val =3D BIT(4); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 31685951a080..a4d1733f5c6a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -463,6 +463,8 @@ struct dw_pcie_ep_func { u8 func_no; u8 msi_cap; /* MSI capability offset */ u8 msix_cap; /* MSI-X capability offset */ + u8 bar_to_atu[PCI_STD_NUM_BARS]; + struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 08:26:01.2617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc01d4ca-b112-48c8-ec91-08de598fe06b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB6326 Content-Type: text/plain; charset="utf-8" PCIe r6.0, section 7.9.15 requires PTM capability in exactly one function to control all PTM-capable functions. This makes PTM registers controller-level rather than per-function. As suggested by Niklas Cassel, add a comment explaining why PTM capability registers are accessed using the standard DBI accessors instead of func_no indexed per-function accessors. Suggested-by: Niklas Cassel Signed-off-by: Aksh Garg Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-designware-ep.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 12625a1059a4..0a9d5402f23a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -995,6 +995,17 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) if (ep->ops->init) ep->ops->init(ep); =20 + /* + * PCIe r6.0, section 7.9.15 states that for endpoints that support PTM, + * this capability structure is required in exactly one function, which + * controls the PTM behavior of all PTM capable functions. This indicates + * the PTM capability structure represents controller-level registers + * rather than per-function registers. + * + * Therefore, PTM capability registers are configured using the standard = DBI + * accessors, instead of func_no indexed per-function accessors. + */ + ptm_cap_base =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); =20 /* --=20 2.34.1