From nobody Sat Feb 7 18:46:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17E8D36997D for ; Thu, 22 Jan 2026 01:51:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769046695; cv=none; b=thf6aZNNqOwpYhAQh/ZrY+CLKfE/azSjkZdprddyInJsWXQKRFbAyXhKhkNuch6+JGKwoIaCYn1CP7/YEohYKXi3DHXDf0kHHZ8WGMlVCtyAzShPSulk5NYqBDGVYnMsMbeqVW3inOX1sZ13c+6wv2S95OUUjydgPGDrVn+o80I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769046695; c=relaxed/simple; bh=f/2d1fGzDtMdu8PeYLJCG0hCit54tFui1Ge4r9D7pqk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ipFf4CpPBitSaVG9jmwUttknbLROKyuNmdML9/P8fFuQZUCR9BXmGKHxC+ojyBc3n5tOnHj3kwfYqTGSEcDrWRjJflj4xcB5Mpwph0aQI2tGWPQx9KZs/tSjah8oYiYbEshURxoa0FC2uYPn5inL0C1ywfW7fJNzbdBRjLPgGw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FP0YExDJ; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FP0YExDJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769046693; x=1800582693; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f/2d1fGzDtMdu8PeYLJCG0hCit54tFui1Ge4r9D7pqk=; b=FP0YExDJh5Xhq8CQrZ2PyTetopTWQpwGyiK23EysySTLvMdZYeaC9kTq 8oRqvQWnkXkgjpbgSIKHDF7/pe8ATIGvpyMfpEyi3+bh2qKpu42au0EsC d49HwRLnc4MkYS9EIzLtszjJIhvCAim4t5agYZnc0jZXy9dip+qHlw/sW K+E0wkuFOZPPd9UOMXclh5k80SycXP6gffrOYOlmsvJTBBvNQBNlst4Gd NcJ5nLrZLDuf/wbYTaERwx9/LS2yFgSkbbdzOVFhJwGuaD6/uSlsffMO8 JccJDIvJZ8K2MDwiTjux1883sQwVtVjRxcaOgYsp0Nf3UmwFtzInskhnh g==; X-CSE-ConnectionGUID: NNpPARWxSDyXHXdTnn+5zA== X-CSE-MsgGUID: gAy9D+QOToWHoEB4o8UTBg== X-IronPort-AV: E=McAfee;i="6800,10657,11678"; a="81393054" X-IronPort-AV: E=Sophos;i="6.21,244,1763452800"; d="scan'208";a="81393054" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2026 17:51:33 -0800 X-CSE-ConnectionGUID: Ffgv696ITwWg+LI3yc/Dkg== X-CSE-MsgGUID: DoyKMvuNRFiE07FNxp+dEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,244,1763452800"; d="scan'208";a="211455644" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa004.fm.intel.com with ESMTP; 21 Jan 2026 17:51:31 -0800 From: Lu Baolu To: Joerg Roedel Cc: Yi Liu , Dmytro Maluka , Jinhui Guo , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] iommu/vt-d: Clear Present bit before tearing down PASID entry Date: Thu, 22 Jan 2026 09:48:54 +0800 Message-ID: <20260122014856.2457052-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260122014856.2457052-1-baolu.lu@linux.intel.com> References: <20260122014856.2457052-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64 bytes). When tearing down an entry, the current implementation zeros the entire 64-byte structure immediately using multiple 64-bit writes. Since the IOMMU hardware may fetch these 64 bytes using multiple internal transactions (e.g., four 128-bit bursts), updating or zeroing the entire entry while it is active (P=3D1) risks a "torn" read. If a hardware fetch occurs simultaneously with the CPU zeroing the entry, the hardware could observe an inconsistent state, leading to unpredictable behavior or spurious faults. Follow the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the PASID entry. 2. Use a dma_wmb() to ensure the cleared bit is visible to hardware before proceeding. 3. Execute the required invalidation sequence (PASID cache, IOTLB, and Device-TLB flush) to ensure the hardware has released all cached references. 4. Only after the flushes are complete, zero out the remaining fields of the PASID entry. Also, add a dma_wmb() in pasid_set_present() to ensure that all other fields of the PASID entry are visible to the hardware before the Present bit is set. Fixes: 0bbeb01a4faf ("iommu/vt-d: Manage scalalble mode PASID tables") Signed-off-by: Lu Baolu Reviewed-by: Dmytro Maluka Reviewed-by: Samiullah Khawaja Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20260120061816.2132558-2-baolu.lu@linux.int= el.com --- drivers/iommu/intel/pasid.h | 14 ++++++++++++++ drivers/iommu/intel/pasid.c | 6 +++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index b4c85242dc79..0b303bd0b0c1 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -234,9 +234,23 @@ static inline void pasid_set_wpe(struct pasid_entry *p= e) */ static inline void pasid_set_present(struct pasid_entry *pe) { + dma_wmb(); pasid_set_bits(&pe->val[0], 1 << 0, 1); } =20 +/* + * Clear the Present (P) bit (bit 0) of a scalable-mode PASID table entry. + * This initiates the transition of the entry's ownership from hardware + * to software. The caller is responsible for fulfilling the invalidation + * handshake recommended by the VT-d spec, Section 6.5.3.3 (Guidance to + * Software for Invalidations). + */ +static inline void pasid_clear_present(struct pasid_entry *pe) +{ + pasid_set_bits(&pe->val[0], 1 << 0, 0); + dma_wmb(); +} + /* * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID * entry. diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 6379b211f12b..07e056b24605 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -273,7 +273,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *io= mmu, struct device *dev, =20 did =3D pasid_get_domain_id(pte); pgtt =3D pasid_pte_get_pgtt(pte); - intel_pasid_clear_entry(dev, pasid, fault_ignore); + pasid_clear_present(pte); spin_unlock(&iommu->lock); =20 if (!ecap_coherent(iommu->ecap)) @@ -287,6 +287,10 @@ void intel_pasid_tear_down_entry(struct intel_iommu *i= ommu, struct device *dev, iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); =20 devtlb_invalidation_with_pasid(iommu, dev, pasid); + intel_pasid_clear_entry(dev, pasid, fault_ignore); + if (!ecap_coherent(iommu->ecap)) + clflush_cache_range(pte, sizeof(*pte)); + if (!fault_ignore) intel_iommu_drain_pasid_prq(dev, pasid); } --=20 2.43.0