From nobody Tue Feb 10 04:08:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72909376BF2 for ; Thu, 22 Jan 2026 15:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769095481; cv=none; b=kq0H216y0XK2gUiOzjzEITvYR0AdSPtCe08r1bWehV9ss3m6BvOSn4jBhvaP1PE5fzWlyatMeMfwRQIRQPEs6UT1/AjyLT9zOnWAqxK5MriEsX5yu2GBHWOrzz4B45J3c8DUBS9KLdF1+gxY5nS+Px5fBqgtlgOKLlC/L3HcrQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769095481; c=relaxed/simple; bh=ambWn6BPEM9noI2YgN2DEgnT09MrEAbBEsjm+bNXegs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s7d5oURFLMmVKjIXD6Do4J1OppODi6uq8go7eTHeHLgfl/Zwjd4BgXRLgFctTSu+81G7nGdiEXfHN8c7cMtBA0V/XRlzwdO5yUAfdMf9Aq36f+GVpIHhMT2VhDrhxcyF6/sFm/ogWT+LVHSVRuocbllDzT8QM4JPd9Sq8tbM14Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=XKTXuoIi; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ECTWD2vV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="XKTXuoIi"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ECTWD2vV" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60M84gPM791167 for ; Thu, 22 Jan 2026 15:24:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= oib0Qq6Eu4yjjcomjdAD6V5SUj5uTqEB4e84Fizw54k=; b=XKTXuoIi1+Il5jSQ b+ztvsh7qEE4KR8rSoKvlJ/usCqXPzVaKM5luY1VHv6tpzzwSmDB60H2yszte+YK 67s3PxrA1IPOSayioitM8/qSOYsyQ9bKFuKZk0xZhOEuQHJq0qKL6V0o1LyMSANM 9FC/jAueHiY4EV5KSvz0hReo3Z1O9DOjvNhOLj2z/CBJHf62OY46m/03ip04UBZk k60wrpl+xQHDIfIapXYXQr+n5w6dzUwfdat9yVSFAUiV3tAjYEFGQzUZRWWR7QW1 PJj4qAahdN3+fLz3pXU/KGuZN/ehNP0KUntWIFxbIBl06dBCgOfUnuOZ+q2B3x/t NkZFIg== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bu6p1jx98-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 22 Jan 2026 15:24:35 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-81f42368322so895669b3a.3 for ; Thu, 22 Jan 2026 07:24:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769095475; x=1769700275; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oib0Qq6Eu4yjjcomjdAD6V5SUj5uTqEB4e84Fizw54k=; b=ECTWD2vVLanh89wDykj3eM+1iPDN0YfknPclgjZTKGR16nPUz7kIUhPYt/ZdOTqaZz xVQunYdHG/ZboTmKF9GzSG5oopYnhI6ZJHAQnsw6q3uxlZrQeqeLpKR1TK479tNRnxEY +j8kBgb0ixX+xKbuz/ZJvxLbLqFt+rGH/ZHsELwN7q+Vx/kIofe3VTW3UE1JEdVQ/IpK G6gAvkmS64Tuo/k8QCkjWJNs0g+HkvkpKA5WoeKGXgB+KkZT0oV94JIipn+geo2YB5Vg bTKZfyjWKFcFG7AUBsDPWKcUl+nnNlx8j4LolVWNLxCMIepaSgbawLysIZnLd2HCdjTq NYww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769095475; x=1769700275; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=oib0Qq6Eu4yjjcomjdAD6V5SUj5uTqEB4e84Fizw54k=; b=Ia5J4+8cJZ7PgkAyKPym5+ylLwKB9ap8ExF+B3nY5qQI6oDnrdzXSS4mqImbkali6y vi3kcD3Mb0TjOQ8SN3mOf+3WvY4ADSc5PkP3Mlq7of4R4g5ttbvI3BobIRG/m3f0V4Js g+NT3RMTVkOJ2Q+ZtI6O4LfNerb8UT0mHzW8n83GAkqMG5xiCaLp6kfo9TQoUHh63zCo AzEh7bUmndWQs+5LLi2C1tZUBD58OZd8kPrNzkqDaBD10UsI5mQKJfTKvKhY90iVPTw6 Ov0Q6swOiwh3fCTam1EpUveOKI4gBj8gJ1rLybVD65mHMIOAlI67SWiu2KcNgdloOWd3 n5fQ== X-Forwarded-Encrypted: i=1; AJvYcCWev/jS7pSboWqwVz85taRjrOrKONAs2GltS3ti+7qWa/gLs5uqR04nvLBtnWjyukRaaSI5PGgqjFfDCTk=@vger.kernel.org X-Gm-Message-State: AOJu0Yz6l8/C2Fd9DcqrqAChe9YIpUPo4dFOeSMHo2uL3THKibdsnAUY MsLqbgEzW4rO62E1TjKrjqhTUatkHzCmAHyZg1xp7KhtG76XXBUbVhKmYRPhY5yUGYNabUIOMp4 elJhN2Rz+lqIK94ecHWIJIJfoeBelqf/Er7s/Gn5fFfuEKcwS/IdJBBTJp5CvFY64VyU= X-Gm-Gg: AZuq6aJ/TUUuvx6x0Bc7uc0TC6YJ4pnJN88W47ovE4PoqAxquYnod+R9YuIhs56v2F8 2+sTXL5E73YOzSGy/ggXy1vRmmBuwB7Xn7EZFvc7kRz5WTvFM2Y22OIJjh4q6jf/acphrJjAkLj 6ytoj2SyfTjqcasENqDng7mVDqq/brv1LpXtlG54Pfn+VZ5TMCMn1k0peBU6qAqwx8yQWWR5+Lv tsIWXToLhJXlUACHn0zAOeU8AwFl5RvMiiP6x6bSkghg/8hgEzrts/l52pYlZJZTnJ+PpdmC0sq DTYmrnrUoKC9AjBxLXys0Y2qZJ7jjA1bEvW2yaXXHJrS5L9NNoEISxEkOD6M9hhh8tnR3pfrLGc /90dFJN3Y3spcRoP0Hym8+fMTeM/l9lUFBrpn2kwi3Ht8p/v7JICwdmpwJ+aAbw8OmWfItfuoMJ 7MZixwJuVvWWgMfgENcudlXa39A3jqnw== X-Received: by 2002:a05:6a00:ad81:b0:823:bbb:770e with SMTP id d2e1a72fcca58-8230bbb7b2amr1235217b3a.65.1769095474663; Thu, 22 Jan 2026 07:24:34 -0800 (PST) X-Received: by 2002:a05:6a00:ad81:b0:823:bbb:770e with SMTP id d2e1a72fcca58-8230bbb7b2amr1235187b3a.65.1769095473839; Thu, 22 Jan 2026 07:24:33 -0800 (PST) Received: from hu-pankpati-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82180636c38sm3743474b3a.24.2026.01.22.07.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 07:24:33 -0800 (PST) From: Pankaj Patil Date: Thu, 22 Jan 2026 20:54:01 +0530 Subject: [PATCH v6 4/4] arm64: dts: qcom: glymur: Enable Glymur CRD board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-upstream_v3_glymur_introduction-v6-4-245f408ed82a@oss.qualcomm.com> References: <20260122-upstream_v3_glymur_introduction-v6-0-245f408ed82a@oss.qualcomm.com> In-Reply-To: <20260122-upstream_v3_glymur_introduction-v6-0-245f408ed82a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , Kamal Wadhwa , Qiang Yu , Sibi Sankar , Jyothi Kumar Seerapu , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769095452; l=16745; i=pankaj.patil@oss.qualcomm.com; s=20251121; h=from:subject:message-id; bh=ambWn6BPEM9noI2YgN2DEgnT09MrEAbBEsjm+bNXegs=; b=VPaWZk9VytqlD1Upw2cjFVQ+XwSaMZJE/hTXIzDi18eRZZtDbXPXX3wbpCzj3QQ29fNsccnKN iug+Lflq6tDBjzGOyEZv6aKJZPW/lx+779UNx1Ij/GIISNZJPaWGuVj X-Developer-Key: i=pankaj.patil@oss.qualcomm.com; a=ed25519; pk=pWpEq/tlX6TaKH1UQolvxjRD+Vdib/sEkb8bH8AL6gc= X-Proofpoint-ORIG-GUID: SDsiOBD4Tdew_Yk9QZQq51zFuwophX3G X-Authority-Analysis: v=2.4 cv=N7ck1m9B c=1 sm=1 tr=0 ts=69724134 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=meRCxBnBdMAtXdFtBwMA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: SDsiOBD4Tdew_Yk9QZQq51zFuwophX3G X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDExNyBTYWx0ZWRfX+7ziF1DY9nWQ ixuWxKGH6zn/wJ8i9NttfE60ox3kIRjUzs3ufbbpH4+CghBACJC79BhUcrSzlERXuLtn+YFuWcm 5yrVMMm/VE9oj0CBT1iOX6EJPc8HaorzPUbdR33ok+sXUK9K9uONcYY2bHxmaqdYCUKHwbu6GQc e/tWswxJmWHaj9zfwXxOwML5eoCR/Z+0WDg4Mo2MrcrIU8aZup5KjHoolpzpkgMhU8dUCEBewCe Ykui7xyF2IeFZ9HbuTPi/qQYeyNUXU1pdWoaa0Y57aCEr+MzhSgVSSI0G5RZtvA920giFQ9AIIx 9JSaZp1HbZHJDReODSqibJp0SUqtjzI8OWApUdZONwI/xLXZJk0uRhaw+Wdt2fZYp0KqGsIfT+Y SsocKDmZuS9XmuE3bON/SisFIo3sbLH7Z197VCOA1uw83kwgpnhe1JEX0HpoHclSh9i3/LYG/kb E7wdeu/PC9zyXkQZCkg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_02,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601220117 Add initial device tree support for the Glymur Compute Reference Device(CRD) board, with this board dts glymur crd can boot to shell with rootfs on nvme and uart21 as serial console Features enabled are: - Board and sleep clocks - Volume up/down keys - Regulators 0 - 4 - Power supplies and sideband signals (PERST, WAKE, CLKREQ) for PCIe3b/4/5/6 controllers and PHYs Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur-crd.dts | 601 ++++++++++++++++++++++++++++= ++++ 2 files changed, 602 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index a5d6f451f85c..c24ade85b73a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts new file mode 100644 index 000000000000..0899214465ac --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -0,0 +1,601 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "glymur.dtsi" +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +/ { + model =3D "Qualcomm Technologies, Inc. Glymur CRD"; + compatible =3D "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 =3D &uart21; + serial1 =3D &uart14; + i2c0 =3D &i2c0; + i2c1 =3D &i2c4; + i2c2 =3D &i2c5; + spi0 =3D &spi18; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&key_vol_up_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vreg_nvme: regulator-nvme { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_nvmesec: regulator-nvmesec { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_SEC_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_sec_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_wlan: regulator-wlan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WLAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wlan_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WWAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wwan_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id =3D "B_E0"; + + vreg_bob1_e0: bob1 { + regulator-name =3D "vreg_bob1_e0"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <4224000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2_e0: bob2 { + regulator-name =3D "vreg_bob2_e0"; + regulator-min-microvolt =3D <2540000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name =3D "vreg_l1b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name =3D "vreg_l2b_e0_2p9"; + regulator-min-microvolt =3D <2904000>; + regulator-max-microvolt =3D <2904000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name =3D "vreg_l7b_e0_2p79"; + regulator-min-microvolt =3D <2790000>; + regulator-max-microvolt =3D <2792000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name =3D "vreg_l8b_e0_1p50"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name =3D "vreg_l9b_e0_2p7"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <2704000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name =3D "vreg_l10b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name =3D "vreg_l11b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name =3D "vreg_l12b_e0_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name =3D "vreg_l15b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name =3D "vreg_l17b_e0_2p4"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name =3D "vreg_l18b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id =3D "C_E1"; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1c_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name =3D "vreg_l2c_e1_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name =3D "vreg_l3c_e1_0p89"; + regulator-min-microvolt =3D <890000>; + regulator-max-microvolt =3D <980000>; + regulator-initial-mode =3D ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name =3D "vreg_l4c_e1_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_s7f_e0_1p32: smps7 { + regulator-name =3D "vreg_s7f_e0_1p32"; + regulator-min-microvolt =3D <1320000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name =3D "vreg_s8f_e0_0p95"; + regulator-min-microvolt =3D <952000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name =3D "vreg_s9f_e0_1p9"; + regulator-min-microvolt =3D <1900000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name =3D "vreg_l2f_e0_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name =3D "vreg_l3f_e0_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name =3D "vreg_l4f_e0_0p3"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E1"; + + vreg_s7f_e1_0p3: smps7 { + regulator-name =3D "vreg_s7f_e1_0p3"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1f_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name =3D "vreg_l2f_e1_0p83"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name =3D "vreg_l4f_e1_1p08"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "H_E0"; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name =3D "vreg_l1h_e0_0p89"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name =3D "vreg_l2h_e0_0p72"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name =3D "vreg_l3h_e0_0p32"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name =3D "vreg_l4h_e0_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&pcie3b { + vddpe-3v3-supply =3D <&vreg_nvmesec>; + + pinctrl-0 =3D <&pcie3b_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3b_phy { + vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; + vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; + + status =3D "okay"; +}; + +&pcie3b_port0 { + reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + vddpe-3v3-supply =3D <&vreg_wlan>; + + pinctrl-0 =3D <&pcie4_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie5 { + vddpe-3v3-supply =3D <&vreg_nvme>; + + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l2f_e0_0p82>; + vdda-pll-supply =3D <&vreg_l4h_e0_1p2>; + + status =3D "okay"; +}; + +&pcie5_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply =3D <&vreg_wwan>; + + pinctrl-0 =3D <&pcie6_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie6_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie6_port0 { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio153"; + function =3D "pcie5_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio152"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio154"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie6_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio149"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins =3D "gpio156"; + function =3D "pcie3b_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio155"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio157"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wlan_reg_en: wlan-reg-en-state { + pins =3D "gpio94"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins =3D "gpio246"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + --=20 2.34.1