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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190eeefasm159551305ad.43.2026.01.21.10.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jan 2026 10:36:25 -0800 (PST) From: Pankaj Patil Date: Thu, 22 Jan 2026 00:05:14 +0530 Subject: [PATCH v5 4/4] arm64: dts: qcom: glymur: Enable Glymur CRD board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-upstream_v3_glymur_introduction-v5-4-8ba76c354e9a@oss.qualcomm.com> References: <20260122-upstream_v3_glymur_introduction-v5-0-8ba76c354e9a@oss.qualcomm.com> In-Reply-To: <20260122-upstream_v3_glymur_introduction-v5-0-8ba76c354e9a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , Kamal Wadhwa , Qiang Yu , Sibi Sankar , Jyothi Kumar Seerapu , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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+ +#include "glymur.dtsi" +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +/ { + model =3D "Qualcomm Technologies, Inc. Glymur CRD"; + compatible =3D "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 =3D &uart21; + serial1 =3D &uart14; + i2c0 =3D &i2c0; + i2c1 =3D &i2c4; + i2c2 =3D &i2c5; + spi0 =3D &spi18; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&key_vol_up_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vreg_nvme: regulator-nvme { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_nvmesec: regulator-nvmesec { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_SEC_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_sec_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_wlan: regulator-wlan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WLAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wlan_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WWAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wwan_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id =3D "B_E0"; + + vreg_bob1_e0: bob1 { + regulator-name =3D "vreg_bob1_e0"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <4224000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2_e0: bob2 { + regulator-name =3D "vreg_bob2_e0"; + regulator-min-microvolt =3D <2540000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name =3D "vreg_l1b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name =3D "vreg_l2b_e0_2p9"; + regulator-min-microvolt =3D <2904000>; + regulator-max-microvolt =3D <2904000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name =3D "vreg_l7b_e0_2p79"; + regulator-min-microvolt =3D <2790000>; + regulator-max-microvolt =3D <2792000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name =3D "vreg_l8b_e0_1p50"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name =3D "vreg_l9b_e0_2p7"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <2704000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name =3D "vreg_l10b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name =3D "vreg_l11b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name =3D "vreg_l12b_e0_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name =3D "vreg_l15b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name =3D "vreg_l17b_e0_2p4"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name =3D "vreg_l18b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id =3D "C_E1"; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1c_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name =3D "vreg_l2c_e1_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name =3D "vreg_l3c_e1_0p89"; + regulator-min-microvolt =3D <890000>; + regulator-max-microvolt =3D <980000>; + regulator-initial-mode =3D ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name =3D "vreg_l4c_e1_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_s7f_e0_1p32: smps7 { + regulator-name =3D "vreg_s7f_e0_1p32"; + regulator-min-microvolt =3D <1320000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name =3D "vreg_s8f_e0_0p95"; + regulator-min-microvolt =3D <952000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name =3D "vreg_s9f_e0_1p9"; + regulator-min-microvolt =3D <1900000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name =3D "vreg_l2f_e0_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name =3D "vreg_l3f_e0_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name =3D "vreg_l4f_e0_0p3"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E1"; + + vreg_s7f_e1_0p3: smps7 { + regulator-name =3D "vreg_s7f_e1_0p3"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1f_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name =3D "vreg_l2f_e1_0p83"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name =3D "vreg_l4f_e1_1p08"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "H_E0"; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name =3D "vreg_l1h_e0_0p89"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name =3D "vreg_l2h_e0_0p72"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name =3D "vreg_l3h_e0_0p32"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name =3D "vreg_l4h_e0_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&pcie3b { + vddpe-3v3-supply =3D <&vreg_nvmesec>; + + pinctrl-0 =3D <&pcie3b_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3b_phy { + vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; + vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; + + status =3D "okay"; +}; + +&pcie3b_port0 { + reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + vddpe-3v3-supply =3D <&vreg_wlan>; + + pinctrl-0 =3D <&pcie4_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie5 { + vddpe-3v3-supply =3D <&vreg_nvme>; + + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l2f_e0_0p82>; + vdda-pll-supply =3D <&vreg_l4h_e0_1p2>; + + status =3D "okay"; +}; + +&pcie5_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply =3D <&vreg_wwan>; + + pinctrl-0 =3D <&pcie6_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie6_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie6_port0 { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio153"; + function =3D "pcie5_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio152"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio154"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie6_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio149"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins =3D "gpio156"; + function =3D "pcie3b_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio155"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio157"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wlan_reg_en: wlan-reg-en-state { + pins =3D "gpio94"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins =3D "gpio246"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + --=20 2.34.1