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Thu, 22 Jan 2026 09:54:31 -0800 (PST) From: Charan Pedumuru Date: Thu, 22 Jan 2026 17:52:58 +0000 Subject: [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-ti-phy-v3-2-751619729433@gmail.com> References: <20260122-ti-phy-v3-0-751619729433@gmail.com> In-Reply-To: <20260122-ti-phy-v3-0-751619729433@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren , Roger Quadros Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Charan Pedumuru X-Mailer: b4 0.14.3 Convert TI PIPE3 PHY binding to DT schema. Changes during conversion: - Define a new pattern 'pcie-phy' to match nodes defined in DT. - Drop obsolete "id" property from the schema. Signed-off-by: Charan Pedumuru --- .../devicetree/bindings/phy/ti,phy-usb3.yaml | 135 +++++++++++++++++= ++++ 1 file changed, 135 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Docum= entation/devicetree/bindings/phy/ti,phy-usb3.yaml new file mode 100644 index 000000000000..605f12f0f79a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI PIPE3 PHY Module + +maintainers: + - Roger Quadros + +description: + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer) + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs. + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3 + interface standard, which defines a common physical layer for + high-speed serial interfaces. + +properties: + $nodename: + pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$" + + compatible: + enum: + - ti,omap-usb3 + - ti,phy-pipe3-pcie + - ti,phy-pipe3-sata + - ti,phy-usb3 + + reg: + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + items: + - const: phy_rx + - const: phy_tx + - const: pll_ctrl + + "#phy-cells": + const: 0 + + clocks: + minItems: 2 + maxItems: 7 + + clock-names: + minItems: 2 + maxItems: 7 + items: + enum: [wkupclk, sysclk, refclk, dpll_ref, + dpll_ref_m2, phy-div, div-clk] + + syscon-phy-power: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle to the system control module + - description: Register offset controlling PHY power + + syscon-pllreset: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle to the system control module + - description: Register offset of CTRL_CORE_SMA_SW_0 + + syscon-pcs: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle to the system control module + - description: Register offset for PCS delay programming + + ctrl-module: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of control module for PHY power on. + deprecated: true + +allOf: + - if: + properties: + compatible: + contains: + const: ti,phy-pipe3-sata + then: + properties: + syscon-pllreset: true + else: + properties: + syscon-pllreset: false + +required: + - reg + - compatible + - reg-names + - "#phy-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + /* TI PIPE3 USB3 PHY */ + usb3-phy@4a084400 { + compatible =3D "ti,phy-usb3"; + reg =3D <0x4a084400 0x80>, + <0x4a084800 0x64>, + <0x4a084c00 0x40>; + reg-names =3D "phy_rx", "phy_tx", "pll_ctrl"; + #phy-cells =3D <0>; + clocks =3D <&usb_phy_cm_clk32k>, + <&sys_clkin>, + <&usb_otg_ss_refclk960m>; + clock-names =3D "wkupclk", "sysclk", "refclk"; + ctrl-module =3D <&omap_control_usb>; + }; + + - | + /* TI PIPE3 SATA PHY */ + phy@4a096000 { + compatible =3D "ti,phy-pipe3-sata"; + reg =3D <0x4A096000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names =3D "phy_rx", "phy_tx", "pll_ctrl"; + clocks =3D <&sys_clkin1>, <&sata_ref_clk>; + clock-names =3D "sysclk", "refclk"; + syscon-pllreset =3D <&scm_conf 0x3fc>; + #phy-cells =3D <0>; + }; +... --=20 2.52.0