From nobody Wed Feb 11 03:44:17 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7EE538BDC4 for ; Thu, 22 Jan 2026 15:14:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769094870; cv=none; b=mu/MV6T3noJ6axRiPBtm9V8bTTmDkDL9GR6CCrHuJ5qWkkGIyVBAPBDKGwmRAkQMkU5vOEO00OP9iM7Oz8IFrOtFYNF5I4U0qUEV2m5j8Gyt6Lj3+dYj5zyAPlVOlMWY5tfsj3RhBJHbi8txyoOjgwoGgtz+85ARQ1ljOfWGFBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769094870; c=relaxed/simple; bh=Kp1EiYbHl52gcoo53/+Mm7ZQjp2iu07iybEcu+QABEU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Qc6N6GE1Y9FzNo0pUfX6VzfxoR/nRje/aq/aPMhzzRJZEUfmBZoG6KssSU4OhAjtr1SUvEzXlfQX+BWizec25LK+cK1ds9A32zqGmh6fq807dBpDs2o0JgfGVGK8XsE9phOgL0gppI2n++jEDTMI6ln7cCJvSasZXxrffkWyImY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=V+2jLvOd; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="V+2jLvOd" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 028C7C21AA8; Thu, 22 Jan 2026 15:14:26 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 293E8606B6; Thu, 22 Jan 2026 15:14:26 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 87BE9119B82E7; Thu, 22 Jan 2026 16:14:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769094865; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=WccFrzV37pjQDcMtab7f2QieezsSKecv42H/QrPd54o=; b=V+2jLvOdCIbZ3VSaeMDssSrE0IPLb+HflOJb2HR4mDdrM7tEtG937icwwRl0lAKNJE72zR 62AMP8zsILL7o1iu5ktQC7/+KHZl69WYh5BwQ7Ip1crpsFa8zBlZxFvgUO4LACDv7iSwmD 46TUpWkZcBiLOdbaLJGyJlmR2tjTXzoeIZCWcsBMt6uoTVtTbI80pBx9CB6qAogTR7cHpL WGwvjjAiiXltTvfS8p1xH+o5BPDtZrg7L7FPzz9C8vuCBxxn5pNWe5YJI7GaS4CnDLK1Ke IGWSovky8mD0QBsWIPNVj1pfG0PoqaLr5Ed7Npk/kDa/CaIDl+tEV0ebWGAKtw== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 22 Jan 2026 16:13:40 +0100 Subject: [PATCH v4 15/15] ARM: dts: r9a06g032: Describe the QSPI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-schneider-6-19-rc1-qspi-v4-15-f9c21419a3e6@bootlin.com> References: <20260122-schneider-6-19-rc1-qspi-v4-0-f9c21419a3e6@bootlin.com> In-Reply-To: <20260122-schneider-6-19-rc1-qspi-v4-0-f9c21419a3e6@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a node describing the QSPI controller. There are 2 clocks feeding this controller: - one for the reference clock - one that feeds both the ahb and the apb interfaces As the binding expect either the ref clock, or all three (ref, ahb and apb) clocks, it makes sense to provide the same clock twice. Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 8debb77803bb..47143e6636d2 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -66,6 +66,18 @@ soc { #size-cells =3D <1>; ranges; =20 + qspi0: spi@40005000 { + compatible =3D "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; + reg =3D <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts =3D ; + clocks =3D <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSP= I0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names =3D "ref", "ahb", "apb"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + rtc0: rtc@40006000 { compatible =3D "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg =3D <0x40006000 0x1000>; --=20 2.51.1